DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 2/19/26.
Applicant’s amendment to claim 9 is acknowledged.
Applicant’s addition of new claim 21 is acknowledged.
Claim 8 is cancelled.
Claims 1-7 and 9-21 are pending and subject to examination at this time.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-7, 9-14 and 16-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee, US Publication No. 2024/0021591 A1.
In a first interpretation-
Lee anticipates:
1. A semiconductor package assembly comprising (see fig. 5; and element labels in fig. 2A):
a package interface (13 and/or 32 and/or 131);
an interposer die (22) having a first surface (e.g. bottom surface) and a second surface (e.g. top surface) opposite to the first surface, the first surface of the interposer die positioned on the package interface, the interposer die (22) including a plurality of conductive connections (223, 220, 225 as labeled in fig. 2A) between the first surface and second surface; and
a chiplet (24) including a connectivity region (243) having conducive pathways, with a first portion (e.g. 243 overlapping 22) of the connectivity region coupled to a conductive connection of the interposer die (22) and a second portion (e.g. 243 non-overlapping 22) of the connectivity region cantilevered from the interposer die, wherein the chiplet (24) is bonded to the second surface of the interposer die (22) via hybrid bonding (e.g. see hybrid bond at para. [0042]). See Lee at para. [0001] – [0117], figs. 1-7.
2. The semiconductor package assembly of claim 1 further comprising:
a spacer interconnect (20 or 21) placed between the second portion (e.g. 243 non-overlapping 22) of the connectivity region (243) of the chiplet (24) and the package interface (13 and/or 32), the spacer interconnect (20 or 21) including spacer conductive connections (203/200, 213/210) coupling conductive pathways of the second portion of the connectivity region (243) to one or more connections within the package interface (13 and/or 32 and/or 131), fig. 5.
4. The semiconductor package assembly of claim 2, wherein
a diameter of the spacer conductive connections (203/200, 213/210) is different than a diameter of a connector (13 and/or 32 and/or 131) included in the package interface and connected to the spacer conductive connections, fig. 5
5. The semiconductor package assembly of claim 4, wherein the diameter of a spacer conductive connection (203/200, 213/210) is smaller than the diameter (32 and/or 131) of the connector included in the package interface, fig. 5.
6. The semiconductor package assembly of claim 5, wherein a plurality of spacer conductive connections (203/200, 213/210) are coupled to the connector (13 and/or 32 and/or 131) included in the package interface, fig. 5.
7. The semiconductor package assembly of claim 2, wherein a diameter of the spacer conductive connections (203, 213) equals a diameter of a connector (13) included in the package interface, fig. 5.
9. The semiconductor package assembly of claim 2, wherein
the spacer interconnect (20 or 21) has a thickness that is equal to a distance between the second portion of the connectivity region (243) of the chiplet (24) and a surface of the package interface (13 and/or 32 and/or 131), fig. 5.
10. The semiconductor package assembly of claim 1, wherein the interposer die (22) comprises an active interposer die, para. [0077].
11. The semiconductor package assembly of claim 1, wherein the chiplet (24) is configured to perform one or more input/output functions, para. [0034].
12. The semiconductor package assembly of claim 1, wherein the first portion (e.g. 243 overlapping 22) of the connectivity region of the chiplet (24) is configured to communicate with the interposer die (22), and the second portion (e.g. 243 non-overlapping 22) of the connectivity region of the chiplet (24) is configured to communicate with a package substrate (13 and/or 32 and/or 131) to which the interposer die is coupled, fig. 5.
Regarding claim 13:
Lee teaches the limitations as applied to claim 1 above.
Regarding claim 14:
Lee teaches the limitations as applied to claim 2 above.
Regarding claim 16:
Lee teaches the limitations as applied to claim 5 above.
Regarding claim 17:
Lee teaches the limitations as applied to claim 6 above.
Regarding claim 18:
Lee teaches the limitations as applied to claim 7 above.
Regarding claim 19:
Lee teaches the limitations as applied to claim 9 above.
Regarding claim 20:
Lee teaches the limitations as applied to claim 10 above.
21. The semiconductor package assembly of claim 2, wherein the chiplet (22) entirely covers a top surface of the spacer interconnect (20 or 21), fig. 5.
Claim(s) 1-3 and 13-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee, US Publication No. 2024/0021591 A1.
In a second interpretation-
Lee anticipates:
1. A semiconductor package assembly comprising (see fig. 5; and element labels in fig. 2A):
a package interface (13 and/or 32 and/or 131);
an interposer die (21) having a first surface (e.g. bottom surface) and a second surface (e.g. top surface) opposite to the first surface, the first surface of the interposer die positioned on the package interface, the interposer die (21) including a plurality of conductive connections (213, 210, 215) between the first surface and second surface; and
a chiplet (24) including a connectivity region (243) having conducive pathways, with a first portion (e.g. 243 overlapping 21) of the connectivity region coupled to a conductive connection of the interposer die (21) and a second portion (e.g. 243 non-overlapping 21) of the connectivity region cantilevered from the interposer die, wherein the chiplet (24) is bonded to the second surface of the interposer die (21) via hybrid bonding (e.g. see hybrid bond at para. [0042]). See Lee at para. [0001] – [0117], figs. 1-7.
Regarding claim 1:
Referring to MPEP § 2131:
“The identical invention must be shown in as complete detail as is contained in the ... claim.” Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236, 9 USPQ2d 1913, 1920 (Fed. Cir. 1989). The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990).
2. The semiconductor package assembly of claim 1 further comprising:
a spacer interconnect (22) placed between the second portion (e.g. 243 non-overlapping 21) of the connectivity region (243) of the chiplet (24) and the package interface (13 and/or 32), the spacer interconnect (22) including spacer conductive connections (223, 220, 225 as labeled in fig. 2A) coupling conductive pathways of the second portion of the connectivity region (243) to one or more connections within the package interface (13 and/or 32 and/or 131), fig. 5.
3. The semiconductor package assembly of claim 2, wherein the spacer interconnect (22) comprises a passive die, para. [0077].
Regarding claim 13:
Lee teaches the limitations as applied to claim 1 above.
Regarding claim 14:
Lee teaches the limitations as applied to claim 2 above.
Regarding claim 15:
Lee teaches the limitations as applied to claim 3 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
12 March 2026