DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 11, 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6, 8-13, 15, 16 and 21-24 have been considered but are moot on grounds of new rejection and interpretation of prior art.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13, 15, 16 and 21-24 is/are rejected under 35 U.S.C. 103 as being obvious over Chen et al. (Chen) (US 2021/0249380 A1) as evidenced by or view of Chen et al. (Chen’409) (US 2021/0098409 A1) as evidenced by or in view of Yuan et al. (Yuan) (US 2017/0092626 A1 now US 9,899,355 B2) as evidenced by or in view of Chen et al. (Chen’074) (US 2022/0278074 A1) and/or Agarwal et al. (Agarwal) (US 2023/0268319 A1).
In regards to claim 1, Chen (Figs. 1-2G and associated text) discloses a method of manufacturing a semiconductor assembly (Fig. 2G) comprising: forming a set of through-silicon vias (items 104, 204) in a carrier wafer (items 100, 200 or 100 plus 200), where a layer of the carrier wafer (items 100, 200 or 100 plus 200) includes integrated passive devices (not shown but present, paragraphs 13, 15); coupling a die (items 300, 400) to a top surface of the carrier wafer (items 100, 200 or 100 plus 200) including the set of through- silicon vias (items 104, 204) using hybrid bonding (paragraph 22), wherein one or more connection layers (items 310, 410) of the die (items 300, 400) are coupled to one or more of the through-silicon vias (items 104, 204) and are coupled to one or more of the integrated passive devices (not shown but present, paragraphs 13, 15, ); coupling a second wafer (item C2) to a top surface of the die (items 300, 400); and removing an amount from a bottom surface of the carrier wafer (items 100, 200 or 100 plus 200) to reveal a conductive portion of at least one of the through-silicon vias (items 104, 204) included in the carrier wafer (items 100, 200 or 100 plus 200). Examiner notes the Applicant has not given any criticality to the order in which these processes are performed.
As evidenced by Chen’409 (Figs. 1-5 and associated text), the second wafer (item 202) can remain to be if so desired and discloses removing an amount from a bottom surface (item 100) of the carrier wafer (item 100 plus 104 plus 105) to reveal a conductive portion of at least one of the through-silicon vias (items 104A, 104B, paragraph 15, 30, Fig. 4) included in the carrier wafer (item 100 plus 104 plus 105) at a time after coupling the die (items 300, 400) to the top surface of the carrier wafer (item 100 plus 104 plus 105). Examiner notes that Chen’409, need not disclose though silicon vias as that is already taken care of by Chen.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’409 for the purpose of protection and structural support (paragraph 26).
Also as evidence by Yuan (Figs. 7A-7D and associated text) discloses forming a set of through-silicon vias (items 10, 20) in a carrier wafer (items 200, paragraph 28), where a layer of the carrier wafer (item 200) includes integrated devices (item 216); coupling a die (item 100) to a top surface of the carrier wafer (item 200) including the set of through- silicon vias (items 10, 20) using hybrid bonding (paragraphs 47, 62), wherein one or more connection layers (item 120) of the die (item 100) are coupled to one or more of the through-silicon vias (items 10, 20) and are coupled to one or more of the integrated devices (item 216); and removing an amount from a bottom surface of the carrier wafer (item 200) to reveal a conductive portion of at least one of the through-silicon vias (items 10, 20) included in the carrier wafer (item 200) at a time after coupling the die (items 100) to the top surface of the carrier wafer (item 200).
Therefore it would have been obvious to one of ordinary skill in the art to incorporate the teachings of Yuan for the purpose of an electrical connection and forming a 3DIC structure.
Chen as modified by Chen’409 and Yuan does not specifically disclose removing an amount from bottom surface of the carrier wafer to reveal a conductive portion of at least one of the through-silicon-vias included in the carrier wafer at a time after coupling the die to the top surface of the carrier wafer and after coupling the second wafer to the top surface of the die.
Chen’074 (paragraphs 80, 81, Figs. 37a-37d, 38a, 38b and associated text and items) discloses removing an amount from bottom surface of the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) to reveal a conductive portion of at least one of the through-silicon-vias (item 120) included in the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) at a time after coupling the die (items 200a, 200b or 200a plus 200b) to the top surface of the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) and after coupling the second wafer (item 550) to the top surface of the die (items 200a, 200b or 200a plus 200b). Examiner notes Chen’074 discloses “these processes may be performed in any suitable order” (paragraph 80).
Agarwal (Figs. 6-12 and associated text) discloses removing an amount from bottom surface of the carrier wafer (items 500 plus 400 plus 600)) to reveal a conductive portion of at least one of the through-silicon-vias (item 210) included in the carrier wafer (items 500 plus 400 plus 600) at a time after coupling the die (items 700A and/or 700B) to the top surface of the carrier wafer (items 500 plus 400 plus 600) and after coupling the second wafer (item 900) to the top surface of the die (items 700A and/or 700B).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’074 and/or Agarwal for the purpose of protection in general or during subsequent processes, similar packages and an electrical connection to other devices. Examiner notes that the Applicant has not established the criticality of the order in which the processes are performed in regards to the method of manufacture. Furthermore, the Applicant has failed to establish that the specific order of these processes yield an advantage and/or unexpected result during the method of manufacture and/or in regards to the quality, performance, operational dependability and/or lifetime of the final product produced by these steps in this order. The Examiner therefore takes position that while claimed as such, the method of manufacture is not order specific or novel.
In regards to claims 2 and 10, Chen (Figs. 1-2G and associated text) discloses coupling a solder bump (item 650) to the conductive portion of the at least one of the through-silicon vias (items 104, 204), the solder bump (item 650) opposite to the die (items 300, 400).
In regards to claims 3, 11, Chen (Figs. 1-2G and associated text) discloses wherein an integrated passive device (not shown but present, paragraphs 13, 15) comprises passive devices (not show but present paragraphs 13, 15, capacitors, resistors, etc.) that are integrated into the carrier wafer and do not include surface mount devices.
In regards to claims 4, 12 and 22, Chen (Figs. 1-2G and associated text) discloses wherein an integrated passive device (not shown but present, paragraphs 13, 15) comprises a capacitor (not show but present paragraphs 13, 15, capacitors, resistors, etc.).
In regards to claims 5, 13 and 23 Chen (Figs. 1-2G and associated text) discloses wherein the capacitor (not show but present paragraphs 13, 15, capacitors, resistors, etc.) comprises a silicon deep trench capacitor (not show but present paragraphs 13, 15, capacitors, resistors, etc.).
In regards to claims 6 and 24, Chen (Figs. 1-2G and associated text) discloses wherein an integrated passive device (not show but present paragraphs 13, 15, capacitors, resistors, etc.) comprises an inductor (not show but present paragraphs 13, 15, capacitors, resistors, etc.).
In regards to claim 8, Chen (Figs. 1-2G and associated text) as modified by Chen’409 (Figs. 1-5 and associated text) and Yuan (Figs. 7A-7D and associated text) discloses wherein removing the amount from the bottom surface of the carrier wafer (items 100, 200 or 100 plus 200, Chen, item 100 plus 104 plus 105, Chen’409, 200, Yuan) to reveal the conductive portion of at least one of the through-silicon vias (items 104, 204, Chen, items 10, 20, Yuan) comprises: grinding away the amount of the carrier wafer (items 100, 200 or 100 plus 200, Chen, item 100 plus 104 plus 105, Chen’409, 200, Yuan) from the bottom surface of the carrier wafer (items 100, 200 or 100 plus 200, Chen, item 100 plus 104 plus 105, Chen’409, 200, Yuan) to expose the conductive portion of at least one of the through- silicon vias (items 104, 204, Chen, items 10, 20, Yuan).
In regards to claim 9, Chen (Figs. 1-2G and associated text) discloses method for forming a semiconductor assembly (Fig. 2G) comprising: coupling, using hybrid bonding (paragraph 22), a die (items 300, 400) to a carrier wafer (items 100, 200 or 100 plus 200), where a layer of the carrier wafer (items 100, 200 or 100 plus 200) includes integrated passive devices (not shown but present, paragraphs 13, 15), a bottom surface the die (items 300, 400) coupled to the carrier wafer (items 100, 200 or 100 plus 200), where one or more of the integrated devices (not shown but present, paragraphs 13, 15) are coupled to one or more connection layers of the die (items 300, 400); coupling a second wafer (item C2) to a top surface of the die (items 300, 400); removing an amount from a bottom surface of the carrier wafer (items 100, 200 or 100 plus 200), resulting in the layer of the carrier wafer (items 100, 200 or 100 plus 200) including the integrated passive devices (not shown but present, paragraphs 13, 15) remaining coupled to the die (items 300, 400); and forming a set of through-silicon vias (items 104, 204) in the layer of the carrier wafer (items 100, 200 or 100 plus 200) between the layer of the carrier wafer (items 100, 200 or 100 plus 200) including the integrated devices (not shown but present, paragraphs 13, 15) and coupled to the die (items 300, 400) at a time after removing the amount from the bottom surface of the carrier wafer (items 100, 200 or 100 plus 200).
As evidenced by Chen’409 (Figs. 1-5 and associated text), the second wafer (item 202) can remain to be if so desired and discloses removing an amount from a bottom surface (item 100) at a time after coupling the die (items 300, 400) to the carrier wafer (item 100 plus 104 plus 105). Examiner notes that Chen’409, need not disclose though silicon vias as that is already taken care of by Chen.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’409 for the purpose of protection and structural support (paragraph 26).
Also as evidence by Yuan (Figs. 7A-7D and associated text) discloses removing an amount from a bottom surface of the carrier wafer at a time after coupling the die (items 100) to the carrier wafer (item 200).
Therefore it would have been obvious to one of ordinary skill in the art to incorporate the teachings of Yuan for the purpose of an electrical connection.
Chen as modified by Chen’409 and Yuan does not specifically disclose removing an amount from bottom surface of the carrier wafer to reveal a conductive portion of at least one of the through-silicon-vias included in the carrier wafer at a time after coupling the die to the top surface of the carrier wafer and after coupling the second wafer to the top surface of the die.
Chen’074 (paragraphs 80, 81, Figs. 37a-37d, 38a, 38b and associated text and items) discloses removing an amount from bottom surface of the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) to reveal a conductive portion of at least one of the through-silicon-vias (item 120) included in the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) at a time after coupling the die (items 200a, 200b or 200a plus 200b) to the top surface of the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) and after coupling the second wafer (item 550) to the top surface of the die (items 200a, 200b or 200a plus 200b). Examiner notes Chen’074 discloses “these processes may be performed in any suitable order” (paragraph 80).
Agarwal (Figs. 6-12 and associated text) discloses removing an amount from bottom surface of the carrier wafer (items 500 plus 400 plus 600)) to reveal a conductive portion of at least one of the through-silicon-vias (item 210) included in the carrier wafer (items 500 plus 400 plus 600) at a time after coupling the die (items 700A and/or 700B) to the top surface of the carrier wafer (items 500 plus 400 plus 600) and after coupling the second wafer (item 900) to the top surface of the die (items 700A and/or 700B).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’074 and/or Agarwal for the purpose of protection in general or during subsequent processes, similar packages and an electrical connection to other devices. Examiner notes that the Applicant has not established the criticality of the order in which the processes are performed in regards to the method of manufacture. Furthermore, the Applicant has failed to establish that the specific order of these processes yield an advantage and/or unexpected result during the method of manufacture and/or in regards to the quality, performance, operational dependability and/or lifetime of the final product produced by these steps in this order. The Examiner therefore takes position that while claimed as such, the method of manufacture is not order specific or novel.
In regards to claim 15, Chen (Figs. 1-2G and associated text) discloses wherein removing the amount from the bottom surface of the carrier wafer (items 100, 200 or 100 plus 200) resulting in the layer of the carrier wafer (items 100, 200 or 100 plus 200) including the integrated devices (not shown but present, paragraphs 13, 15) remaining coupled to the die (items 300, 400) comprises: grinding away the amount from a bottom surface of the carrier wafer (items 100, 200 or 100 plus 200).
In regards to claim 16, Chen (Figs. 1-2G and associated text) discloses wherein the amount from the bottom surface of the carrier wafer (items 100, 200 or 100 plus 200) is based on a difference between a thickness of the carrier wafer (items 100, 200 or 100 plus 200) and a thickness of the layer of the carrier wafer (items 100, 200 or 100 plus 200) including the integrated devices (not shown but present, paragraph 13, 15).
In regards to claim 21, Chen (Figs. 1-2G and associated text) discloses method of manufacturing a semiconductor assembly (Fig. 2G) comprising: forming a set of through-silicon vias (items 104, 204) in a carrier wafer (items 100, 200 or 100 plus 200), where a layer of the carrier wafer (items 100, 200 or 100 plus 200) includes integrated passive devices (not shown but present, paragraphs 13, 15); coupling a die (items 300, 400) to a top surface of the carrier wafer (items 100, 200 or 100 plus 200) including the set of through- silicon vias (items 104, 204) using hybrid bonding (paragraph 22), wherein one or more connection layers (items 310, 410) of the die (items 300, 400)are coupled to one or more of the through-silicon vias (items 104, 204) and are coupled to one or more of the integrated passive devices (not show but present, paragraphs 13, 15); coupling a second wafer (item C2) to a top surface of the die (items 300, 400); removing an amount from a bottom surface of the carrier wafer (items 100, 200 or 100 plus 200) to reveal a conductive portion of at least one of the through-silicon vias (items 104, 204) included in the carrier wafer (items 100, 200 or 100 plus 200); and coupling a solder bump (item 650) to the conductive portion of the at least one of the through-silicon vias (items 104, 204), the solder bump (item 650) opposite to the die (items 300, 400).
As evidenced by Chen’409 (Figs. 1-5 and associated text), the second wafer (item 202) can remain to be if so desired and discloses removing an amount from a bottom surface (item 100) of the carrier wafer (item 100 plus 104 plus 105) to reveal a conductive portion of at least one of the through-silicon vias (items 104A, 104B, paragraph 15, 30, Fig. 4) included in the carrier wafer (item 100 plus 104 plus 105) at a time after coupling the die (items 300, 400) to the top surface of the carrier wafer (item 100 plus 104 plus 105). Examiner notes that Chen’409, need not disclose though silicon vias as that is already taken care of by Chen.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’409 for the purpose of protection and structural support (paragraph 26).
Also as evidence by Yuan (Figs. 7A-7D and associated text) discloses forming a set of through-silicon vias (items 10, 20) in a carrier wafer (items 200, paragraph 28), where a layer of the carrier wafer (item 200) includes integrated devices (item 216); coupling a die (item 100) to a top surface of the carrier wafer (item 200) including the set of through- silicon vias (items 10, 20) using hybrid bonding (paragraphs 47, 62), wherein one or more connection layers (item 120) of the die (item 100) are coupled to one or more of the through-silicon vias (items 10, 20) and are coupled to one or more of the integrated devices (item 216); and removing an amount from a bottom surface of the carrier wafer (item 200) to reveal a conductive portion of at least one of the through-silicon vias (items 10, 20) included in the carrier wafer (item 200) at a time after coupling the die (items 100) to the top surface of the carrier wafer (item 200).
Therefore it would have been obvious to one of ordinary skill in the art to incorporate the teachings of Yuan for the purpose of an electrical connection and forming a 3DIC structure.
Chen as modified by Chen’409 and Yuan does not specifically disclose removing an amount from bottom surface of the carrier wafer to reveal a conductive portion of at least one of the through-silicon-vias included in the carrier wafer at a time after coupling the die to the top surface of the carrier wafer and after coupling the second wafer to the top surface of the die.
Chen’074 (paragraphs 80, 81, Figs. 37a-37d, 38a, 38b and associated text and items) discloses removing an amount from bottom surface of the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) to reveal a conductive portion of at least one of the through-silicon-vias (item 120) included in the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) at a time after coupling the die (items 200a, 200b or 200a plus 200b) to the top surface of the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) and after coupling the second wafer (item 550) to the top surface of the die (items 200a, 200b or 200a plus 200b). Examiner notes Chen’074 discloses “these processes may be performed in any suitable order” (paragraph 80).
Agarwal (Figs. 6-12 and associated text) discloses removing an amount from bottom surface of the carrier wafer (items 500 plus 400 plus 600)) to reveal a conductive portion of at least one of the through-silicon-vias (item 210) included in the carrier wafer (items 500 plus 400 plus 600) at a time after coupling the die (items 700A and/or 700B) to the top surface of the carrier wafer (items 500 plus 400 plus 600) and after coupling the second wafer (item 900) to the top surface of the die (items 700A and/or 700B).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’074 and/or Agarwal for the purpose of protection in general or during subsequent processes, similar packages and an electrical connection to other devices. Examiner notes that the Applicant has not established the criticality of the order in which the processes are performed in regards to the method of manufacture. Furthermore, the Applicant has failed to establish that the specific order of these processes yield an advantage and/or unexpected result during the method of manufacture and/or in regards to the quality, performance, operational dependability and/or lifetime of the final product produced by these steps in this order. The Examiner therefore takes position that while claimed as such, the method of manufacture is not order specific or novel.
Claims 1 and 21 is/are rejected under 35 U.S.C. 103 as being obvious over Yuan et al. (Yuan) (US 2017/0092626 A1 now US 9899355 B2) in view of Chen et al. (Chen’409) (US 2021/0098409 A1) as evidenced by or in view of Chen et al. (Chen’074) (US 2022/0278074 A1) and/or Agarwal et al. (Agarwal) (US 2023/0268319 A1).
In regards to claims 1 and 21, Yuan (Figs. 7A-7D and associated text) discloses forming a set of through-silicon vias (items 10, 20) in a carrier wafer (items 200, paragraph 28), where a layer of the carrier wafer (item 200) includes integrated (passive) devices (item 216); coupling a die (item 100) to a top surface of the carrier wafer (item 200) including the set of through- silicon vias (items 10, 20) using hybrid bonding (paragraphs 47, 62), wherein one or more connection layers (item 120) of the die (item 100) are coupled to one or more of the through-silicon vias (items 10, 20) and are coupled to one or more of the integrated devices (item 216); and removing an amount from a bottom surface of the carrier wafer (item 200) to reveal a conductive portion of at least one of the through-silicon vias (items 10, 20) included in the carrier wafer (item 200) at a time after coupling the die (items 100) to the top surface of the carrier wafer (item 200), and coupling a solder bump (items 232a plus 234a plus 228a or 232a alone) to the conductive portion of the at least one of the through-silicon vias (items 10, 20), the solder bump (items 232a plus 234a plus 228a or 232a) opposite to the die (item 100), but does no specifically disclose coupling a second wafer to a top surface of the die.
Chen’409 (Figs. 1-5 and associated text) coupling a second wafer (item 202) to a top surface of the die (item 300, 400).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’409 for the purpose of protection and structural support (paragraph 26).
Yuan as modified by Chen’409 does not specifically disclose removing an amount from bottom surface of the carrier wafer to reveal a conductive portion of at least one of the through-silicon-vias included in the carrier wafer at a time after coupling the die to the top surface of the carrier wafer and after coupling the second wafer to the top surface of the die.
Chen’074 (paragraphs 80, 81, Figs. 37a-37d, 38a, 38b and associated text and items) discloses removing an amount from bottom surface of the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) to reveal a conductive portion of at least one of the through-silicon-vias (item 120) included in the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) at a time after coupling the die (items 200a, 200b or 200a plus 200b) to the top surface of the carrier wafer (items 100/100’ plus 150 plus 190, which becomes 100/100’ afterwards) and after coupling the second wafer (item 550) to the top surface of the die (items 200a, 200b or 200a plus 200b). Examiner notes Chen’074 discloses “these processes may be performed in any suitable order” (paragraph 80).
Agarwal (Figs. 6-12 and associated text) discloses removing an amount from bottom surface of the carrier wafer (items 500 plus 400 plus 600)) to reveal a conductive portion of at least one of the through-silicon-vias (item 210) included in the carrier wafer (items 500 plus 400 plus 600) at a time after coupling the die (items 700A and/or 700B) to the top surface of the carrier wafer (items 500 plus 400 plus 600) and after coupling the second wafer (item 900) to the top surface of the die (items 700A and/or 700B).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen’074 and/or Agarwal for the purpose of protection in general or during subsequent processes, similar packages and an electrical connection to other devices. Examiner notes that the Applicant has not established the criticality of the order in which the processes are performed in regards to the method of manufacture. Furthermore, the Applicant has failed to establish that the specific order of these processes yield an advantage and/or unexpected result during the method of manufacture and/or in regards to the quality, performance, operational dependability and/or lifetime of the final product produced by these steps in this order. The Examiner therefore takes position that while claimed as such, the method of manufacture is not order specific or novel.
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 March 19, 2026