DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16 in the reply filed on 12/26/2025 is acknowledged. Claims 17-20 have been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over McFarland (US 20020074637), hereinafter McFarland, in view of Park (US 20120095123), hereinafter Park.
Regarding claim 1, McFarland (refer to Figure 1) teaches an electronic device (100, para 17) comprising:
an interposer (middle part of 110 through which 160 passes; see para 20) including a metallic through via (160 that pass through middle part of 110) extending from a first surface (upper surface in orientation of Figure 1) of the interposer to a second surface (lower surface in orientation of Figure 1) of the interposer;
a first polymer layer (polymer layer just above 160; i.e. just above 160 that pass through middle part of 110 and in which conductive pads 116 are formed – as seen in orientation of Figure 1), adjacent to the first surface (i.e. upper surface) of the interposer; and
one or more dies (120, para 19) connected (i.e. connected by 116, described as "a plurality of conductive pads 116" in para 20) to the metallic through via (160 that pass through middle part of 110).
McFarland does not teach that the first polymer layer is a “porous” polymer layer, but the same is taught by Park (see abstract and para 14; also see para 3). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify McFarland so that the first polymer layer is a “porous” polymer layer. The ordinary artisan would have been motivated to modify McFarland for at least the purpose of improving performance, such as in areas of mechanical strength, thermal stability and proccessability (para 3 of Park).
Regarding claims 2, McFarland (refer to Figure 1) teaches the electronic device of claim 1, but does not specifically teach that the interposer includes “glass”. However, McFarland teaches that the interposer is part of a substrate (para 20), and also teaches that a known substrate type suitable for soldering is a printed circuit board (para 3). Further, it is well known in the art that a common materials for printed circuit boards (e.g. multilayer FR-4 or ceramic), comprise glass. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify McFarland so that the interposer includes “glass”. The ordinary artisan would have been motivated to modify McFarland for at least the purpose of using a common dielectric material such as glass that is a good insulator and is capable of creating a fire retardant material like FR-4 for interposers and substrates.
Regarding claims 3, McFarland (refer to Figure 1) teaches the electronic device of claim 1, but does not specifically teach that the interposer includes “silicon”. However, McFarland teaches that silicon is a suitable material to support integrated circuit layers (para 17). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify McFarland so that the interposer that supports circuitry includes “silicon”. The ordinary artisan would have been motivated to modify McFarland for at least the purpose of using a material that more closely matches in coefficient of thermal expansion with chips mounted on the interposer, thus reducing stresses under thermal cycling loads.
Regarding claims 4, McFarland (refer to Figure 1) teaches the electronic device of claim 1, further comprising a second polymer layer (polymer layer just below160 that pass through middle part of 110 and in which conductive pads corresponding to “conductive bumps 150” are formed – as seen in orientation of Figure 1; see para 18) adjacent to the second surface (i.e. lower surface in orientation of Figure 1) of the interposer. McFarland does not teach that the second polymer layer is a “porous” polymer layer, but the same is taught by Park (see abstract and para 14; also see para 3). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify McFarland so that the second polymer layer is a “porous” polymer layer. The ordinary artisan would have been motivated to modify McFarland for at least the purpose forming porous polymer layer on opposing surfaces of the interposer to further improve performance, such as in areas of mechanical strength, thermal stability and proccessability (para 3 of Park).
Regarding claims 5, McFarland (refer to Figure 1) teaches electronic device of claim 1, further comprising one or more first horizontal metallic routings (116, para 20) interproximal the first surface (i.e. upper surface in orientation of Figure 1) of the interposer and the first porous polymer layer (polymer layer just above 160 that pass through middle part of 110 and in which conductive pads 116 are formed – as seen in orientation of Figure 1).
Regarding claims 6, McFarland (refer to Figure 1) teaches the electronic device of claim 4, further comprising:
one or more first horizontal metallic routings (116, para 20) interproximal the first surface (i.e. upper surface in orientation of Figure 1) of the interposer and the first porous polymer layer (polymer layer just above 160 that pass through middle part of 110 and in which conductive pads 116 are formed – as seen in orientation of Figure 1); and
one or more second horizontal metallic routings (horizontal pads, not labelled – to which 150 are attached – see Figure 1) interproximal the second surface (i.e. lower surface in orientation of Figure 1) of the interposer and the second porous polymer layer (polymer layer just below160 that pass through middle part of 110 and in which conductive pads corresponding to “conductive bumps 150” are formed – as seen in orientation of Figure 1; see para 18).
Regarding claim 7, it recites an additional layer; i.e. “a third porous polymer layer” that is substantially similar to and adjacent to the first porous polymer layer, which amounts to duplication of parts. The additional recitation of “one or more first horizontal metallic routings interproximal the first porous polymer layer adjacent to the first surface of the interposer and the third porous polymer layer” has already been addressed for claim 5. It would have been obvious to one of ordinary skill in the art to stack a third porous polymer layer on the first porous polymer layer, both being substantially similar layer, as claimed, because such structure is considered to be a duplication of parts that has no patentable significance unless a new unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), MPEP 2144.04.
Regarding claim 8, it recites an additional layer; i.e. “a fourth porous polymer layer” that is substantially similar to and adjacent to the second porous polymer layer, which also amounts to duplication of parts. The additional recitation of “one or more second horizontal metallic routings interproximal the second porous polymer layer and the fourth porous polymer layer” has already been addressed for claim 6. It would have been obvious to one of ordinary skill in the art to stack a fourth porous polymer layer on the second porous polymer layer, both being substantially similar layer, as claimed, because such structure is considered to be a duplication of parts that has no patentable significance unless a new unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), MPEP 2144.04.
Regarding claims 9, McFarland (refer to Figure 1), as modified in view of Park for claim 1 so that the first polymer layer is a first porous polymer layer (see rejection of claim 1), and Park further teaches that the first porous polymer layer (as taught by Park) comprises a nanopolymer (para 3 and 60 of Park). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify McFarland so that the first polymer layer is a first “porous” polymer layer that comprises a nanopolymer. The ordinary artisan would have been motivated to modify McFarland for at least the purpose of using a material that is a poor conductor of heat, thus improving performance, such as in areas of thermal stability and proccessability (para 3 of Park).
Regarding claims 10, McFarland (refer to Figure 1), as modified in view of Park for claim 1 and claim 4 so that the first polymer layer and the second polymer layer are each porous polymer layers; and Park further teaches that porous polymer layers may comprises a nanopolymer (para 3 and 60 of Park). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify McFarland so that the first porous polymer layer comprises a nanopolymer, and wherein the second porous polymer layer comprises a nanopolymer. The ordinary artisan would have been motivated to modify McFarland for at least the purpose of using a material that is a poor conductor of heat, thus improving performance, such as in areas of thermal stability and proccessability (para 3 of Park).
Regarding claim 11, McFarland (refer to Figure 1) teaches an electronic device (100, para 17), comprising:
a cored substrate (110, see para 20) including a core (middle part of 110 through which 160 passes; see para 20) and one or more build up layers (layer just above or just below 160; i.e. 160 that pass through middle part of 110 and in which conductive pads 116 are formed – as seen in orientation of Figure 1) on either major surface (i.e. upper or lower surface) of the core,
wherein the one or more build up layers includes at least one polymer layer;
one or more metallic vias (160 that pass through middle part of 110) extending through the cored substrate; and
one or more dies (120, para 19) coupled to the at least one polymer layer (such as upper polymer layer) and connected to (see Figure 1) the one or more metallic vias (160).
McFarland does not teach that the at least one polymer layer is a “porous” polymer layer, and that the core is a “glass” core; i.e. comprises glass.
Park teaches the advantage of using a polymer layer that is a porous polymer layer (see abstract and para 14; also see para 3). Further, McFarland teaches that the cored substrate (para 20), and also teaches that a known substrate type suitable for soldering is a printed circuit board (para 3). Further, it is well known in the art that a common materials for printed circuit boards (e.g. multilayer FR-4 or ceramic), comprise glass. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify McFarland so that that the at least one polymer layer is a “porous” polymer layer, and that the core is a “glass” core; i.e. comprises glass. The ordinary artisan would have been motivated to modify McFarland for at least the purpose of using a core material that is known to be fire retardant (such as FR-4) and resistant to heat, and also using a porous polymer that also improves performance, such as in areas of thermal stability and proccessability (para 3 of Park).
Regarding claim 12, McFarland (refer to Figure 1) teaches the electronic device of claim 11, further comprising: a first layer (polymer layer just above 160; i.e. just above 160 that pass through middle part of 110 and in which conductive pads 116 are formed – as seen in orientation of Figure 1) of the one or more build up layers, the first layer adjacent the glass core; and one or more first horizontal metallic routings (116, para 20) interproximal the glass core (middle part of 110 through which 160 passes, as modified for claim 11) and the first layer (polymer layer just above 160, as modified for claim 11).
Regarding claims 13-14, McFarland (refer to Figure 1) teaches the electronic device of claim 12, wherein the first layer is a porous polymer layer (as modified for claim 11 and 12 in view of Park); and further wherein (as recited in claim 13) the first layer comprises a nanopolymer (para 3 and 60 of Park). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify McFarland so that the first layer is a porous polymer layer i that comprises a nanopolymer. The ordinary artisan would have been motivated to modify McFarland for at least the purpose of using a material that is a poor conductor of heat, thus improving performance, such as in areas of thermal stability and proccessability (para 3 of Park).
Regarding claims 15-16, McFarland (refer to Figure 1) teaches the electronic device of claim 11, further comprising: a first layer of the one or more build up layers (reads on a build up layer that has at least one layer, as is the case for claim 11), the first layer adjacent the glass core (i.e. just above the glass core); and (as recited in claim 16) one or more first horizontal metallic routings (116, para 20) interproximal the glass core layer and the first layer. McFarland does not teach “an adhesion promotion layer” that is interproximal the first layer and the glass core, and as such, also does not teach that the one or more first horizontal metallic routings are interproximal “the adhesion promotion layer” and the first layer. However, McFarland teaches that use of adhesion promotion layers and diffusion barrier layers is known in the art (para 32). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify McFarland to include an adhesion promotion layer between the dissimilar materials such as glass core and the porous first layer, which would result in a configuration wherein “an adhesion promotion layer” is interproximal the first layer and the glass core, and as such, the one or more first horizontal metallic routings are interproximal the adhesion promotion layer and the first layer. The ordinary artisan would have been motivated to modify McFarland for at least the purpose of enhancing adhesion between dissimilar materials (para 32 of McFarland), thus mitigating delamination failures during device life.
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892