DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 12/12/2025.
Claims 1-20 are pending in this application.
Final Restriction Requirement
2. Applicant made a provisional election with traverse to prosecute the
invention of Species I, claims 1-14 is acknowledged.
To traverse the restriction requirement, Applicant just simply stated that the species identified by the Examiner are not mutually exclusive, and referred to claim 7 as an example of evidence. Applicant did not further distinctly and specifically point out the supposed error in the restriction requirement. Claim 7 recites a third semiconductor device comprising a second gate cut, wherein the second body is separated laterally from the second gate cut by a third distance, and wherein the second and third distance differ by at least 2 nm. These claimed features are not so obvious variants from what is/are recited in the inventions of Species II and/or Species III, and that they are patentably distinct from each other (see the restriction requirement for further). Therefore, the restriction requirement is proper, and the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claims 15-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Acknowledges
3. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 03/07/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
4. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1, 3-7, and 9-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US 2023/0141523)
Regarding claim 1, Chen discloses an integrated circuit comprising:
a first semiconductor device 188-1 (in short; that is, the first semiconductor device having gate structure 188-1; see Figs. 2P, 2W) comprising (i) a first source region 178-1 (see fig. 2N-2 and paras. 0069, 0075-0079), (ii) a first drain region 178-2, (iii) a first body 108 (fig. 2N-2) or 108’-1 (fig. 2W) comprising semiconductor material extending in a first direction (along body or nanostructure channel 108’-1) from the first source region to the first drain region, and (iv) a first gate structure 188-1/194 extending in a second direction (crossing the body or channel 108’-1) and on the first body 108’-1 (see also Fig. 2J-3);
a second semiconductor device 188-3 comprising (i) a second source region, (ii) a second drain region, (iii) a second body 108’-3 (Fig. 2W, fig. 2N-2) comprising semiconductor material extending in the first direction from the second source region to the second drain region, and (iv) a second gate structure 188-3 extending in the second direction and on the second body 108’-3; and
a gate cut 124 (which may comprise core layer 120 and dielectric shell 118, see fig. 2P), laterally between and separating the first gate structure 188-1 and the second gate structure 188-3, the gate cut 124 comprising dielectric material (para. 0056);
wherein the first body 108’-1 is separated laterally from the gate cut 124 by a first distance, wherein the second body 108’-3 is separated laterally from the gate cut 124 by a second distance, and wherein the first and second distances differ by at least 2 nanometers (nm) (see fig. 2W; see also paras. 0090-0091).
Regarding claim 3, Chen discloses the integrated circuit of claim 1, wherein:
the first gate structure 188-1 comprises (i) a gate electrode 194, and (ii) a gate dielectric 190 & 192 (or 190 & 192 & 118CN) on the first body 108’-1, the gate dielectric 190 & 192 separating the gate electrode 194 from the first body 108’-1; and
the gate dielectric 190 & 192 (or 190 & 192 & 118CN), and not the gate electrode 194, is laterally between the first body 108’-1 and the dielectric material 120 of the gate cut 124. See fig. 2W.
Regarding claim 4, Chen discloses the integrated circuit of claim 1, wherein the first distance is zero, such that the first body 108/108’-1 is in contact with the dielectric material 118 of the gate cut. See figs. 2P, 2W.
Regarding claim 5, Chen discloses the integrated circuit of claim 1, wherein:
the first gate structure 188-1 comprises (i) a gate electrode 194, and (ii) gate dielectric 190 & 192 between the gate electrode 194 and the first body 108’-1; and
the gate dielectric 190 &192 is in contact with the dielectric material 118 of the gate cut. See figs. 2P, 2W.
Regarding claim 6. (Original) The integrated circuit of claim 1, wherein:
the first gate structure comprises (i) a gate electrode 194, and (ii) gate dielectric 190 & 192 between the gate electrode and the first body 108’-1; and
no portion of the gate electrode 194 is laterally between at least a section of the first body 108’-1 and the dielectric material 118 & 120 of the gate cut. See fig. 2W.
Regarding claim 7, Chen discloses the integrated circuit of claim 1, wherein the gate cut 124 is a first gate cut, and wherein the integrated circuit further comprises:
a third semiconductor device (unshown device right on the left of the leftmost dielectric fin 134 in fig. 2P; note that the drawings of Chen inherently just show portion of the whole semiconductor structure; see para. 0032; the whole structure is well known in the art to comprise a plurality of semiconductor devices formed on a substrate) comprising (i) a third source region, (ii) a third drain region, (iii) a third body comprising semiconductor material extending in the first direction from the third source region to the third drain region, and (iv) a third gate structure extending in the second direction and on the third body (the third source, drain, gate, and/or body of the third device should be similar to that/those of the devices 186-1 – 186-3 shown in figs. 2), wherein the second semiconductor device 186-3 is laterally between the first device 186-1 and third semiconductor device (not shown; see fig. 2P); and
a second gate cut (portion of which is shown as the leftmost portion of dielectric Fin structure in figs. 2P, 2W) laterally between and separating the second gate structure and the third gate structure, the second gate cut comprising the dielectric material, wherein there is no other semiconductor device between the second semiconductor device and the second gate cut;
wherein the second body 108’-3 is separated laterally from the second gate cut 134 (the leftmost one shown in figs. 2P, 2W) by a third distance, and wherein the second and third distances differ by at least 2 nm.
Regarding claim 9, Chen discloses the integrated circuit of claim 1, wherein at least one of the first or second distances is less than 2 nm (fig. 2P shows the first distance is about zero).
Regarding claim 10, Chen discloses the integrated circuit of claim 1, wherein the first and second distances differ by at least 4 nm. See fig. 2P, and para. 0090-0091.
Regarding claim 11, Chen discloses the integrated circuit of claim 1, wherein each of the first and second bodies is a nanoribbon, a nanowire, or a nanosheet. See figs. 2, and paras. 0029, 0084.
Regarding claim 12, Chen discloses the integrated circuit of claim 1, wherein each of the first and second bodies is a fin. See paras. 0036-0037, 0084, and figs. 2.
Regarding claim 13, Chen discloses the integrated circuit of claim 1, wherein the first device comprises:
a plurality of bodies 108’-1 arranged in a vertical stack and comprising semiconductor material, the plurality of bodies extending in the first direction from the first source region to the first drain region, the plurality of bodies including the first body,
wherein the first gate structure 188-1 at least in part wraps around middle portions of each body of the plurality of bodies, and
wherein the plurality of bodies comprises a plurality of nanoribbons, a plurality of nanowires, or a plurality of nanosheets. See figs. 2, and paras. 0029, 0084.
Regarding claim 14, Chen discloses a printed circuit board comprising the integrated circuit of claim 1. See figs. 2.
Claim Rejections - 35 U.S.C. § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1, and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2019/0139955)
Regarding claim 1, Kim discloses an integrated circuit comprising:
a first semiconductor device (having fin structure 110B right next to and on the left of a gate separation pattern CT, see fig. 27) comprising (i) a first source region, (ii) a first drain region (similar to source/drain region 120B in figs. 2-5), (iii) a first body 110B comprising semiconductor material extending in a first direction from the first source region to the first drain region, and (iv) a first gate structure 130 (on the left of the gate separation pattern CT, fig. 27) extending in a second direction and on the first body;
a second semiconductor device (having fin structure 110A right next to and on the left of the gate separation pattern CT, see fig. 27) comprising (i) a second source region, (ii) a second drain region (figs. 2-5), (iii) a second body 110A comprising semiconductor material extending in the first direction from the second source region to the second drain region, and (iv) a second gate structure 130 (on the left of the gate separation pattern CT) extending in the second direction and on the second body; and
a gate cut CT laterally between and separating the first gate structure and the second gate structure, the gate cut CT comprising dielectric material;
wherein the first body 110B is separated laterally from the gate cut CT by a first distance,
wherein the second body 110A is separated laterally from the gate cut CT by a second distance.
Kim does not specifically teach that the wherein the first and second distances differ by at least 2 nanometers (nm).
However, fig. 27 of Kim shows such distances differ more than the size/width of the fin 110A/110B. Current technology is well known to have a size/width of a fin to be a few nanometers (nm), for the advantages of smaller size devices, leakage reductions, performance improving, etc. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made that Kim does obviously disclose the first and second distances differing by at least 2 nanometers (nm).
Regarding claim 2, Kim discloses he integrated circuit of claim 1, wherein there is no other semiconductor device between the first semiconductor device 110B (the left one in fig. 27) and the gate cut CT, and between the second semiconductor device 110A (the right one) and the gate cut CT.
Allowable Subject Matter
9. Claim 8 is allowable.
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed integrated circuit (in addition to the other limitations in the claim) wherein the first gate cut has a first width measured in the second direction, the second gate cut has a second width measured in the second direction, and the first and second widths differ by at least 2 nm.
Conclusion
10. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 January 21, 2026