DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Specie B (Claims 8-14) in the reply filed on 11/28/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8 and 12-14 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Chou (US 2018/0364567).
With respect to Claim 8, Chou discloses a method of forming an integrated circuit (paragraph 2), comprising: forming a sacrificial layer pattern (Figures 4- 6, 14b) over a conductive layer (Figure 6, 11, paragraph 22) located over a substrate (Figure 6, 10); forming dielectric spacers (Figure 6, 16a) on sidewalls of the sacrificial layer pattern (Figure 6, 14a) and removing the sacrificial layer between the dielectric spacers, thereby forming a spacer pattern (Figure 7, 16a); and transferring the spacer pattern to the conductive layer thereby forming a conductive pattern (Figure 10, 11a) .See Figures 4-10 and corresponding text, especially paragraphs 22—36.
With respect to Claim 12, Chou discloses wherein forming dielectric spacers including forming a silicon oxide layer by atomic layer deposition. See paragraph 30.
With respect to Claim 13, Chou discloses wherein transferring the spacer pattern (Figure 7, 16a) includes removing a portion of an underlayer (Figures 1-7, 12) located between the sacrificial layer pattern (Figure 2, 14a) and the conductive layer (Figure 2, 11), and then transferring the spacer pattern to the underlayer (Figures 7-9).
With respect to Claim 14, Chou discloses wherein removing the portion of the underlayer (Figures 1-7, 12) includes removing an unprotected portion of the spacer pattern (Figures 8-9, 16a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US 2018/0364567) as applied to claims 8 and 12-14 above, and further in view of Hakey et al (US 2009/0231085).
Chou et al is relied upon as discussed above.
However, Chou et al does not disclose the conductive pattern includes a serpentine resistor or connecting the conductive pattern to a transistor that extends into the substrate.
Hakey at al disclose the use of lithography techniques to form serpentine resistors (Figure 3a) and their connection to transistors. See paragraphs 18-25.
It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to use the lithography technique of Chou et al, for its known benefit in the art of forming serpentine resistors or connections to transistors, as disclosed by Hakey et al. As Hakey et al discloses the use of lithography to form serpentine resistors or connections to transistors, the use of a known lithography technique, for its benefit of forming serpentine resistors or connections to transistors would have been within the skill of one of ordinary skill in the art.
With respect to Claim 9, the combined references make obvious wherein the conductive pattern includes serpentine resistor. See Figure 3a and paragraphs 18-25 of Hakey et al.
With respect to Claim 11, the combined references make obvious further connecting the conductive pattern to a transistor that extends into the substrate. See Figure 3a and paragraphs 18-25 of Hakey et al.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The cited prior art does not anticipate or make obvious inter alia “ wherein the conductive layer includes nichrome (NiCr), silicon-chromium (SiCr) or silicon-silicon carbide- chromium (SiCCr)”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6.
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AGG
January 5, 2025
/ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812