DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of invention Group I in the reply filed on 12/30/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3 and 7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 3 reciting “a thickness of the protrusion is in a range of about 1 micron to about 20 microns” lacks adequate support. Applicant’s original disclosure describes the protrusion thickness range of 1-20 microns. However, “about 1 micron” and “about 20 microns” are not disclosed.
Claim 7 reciting “the second portion of the metal layer extends into the pad by a distance in a range of about 1 micron to about 20 microns” lacks adequate support. Applicant’s original disclosure describes the distance range of 1-20 microns. However, “about 1 micron” and “about 20 microns” are not disclosed.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 and 26-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “individual of the plurality of dielectric layers positioned adjacent to another dielectric layer” renders the claim indefinite. Firstly, it is unclear if “individual of the plurality of dielectric layers” is intended to refer to “one of the plurality of dielectric layers” or “each of the plurality of the dielectric layers”. Furthermore, it is unclear if “another dielectric layer” is one of the plurality of dielectric layers or is separate from the plurality of dielectric layers.
Claim 26 reciting “individual of the first plurality of dielectric layers positioned adjacent to another dielectric layer” and “individual of the second plurality of dielectric layers” renders the claim indefinite for similar reasons as claim 1 above.
Claim 11 reciting “the fill material is liquid metal” renders the claim indefinite. It is unclear if the final structure of the apparatus as claimed include the fill material in liquid state. Applicant’s disclosure does not describe how the fill material would remain liquid. As best understood, this limitation is treated as product by process where the fill material in the final structure need not be liquid.
Claim 14 reciting “individual of the one or more integrated circuit dies” render the claim indefinite. It is unclear if “individual of the one or more integrated circuit dies” is intended to refer to “one of the one or more integrated circuit dies” or “each of the one or more integrated circuit dies”.
Claim 15 reciting “individual second dielectric layers positioned adjacent to another second dielectric layer” and “individual of the plurality of second dielectric layers” renders the claim indefinite for similar reasons as claim 1 above. Furthermore, the recitation to “the first dielectric layers” in claim 15 renders the claim indefinite. It is unclear if the entirety of the first dielectric layers is intended or would one of the first dielectric layers suffice.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-17, 26-28, and 30-32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. US 2022/0053648 A1 (Nakamura).
PNG
media_image1.png
512
650
media_image1.png
Greyscale
In re claim 1, as best understood, Nakamura discloses (e.g. FIGs. 1 & 14) an apparatus, comprising:
a plurality of dielectric layers 61,63, “individual of the plurality of dielectric layers positioned adjacent to another dielectric layer” (as best understood, 61,63 are adjacent to each other), “individual of the plurality of dielectric layers” 61,63 comprising one or more conductive traces 62,64 and one or more vias 61x,63x;
a plurality of conductive contacts 66 located on a top dielectric layer 63 of the dielectric layers; and
a glass core 10 (¶ 29) positioned adjacent to a bottom dielectric layer 61 of the dielectric layers, the glass core comprising:
a layer of glass 10 comprising a top surface 10a, a bottom surface 10b opposite the top surface 10a, and a hole 101,102 extending from the top surface 10a to the bottom surface 10b; and
a through-glass via (23a,23b inside hole 101,102) comprising fill material 23b that at least partially fills the hole 101,102, a pad 20A,20B, and a metal layer 23a, the through-glass via (23a,23b inside hole 101,102) extending through the hole 101,102, a portion of the pad 20A,20B located on the top surface 10a of the layer of glass 10, a first portion of the metal layer (portion of 23a inside 10) positioned adjacent to an inner wall of the hole 101,102, a second portion of the metal layer (23a outside 10) extending past the top surface 10a of the layer of glass 10 and into the pad 20A,20B, the fill material 23b comprising a first metal (¶ 50-51), the metal layer 23a comprising a second metal (¶ 50-51).
In re claim 2, Nakamura discloses (e.g. FIG. 1) wherein the pad 20A,20B comprises a protrusion (corresponding to portion 24a,24b) extending away from the top surface 10a of the layer of glass 10, the protrusion coaxial with the hole 101,102 (¶ 34).
In re claim 4, Nakamura discloses (e.g. FIG. 1) wherein the pad 20A,20B does not have a recess.
In re claim 6, Nakamura discloses (e.g. FIG. 1) wherein the first portion of the metal layer (23a inside 10) is positioned between the fill material 23b and the layer of glass 10.
In re claim 7, Nakamura discloses (e.g. FIG. 1) wherein the second portion of the metal layer (23b outside 10) extends into the pad 20A by a distance that correspond to the thickness layers 22a+22b of the pad 20A. The combined thickness of 22a and 22b is approximately 3.5 µm to 17 µm (¶ 52) which teaches the claimed range of about 1 micron to about 20 microns.
In re claim 8, Nakamura discloses (e.g. FIG. 1) wherein the metal layer 23a is a first metal layer, the through-glass via further comprising a second metal layer 22a,22b located on the top surface 10a of the layer of glass 10 and positioned between the top surface 10a of the layer of glass 10 and the pad (rest of pad 20A,20B), the second metal layer 22a,22b comprising a third metal (¶ 50).
In re claim 9, Nakamura discloses (e.g. FIG. 1) wherein the pad 20A,20B is a first pad, the through-glass via further comprising a second pad 30A,30B located on the bottom surface 10b of the layer of glass 10, the metal layer 23a further comprising a third portion (portion below 10b) that extends past the bottom surface 10b of the layer of glass 10 into the second pad 30A,30B.
In re claim 10, Nakamura discloses (e.g. FIG. 1) wherein the fill material 23b is copper (¶ 50).
In re claim 11, as best understood, the limitation “the fill material is liquid metal” pertains to a product by process limitation. The final structure of the fill material does not distinguish over Nakamura’s via interconnect. In regard to the product by process language, since a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao and Sato et al., 190 USPQ 15 at 17 (CCPA 1976) (footnote 3). “[T]he lack of physical description in a product-by-process claim makes determination of the patentability of the claim more difficult, since in spite of the fact that the claim may recite only process limitations, it is the patentability of the product claimed and not of the recited process steps which must be established. We are therefore of the opinion that when the prior art discloses a product which reasonably appears to be either identical with or only slightly different than a product claimed in a product-by-process claim, a rejection based alternatively on either section 102 or section 103 of the statute is eminently fair and acceptable. As a practical matter, the Patent Office is not equipped to manufacture products by the myriad of processes put before it and then obtain prior art products and make physical comparisons therewith.” In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). See also In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the final product per se which must be determined for patentability in a "product by, all of" claim, and not the patentability of the process, and that an old or obvious product, whether claimed in "product by process" claims or not, is not patentable. Note that Applicant has the burden of proof in such cases, as the above case law makes clear. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based upon the product itself. The patentability of a product does not depend on its method of production. If the product in product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product is made by a different process. In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985).
In re claim 12, Nakamura discloses (e.g. FIG. 1 & 14) wherein the through-glass via is a first through-glass via (one of vias in holes 102), the hole is a first hole (one of 102), the glass core 10 further comprising a second through-glass via (another one of vias in another hole 102, see FIG. 14) extending from the top surface 10a of the layer of glass 10 to the bottom surface 10b of the layer of glass 10, the top surface 10a of the layer of glass 10 being dished between the first through-glass via and the second through-glass via. The surface 10a of layer of glass 10 is recessed relative top surfaces of 40 and 50. No specific “dished” shape has been claimed that would structurally distinguish over surface 10a that is recessed relative to top surfaces of 40 and 50. The term “dished” is understood to mean a concave shape which is indistinguishable over any recessed shape, such as the surface 10a recessed relative to the top surfaces of 40 and 50 defining a “dished” surface.
In re claim 13, Nakamura discloses (e.g. FIG. 1 & 14) wherein the through-glass via is a first through-glass via (one of vias in holes 102), the hole is a first hole (one of 102), the glass core 10 further comprising a second through-glass via (another one of vias in another hole 102, see FIG. 14) extending from the top surface 10a of the layer of glass 10 to the bottom surface 10b of the layer of glass 10, the top surface 10a of the layer of glass 10 being scalloped between the first through-glass via and the second through-glass via. The surface 10a of layer of glass 10 is recessed relative top surfaces of 40 and 50. No specific “scalloped” shape has been claimed that would structurally distinguish over surface 10a that is recessed relative to top surfaces of 40 and 50. The term “scalloped” is understood to mean a concave shape which is indistinguishable over any recessed shape, such as the surface 10a recessed relative to the top surfaces of 40 and 50 defining a “dished” surface.
In re claim 14, as best understood, Nakamura discloses (FIG. 14) further comprising one or more integrated circuit dies 100, “individual of one or more the integrated circuit dies” 100 attached to one or more of the plurality of conductive contacts 66.
In re claim 15, as best understood, Nakamura discloses (e.g. FIG. 1) wherein the plurality of dielectric layers 61,63 are first dielectric layers, the one or more conductive traces 62,64 are one or more first conductive traces, the one or more vias 61x,63x are one or more first vias, and the plurality of conductive contacts 66 are a first plurality of conductive contacts, the apparatus further comprising:
a plurality of second dielectric layers 71,73, “individual second dielectric layers positioned adjacent to another second dielectric layer”, “individual of the plurality of second dielectric layers” comprising one or more second conductive traces 72,74 and one or more second vias 71x,73x; and
a plurality of second conductive contacts (metal on 74, not shown, ¶ 115) located on a bottom dielectric layer of the plurality of second dielectric layers 71,73, the glass core 10 positioned between “the first dielectric layers” 61,63 and the plurality of second dielectric layers 71,73.
In re claim 16, Nakamura discloses (e.g. FIG. 1) further comprising an electrically conductive path from one of the first plurality of conductive contacts 66 to one of the plurality of second conductive contacts (metal on 74, ¶ 115), the electrically conductive path comprising at least one first conductive trace 62,64, at least one first via 61x,63x, the through-glass via 20,30, at least one second conductive trace 72,74, and at least one second via 71x,73x.
In re claim 17, Nakamura discloses (e.g. FIG. 1) further comprising a printed circuit board (motherboard, not shown, ¶ 115), the plurality of second conductive contacts (metal on 74) attached to the printed circuit board (motherboard, ¶ 115).
In re claim 26, as best understood, Nakamura discloses (e.g. FIGs. 1 & 14) an apparatus, comprising:
a printed circuit board (motherboard, not shown, ¶ 115); and
a substrate portion 2 attached to the printed circuit board (¶ 115), the substate portion comprising (FIG. 1):
a first plurality of dielectric layers 61,63, “individual of the first plurality of dielectric layers positioned adjacent to another dielectric layer”, “individual of the first plurality of dielectric layers” comprising one or more conductive traces 62,64 and one or more vias 61x,63x;
a plurality of first conductive contacts 66 located on a top dielectric layer 63 of the first dielectric layers,
a glass core 10 (¶ 29) positioned adjacent to a bottom dielectric layer 61 of the first dielectric layers, the glass core comprising:
a layer of glass 10 comprising a top surface 10a, a bottom surface 10b opposite the top surface 10a, and a hole 101,102 extending from the top surface 10a to the bottom surface 10b; and
a through-glass via (23a,23b inside hole 101,102) comprising fill material 23b that at least partially fills the hole 101,102, a pad 20A,20B, and a metal layer 23a, the through-glass via (23a,23b inside hole 101,102) extending through the hole 101,102, a portion of the pad 20A,20B located on the top surface 10a of the layer of glass 10, a first portion of the metal layer (portion of 23a inside 10) positioned adjacent to an inner wall of the hole 101,102, a second portion of the metal layer (23a outside 10) extending past the top surface 10a of the layer of glass 10 and into the pad 20A,20B, the fill material 23b comprising a first metal (¶ 50-51), the metal layer 23a comprising a second metal (¶ 50-51);
a second plurality of second dielectric layers 71,73 on an opposite side 10b of the glass core from the first plurality of dielectric layers 61,63, “individual of the second plurality of dielectric layers” comprising one or more second conductive traces 72,74 and one or more second vias 71x,73x; and
a plurality of second conductive contacts (metal on 74, not shown, ¶ 115) located on a bottom dielectric layer of the plurality of second dielectric layers 71,73, plurality of second conductive contacts attached to the printed circuit board (¶ 115).
In re claim 27, Nakamura discloses (FIG. 14) the substrate portion comprises one or more integrated circuit dies 100 attached to the plurality of first conductive contacts 66.
In re claim 28, Nakamura discloses (e.g. FIG. 14) further comprising an integrated circuit component 100 attached to the printed circuit board (motherboard, not shown, ¶ 115).
In re claim 30, Nakamura discloses (e.g. FIG. 1) wherein the pad 20A,20B comprises a protrusion (corresponding to portion 24a,24b) extending away from the top surface 10a of the layer of glass 10, the protrusion coaxial with the hole 101,102 (¶ 34).
In re claim 31, Nakamura discloses (e.g. FIG. 1) wherein the pad 20A,20B does not have a recess.
In re claim 32, Nakamura discloses (e.g. FIG. 1) wherein the first portion of the metal layer (23a inside 10) is positioned between the fill material 23b and the layer of glass 10.
Claims 1-2, 4, 6, 8, 10-17, 26-28 and 30-32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. US 2022/0302053 A1 (Park).
PNG
media_image2.png
660
828
media_image2.png
Greyscale
In re claim 1, as best understood, Park discloses (e.g. FIG. 2 & 8) an apparatus, comprising:
a plurality of dielectric layers 552,554,560, “individual of the plurality of dielectric layers positioned adjacent to another dielectric layer” (as best understood, 552,554,560 are adjacent to each other), “individual of the plurality of dielectric layers” 552,554,560 comprising one or more conductive traces (part of 582 above layer 560) and one or more vias (part of 582 in opening 560O) (alternatively, dielectric layers, traces and vias may be taught by respective layers of base substrate 600, see FIG. 8, ¶ 153);
a plurality of conductive contacts 584 (alternatively, 622 in FIG. 8) located on a top dielectric layer 560 of the dielectric layers; and
a glass core 510 (¶ 22) positioned adjacent to a bottom dielectric layer 552 (alternatively, layer of 610 closest to 510) of the dielectric layers, the glass core comprising:
a layer of glass 510 comprising a top surface 514, a bottom surface 512 opposite the top surface 514, and a hole (of through electrode 520) extending from the top surface 514 to the bottom surface 512; and
a through-glass via 520 comprising fill material that at least partially fills the hole, a pad 570, and a metal layer (barrier surrounding plug, not shown, ¶ 23), the through-glass via 520 extending through the hole, a portion of the pad 570 located on the top surface 514 of the layer of glass 510, a first portion of the metal layer (barrier film surrounding plug inside 510, ¶ 23) positioned adjacent to an inner wall of the hole, a second portion of the metal layer (portion of barrier film surrounding plug outside 510) extending past the top surface 514 of the layer of glass 510 and into the pad 570, the fill material comprising a first metal (Cu or W plug, ¶ 23), the metal layer comprising a second metal (conductive barrier film, ¶ 23).
In re claim 2, Park discloses (e.g. FIG. 2) wherein the pad 570 comprises a protrusion (corresponding to portion protruding above 550 with a thickness of T5, ¶ 43) extending away from the top surface 514 of the layer of glass 510, the protrusion coaxial with the hole (top portion above each through via 520 is coaxial with the via hole).
In re claim 4, Park discloses (e.g. FIG. 2) wherein the pad 570 does not have a recess (no recess on surface of pad 570 away from via 520).
In re claim 6, Park discloses (e.g. FIG. 2) wherein the first portion of the metal layer (barrier film surrounding plug 520 inside 510, ¶ 23) is positioned between the fill material 520 and the layer of glass 510.
In re claim 8, Park discloses (e.g. FIG. 2) wherein the metal layer (barrier film surrounding plug 520, ¶ 23) is a first metal layer, the through-glass via further comprising a second metal layer 572 located on the top surface 514 of the layer of glass 510 and positioned between the top surface 514 of the layer of glass and the pad 574, the second metal layer 572 comprising a third metal (¶ 38).
In re claim 10, Park discloses (e.g. FIG. 2) wherein the fill material is copper (¶ 23).
In re claim 11, as best understood, the limitation “the fill material is liquid metal” pertains to a product by process limitation. The final structure of the fill material does not distinguish over Park’s plug. In regard to the product by process language, since a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao and Sato et al., 190 USPQ 15 at 17 (CCPA 1976) (footnote 3). “[T]he lack of physical description in a product-by-process claim makes determination of the patentability of the claim more difficult, since in spite of the fact that the claim may recite only process limitations, it is the patentability of the product claimed and not of the recited process steps which must be established. We are therefore of the opinion that when the prior art discloses a product which reasonably appears to be either identical with or only slightly different than a product claimed in a product-by-process claim, a rejection based alternatively on either section 102 or section 103 of the statute is eminently fair and acceptable. As a practical matter, the Patent Office is not equipped to manufacture products by the myriad of processes put before it and then obtain prior art products and make physical comparisons therewith.” In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). See also In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the final product per se which must be determined for patentability in a "product by, all of" claim, and not the patentability of the process, and that an old or obvious product, whether claimed in "product by process" claims or not, is not patentable. Note that Applicant has the burden of proof in such cases, as the above case law makes clear. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based upon the product itself. The patentability of a product does not depend on its method of production. If the product in product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product is made by a different process. In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985).
In re claim 12, Park discloses (e.g. FIGs. 1-2) wherein the through-glass via 520 is a first through-glass via, the hole is a first hole, the glass core further comprising a second through-glass via (another one of 520) extending from the top surface 514 of the layer of glass 510 to the bottom surface 512 of the layer of glass 510, the top surface 514 of the layer of glass 510 being dished between the first through-glass via 520 and the second through-glass via 520. The surface 514 of layer of glass 510 is recessed relative the tips of plugs 520. No specific “dished” shape has been claimed that would structurally distinguish over surface 514 that is recessed relative to tips of plugs 520. The term “dished” is understood to mean a concave shape which is indistinguishable over any recessed shape, such as the surface 514 recessed relative to the ends of the plugs defining a “dished” surface.
In re claim 13, Park discloses (e.g. FIGs. 1-2) wherein the through-glass via 520 is a first through-glass via, the hole is a first hole, the glass core further comprising a second through-glass via (another one of 520) extending from the top surface 514 of the layer of glass 510 to the bottom surface 512 of the layer of glass 510, the top surface 514 of the layer of glass 510 being scalloped between the first through-glass via 520 and the second through-glass via 520. The surface 514 of layer of glass 510 is recessed relative the tips of plugs 520. No specific “scalloped” shape has been claimed that would structurally distinguish over surface 514 that is recessed relative to tips of plugs 520. The term “scalloped” is understood to mean a concave shape which is indistinguishable over any recessed shape, such as the surface 514 recessed relative to the ends of the plugs defining a “scalloped” surface.
In re claim 14, as best understood, Park discloses (FIG. 8) further comprising one or more integrated circuit dies 200,400, “individual of one or more the integrated circuit dies” 200,400 attached (indirectly and electrically) to one or more of the plurality of conductive contacts 584.
In re claim 15, as best understood, Park discloses (e.g. FIG. 2) wherein the plurality of dielectric layers 552,554,560 are first dielectric layers, the one or more conductive traces (582 above 560) are one or more first conductive traces, the one or more vias (582 in opening 560O) are one or more first vias, and the plurality of conductive contacts 584 are a first plurality of conductive contacts, the apparatus further comprising:
a plurality of second dielectric layers 534 (between plural wiring layers 532, ¶ 29-30), “individual second dielectric layers positioned adjacent to another second dielectric layer”, “individual of the plurality of second dielectric layers” comprising one or more second conductive traces 532 and one or more second vias 532 (wiring vias connecting wiring patterns on different wiring layers, ¶ 30); and
a plurality of second conductive contacts 536,540 located on a bottom dielectric layer (bottommost layer of 534) of the plurality of second dielectric layers, the glass core 510 positioned between “the first dielectric layers” 552,554,560 and the plurality of second dielectric layers 534.
In re claim 16, Park discloses (e.g. FIG. 2) further comprising an electrically conductive path from one of the first plurality of conductive contacts 584 to one of the plurality of second conductive contacts 536,540, the electrically conductive path comprising at least one first conductive trace (582 above 560), at least one first via (582 in opening 560O), the through-glass via 520, at least one second conductive trace 532, and at least one second via 532 (wiring vias connecting wiring patterns on different wiring layers, ¶ 30).
In re claim 17, Park discloses (e.g. FIG. 8) further comprising a printed circuit board 600 (¶ 153), the plurality of second conductive contacts 536,540 attached (indirectly and electrically) to the printed circuit board 600.
In re claim 26, as best understood, Park discloses (e.g. FIGs. 2 & 8) an apparatus, comprising:
a printed circuit board 600 (¶ 153); and
a substrate portion 500 attached to the printed circuit board 600, the substate portion 500 comprising (FIG. 2):
a first plurality of dielectric layers, 552,554,560, “individual of the first plurality of dielectric layers positioned adjacent to another dielectric layer”, “individual of the first plurality of dielectric layers” (as best understood, 552,554,560 are adjacent to each other) comprising one or more conductive traces (part of 582 above layer 560) and one or more vias (part of 582 in opening 560O);
a plurality of first conductive contacts 584 located on a top dielectric layer 560 of the first dielectric layers,
a glass core 510 (¶ 22) positioned adjacent to a bottom dielectric layer 552 of the first dielectric layers, the glass core comprising:
a layer of glass 510 comprising a top surface 514, a bottom surface 512 opposite the top surface 514, and a hole (of through electrode 520) extending from the top surface 514 to the bottom surface 512; and
a through-glass via 520 comprising fill material that at least partially fills the hole, a pad 570, and a metal layer (barrier surrounding plug, not shown, ¶ 23), the through-glass via 520 extending through the hole, a portion of the pad 570 located on the top surface 514 of the layer of glass 510, a first portion of the metal layer (barrier film surrounding plug inside 510, ¶ 23) positioned adjacent to an inner wall of the hole, a second portion of the metal layer (portion of barrier film surrounding plug outside 510) extending past the top surface 514 of the layer of glass 510 and into the pad 570, the fill material comprising a first metal (Cu or W plug, ¶ 23), the metal layer comprising a second metal (conductive barrier film, ¶ 23);
a second plurality of dielectric layers 534 (between plural wiring layers 532, ¶ 29-30) on an opposite side of the glass core 510 from the first plurality of dielectric layers 552,554,560, “individual second plurality of dielectric layers” comprising one or more conductive traces 532 and one or more second vias 532 (wiring vias connecting wiring patterns on different wiring layers, ¶ 30); and
a plurality of second conductive contacts 536,540 located on a bottom dielectric layer (bottommost layer of 534) of the second plurality of dielectric layers, the plurality of second conductive contacts 536,540 attached (indirectly and electrically) to the printed circuit board 600.
In re claim 27, Park discloses (FIG. 8) the substrate portion comprises one or more integrated circuit dies 200,400 attached (indirectly and electrically) to the plurality of first conductive contacts 584.
In re claim 28, Park discloses (e.g. FIG. 8) further comprising an integrated circuit component 200,400 attached (indirectly and electrically) to the printed circuit board 600.
In re claim 30, Park discloses (e.g. FIG. 2) wherein the pad 570 comprises a protrusion (corresponding to portion protruding above 550 with a thickness of T5, ¶ 43) extending away from the top surface 514 of the layer of glass 510, the protrusion coaxial with the hole (top portion above each through via 520 is coaxial with the via hole).
In re claim 31, Park discloses (e.g. FIG. 2) wherein the pad 570 does not have a recess (no recess on surface of pad 570 away from via 520).
In re claim 32, Park discloses (e.g. FIG. 2) wherein the first portion of the metal layer (barrier film surrounding plug 520 inside 510, ¶ 23) is positioned between the fill material 520 and the layer of glass 510.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura.
In re claim 3, Nakamura discloses (e.g. FIG. 1) wherein a thickness of the protrusion (e.g. 24b) is about 6 µm to 24µm (¶ 53). The claimed range of range of about 1 microns to about 20 microns is obvious over Nakamura teaching about 6 µm to 24µm. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997). See MPEP 2144.05.
Claims 3 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park.
In re claim 3, Park discloses (e.g. FIG. 2) wherein a thickness T5 of the protrusion (portion of 570 protruding above 550) is about 4 µm or less (¶ 43). The claimed range of range of about 1 microns to about 20 microns is obvious over Park teaching about 4 µm or less. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 7, Park discloses (e.g. FIG. 2) wherein the second portion of the metal layer (portion of barrier film surrounding plug exposed by 510) extends into the pad by a distance T4. Park further discloses T4 is less than T5 which is about 4 µm or less (¶ 43). Forming T4 to be in a range of about 1 microns to about 20 microns is obvious over Park teaching an overlapping range. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Claims 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and further in view of Schrauben et al. US 2019/0019736 A1 (Schrauben).
In re claim 5, Park discloses (e.g. FIG. 2) wherein the second metal (conductive barrier film, ¶ 23) is a metal or metal nitride. Park does not explicitly disclose the second metal is titanium or ruthenium. Schrauben teaches barrier layer formed of titanium nitride for preventing diffusion of copper (¶ 134). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Park’s barrier metal layer to include titanium as the second metal to form a barrier layer that is effective in preventing diffusion as taught by Schrauben. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
In re claim 18, Park discloses the claimed invention including a glass core 510 (¶ 22). Park does not explicitly disclose the glass comprises aluminum, oxygen, boron, silicon, and an alkaline-earth metal. However, Schrauben discloses interconnecting substrate comprising a glass base layer including aluminoborosilicate glass that include alkaline earth modifiers (¶ 118). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Park’s glass core using aluminoborosilicate glass modified with alkaline earth metal as taught by Schrauben as a suitable glass material as a base layer for forming interconnections as taught by Schrauben. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura or Park as applied to claim 26 above, and further in view of Bozorg-Grayeli et al. US 2020/0411395 A1 (Bozorg-Grayeli).
In re claim 29, Nakamura discloses the claimed invention including a semiconductor package as shown in FIG. 14 to be mounted onto a motherboard (¶ 115). Park also discloses the claimed invention including a semiconductor package as shown in FIG. 8 including the printed circuit board 600 (¶ 131). Nakamura and Park do not explicitly disclose a housing that encloses the printed circuit board.
However, Bozorg-Grayeli teaches providing a housing around IC package and printed circuit board (¶ 200) for protecting the device.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form a housing around Nakamura or Park’s semiconductor package that encloses the semiconductor package printed circuit board to provide protection as taught by Bozorg-Grayeli.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896