CTNF 17/958,094 CTNF 97667 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendments 2. The Amendments filed February 17 th , 2026 in response to the Non-Final Office Action mailed 11/14/2025 are noted. 3. Claim 19 is now canceled; Claim 26 is newly-added; Claims 1-18 and 20-26 remain pending in the application. 4. Claims 1-18 and 20-26 have been fully considered in examination. Information Disclosure Statement The information disclosure statement (IDS) submitted on 02/13/2026 and 03/03/2026 were filed after the mailing date of the Non-Final Rejection on 11/14/2025. The submission(s) is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Objections 07-29-01 AIA Claim 26 is objected to because of the following informalities: Claim 26, lines 1-2: “a buffer layer in on the substrate” should (presumably) read --- a buffer layer on the substrate --- Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2, 8, 10, 20, 22, and 24-26 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Vellianitis (U.S. PG Pub No US2021/0391471A1) . Regarding claim 1, Vellianitis teaches a device (80T) fig. 8 [0039] comprising: a source region (portion of 120 in direct contact with source terminal right 170) fig. 8 [0039]; a drain region (portion of 120 in direct contact with drain terminal left 170) fig. 8 [0039]; a channel (comprising channel region portion of 120 horizontally between source region of 120 and drain region of 120) fig. 8 [0038-0039] between the source region (portion of 120 in direct contact with right 170) and the drain region (portion of 120 in direct contact with left 170); a gate electrode (141) fig. 8 [0012, 0039] (“gate layer” [0039] acting as gate electrode [0012]); and a gate dielectric (131) fig. 8 [0039] between (vertically between) the gate electrode (141) and the channel (channel region portion of 120 horizontally between source region of 120 and drain region of 120), wherein the gate dielectric (131) is ferroelectric [0039], wherein the gate dielectric (131 formed of 130 material) [0027, 0035, 0039] comprises scandium, aluminum, and nitrogen [0027] (“The high-Sc content AlScN layer may function as a ferroelectric layer… third material layer 130 (as a ferroelectric layer)” [0027 Vellianitis ]). Regarding claim 2, Vellianitis teaches the device (80T) fig. 8 [0039] of claim 1. Vellianitis also teaches wherein the channel (comprising channel region portion of 120 and adjoined 110 layer ) fig. 8 [0014, 0038-0039] comprises gallium and nitrogen (110 portion of channel material may be composed of gallium nitride GaN [0014]). Regarding claim 8, Vellianitis teaches a device (80T) fig. 8 [0039] comprising: a transistor (80T), the transistor (80T) comprising a gate dielectric (131) fig. 8 [0039], wherein the gate dielectric (131) is ferroelectric [0039], wherein the gate dielectric (131 formed of 130 material) [0027, 0035, 0039] comprises scandium, aluminum, and nitrogen [0027] (“The high-Sc content AlScN layer may function as a ferroelectric layer… third material layer 130 (as a ferroelectric layer)” [0027 Vellianitis ]). Regarding claim 10, Vellianitis teaches the device (80T) fig. 8 [0039] of claim 8. Vellianitis also teaches wherein the transistor (80T) comprises a channel (comprising channel region portion of 120 and adjoined 110 layer ) fig. 8 [0014, 0038-0039], wherein the channel (120 with 110) comprises gallium and nitrogen (110 portion of channel material may be composed of gallium nitride GaN [0014]). Regarding claim 20, Vellianitis teaches a method [see figs. 1-8, 0013] comprising: depositing a channel (120) fig. 2 [0020, 0039] of a transistor (80T) fig. 8 [0039]; depositing a gate dielectric (130/131) fig. 3 [0027, 0039] of the transistor (80T), wherein the gate dielectric (130/131) and the channel (120) are in direct contact, wherein the gate dielectric (131/130) is ferroelectric [0039], wherein the gate dielectric (131 formed of 130 material) [0027, 0035, 0039] comprises scandium, aluminum, and nitrogen [0027] (“the high-Sc content AlScN layer may function as a ferroelectric layer… third material layer 130 (as a ferroelectric layer)” [0027 Vellianitis ]); and depositing a gate electrode (140/141) fig. 4 [0028-0029, 0039] (“gate layer” [0039] acting as gate electrode [0012]) of the transistor (80T), wherein the gate electrode (141 formed of 140) and the gate dielectric (131 formed of 130) are in direct contact. Regarding claim 22, Vellianitis teaches the method [see figs. 1-8, 0013] of claim 20. Vellianitis also teaches wherein the channel (comprising channel region portion of 120 and adjoined 110 layer ) fig. 8 [0014, 0038-0039] comprises gallium and nitrogen (110 portion of channel material may be composed of gallium nitride GaN [0014]). Regarding claim 24, Vellianitis teaches the method [see figs. 1-8, 0013] of claim 20. Vellianitis also teaches wherein depositing the gate dielectric (130/131) fig. 3 [0027, 0039] comprises depositing the gate dielectric (130 material used to form gate dielectric 131) with use of atomic layer deposition (“ALD” [0016, 0024, 0026]). Regarding claim 25, Vellianitis teaches the method [see figs. 1-8, 0013] of claim 20. Vellianitis also teaches wherein depositing the channel (120) fig. 2 [0020, 0039] comprises depositing the channel (120) with use of atomic layer deposition (“ALD” [0016, 0020]). Regarding claim 26, Vellianitis teaches the device (80T) fig. 8 [0039] of claim 1. Vellianitis also teaches further comprising a substrate (100 with 150) fig. 8 [0014, 0034, 0039] (100 with 150 acting as a substrate to support overlying components) and a buffer layer (160) fig. 8 [0036-0037, 0039] (acting as a buffer between adjacent contact structures 170) fig. 8 [0038-0039] on (supported by top of) the substrate (100 with 150) and in direct contact with the substrate (comprising 150), wherein the gate electrode (141) fig. 8 [0012, 0039] (“gate layer” [0039] acting as gate electrode [0012]) is on the (supported by bottom of) buffer layer (160) and in direct contact with the buffer layer (160), wherein the gate dielectric (131) fig. 8 [0039] is on (supported by top of) the gate electrode (141) and in direct contact with the gate electrode (141), wherein the channel (channel region portion of 120 horizontally between source region of 120 and drain region of 120) fig. 8 [0038-0039] is on (supported by bottom of) the gate dielectric (131) and in direct contact with the gate dielectric (131) . 07-15 AIA Claim s 15 and 16 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Xie (U.S. PG Pub No US2023/0290834A1) . Regarding claim 15, Xie teaches a device [see fig. 2, 0035] comprising: a transistor (see fig. 2, at step 210) [0035] comprising: a source region (18) fig. 2 [0035]; a drain region (20) fig. 2 [0035]; a channel (comprising 14) fig. 2 [0035] (acting as a channel between horizontally) between the source region (18) and the drain region (20); a gate electrode (28) fig. 2 [0035] (gate metal acting as gate electrode in transistor structure [0035]); and a gate dielectric (10) fig. 2 [0035] (comprising 10 acting as gate dielectric separating gate 28 and channel 14) between the gate electrode (28) and the channel (14), wherein the gate dielectric (10) comprises scandium, aluminum, and nitrogen (ScAlN layer 10) [0035], wherein a threshold voltage of the transistor is greater than 0 volts and less than 0.5 volts (when recessed and without AlOx, threshold voltage is slightly greater than 0 V and less than 0.5 V; see [0041] and annotated fig. 7 of Xie below ). PNG media_image1.png 577 758 media_image1.png Greyscale Annotated fig. 7 of Xie Regarding claim 16, Xie teaches the device [see fig. 2, 0035] device of claim 15. Xie also teaches wherein the channel (comprising 14) fig. 2 [0035] comprises gallium and nitrogen (14 is formed of GaN [0035]) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 3, 5-7, 11-14, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Vellianitis (U.S. PG Pub No US2021/0391471A1), as applied in claims 1, 8, and 20 above, in view of Yu (US2022/0271220A1) (of record) . Regarding claim 3, Vellianitis teaches the device (80T) fig. 8 [0039] of claim 1. However, Vellianitis does not explicitly disclose teaches wherein the channel (comprising channel region portion of 120) fig. 8 [0038-0039] comprises molybdenum and sulfur (AlScN instead) [0023]. Yu teaches a transistor device (100) fig. 1 [0034-0038] wherein the channel [0036] comprises molybdenum and sulfur (includes 2D MoS2 layer) [0036, 0058]. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Vellianitis such that the channel comprises a 2D material such as molybdenum disulfide [0058] in order to enable use of the semiconductor element for applications such as memory processing [0056-0058] (capable of memory operations) with lower contact resistance [0057] and gate leakage current [0057], as taught by Yu . Regarding claim 5, Vellianitis teaches the device (80T) fig. 8 [0039] of claim 1. Vellianitis also teaches wherein the device (80T) comprises a transistor (80T is a “transistor structure” [0039]), wherein the transistor (80T) comprises the source region (portion of 120 in direct contact with source terminal right 170) fig. 8 [0039], the drain region (portion of 120 in direct contact with drain terminal left 170) fig. 8 [0039], the channel (channel region portion of 120 horizontally between source region of 120 and drain region of 120) fig. 8 [0038-0039], the gate dielectric (131) fig. 8 [0039], and the gate electrode (141) fig. 8 [0039]. However, Vellianitis does not explicitly disclose wherein the transistor (80T) is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor. Yu teaches a transistor device (100) fig. 1 [0034-0038] wherein the transistor (110) fig. 1 [0035] is a FinFET [0013, 0061] (or HEMT). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Vellianitis such that the channel comprises a 2D material such as molybdenum disulfide [0058] in a transistor configured as a FinFET [0013, 0035, 0061] in order to enable better usage of the semiconductor element for applications such as memory processing [0056-0058] (capable of memory operations) with lower contact resistance [0057] and gate leakage current [0057], as taught by Yu . With respect to X/Y/Z claims below, they contain identical grounds of rejection and claim phrasing – hence they are not repeated for simplicity: Regarding claim 6/13 , Vellianitis does not explicitly disclose a processor comprise the device (80T) fig. 8 [0039] of claim 1/8 . Yu teaches a processor (capable of memory operations/processing) [0056-0058 Yu ] comprising the device (100) fig. 1 [0058 Yu ] of claim 1/8/15 (in view Chen ). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Vellianitis to be configured with the various features of Yu (such as 2D material such as molybdenum disulfide [0058] in a transistor configured as a FinFET [0013, 0035, 0061] in order to enable better usage of the semiconductor element for applications such as memory processing [0056-0058] (capable of memory operations) with lower contact resistance [0057] and gate leakage current [0057], as taught by Yu . Regarding claim 7/14 , Vellianitis in view of Yu (with reference to Yu ) teaches a system (100) fig. 1 [0058] comprising the processor (comprising 110) fig. 1 [0036] of claim 6/13 and one or more memory devices [0056-0058 Yu ]. Regarding claim 11, Vellianitis teaches the device (80T) fig. 8 [0039] of claim 8. Vellianitis also teaches wherein the transistor (80T) comprises a channel (comprising channel region portion of 120) fig. 8 [0014, 0038-0039]. However, Vellianitis does not explicitly disclose wherein the channel (120) comprises molybdenum and sulfur. Yu teaches a transistor device (100) fig. 1 [0034-0038] wherein the channel [0036] comprises molybdenum and sulfur (includes 2D MoS2 layer) [0036, 0058]. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Vellianitis such that the channel comprises a 2D material such as molybdenum disulfide [0058] in order to enable use of the semiconductor element for applications such as memory processing [0056-0058] (capable of memory operations) with lower contact resistance [0057] and gate leakage current [0057], as taught by Yu . Regarding claim 12, Vellianitis teaches the device (80T) fig. 8 [0039] of claim 8. However, Vellianitis does not explicitly disclose wherein the transistor (80T) is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor. Yu teaches a transistor device (100) fig. 1 [0034-0038] wherein the transistor (110) fig. 1 [0035] is a FinFET [0013, 0061] (or HEMT). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Vellianitis such that the channel comprises a 2D material such as molybdenum disulfide [0058] in a transistor configured as a FinFET [0013, 0035, 0061] in order to enable better usage of the semiconductor element for applications such as memory processing [0056-0058] (capable of memory operations) with lower contact resistance [0057] and gate leakage current [0057], as taught by Yu . Regarding claim 23, Vellianitis teaches the device (80T) fig. 8 [0039] of claim 20. However, Vellianitis does not explicitly disclose teaches wherein the channel (comprising channel region portion of 120) fig. 8 [0038-0039] comprises molybdenum and sulfur (AlScN instead) [0023]. Yu teaches a method [see fig. 10, 0061] of forming a transistor device (100) fig. 1 [0034-0038] wherein the channel [0036] comprises molybdenum and sulfur (includes 2D MoS2 layer) [0036, 0058]. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Vellianitis such that the channel comprises a 2D material such as molybdenum disulfide [0058] in order to enable use of the semiconductor element for applications such as memory processing [0056-0058] (capable of memory operations) with lower contact resistance [0057] and gate leakage current [0057], as taught by Yu . 07-21-aia AIA Claim s 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Xie (U.S. PG Pub No US2023/0290834A1), as applied in claim 15 above, in view of Yu (US2022/0271220A1) (of record) . Regarding claim 17, Xie teaches the device [see fig. 2, 0035] of claim 15. However, Xie does not explicitly disclose wherein the channel (comprising 14) fig. 2 [0035] comprises molybdenum and sulfur (GaN instead). Yu teaches a transistor device (100) fig. 1 [0034-0038] wherein the channel [0036] comprises molybdenum and sulfur (includes 2D MoS2 layer) [0036, 0058]. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Xie such that the channel comprises a 2D material such as molybdenum disulfide [0058] in order to enable use of the semiconductor element for applications such as memory processing [0056-0058] (capable of memory operations) with lower contact resistance [0057] and gate leakage current [0057], as taught by Yu . Regarding claim 18, Xie teaches the device [see fig. 2, 0035] of claim 15. However, Xie does not explicitly disclose wherein the transistor [see fig. 2, 0035] is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor. Yu teaches a transistor device (100) fig. 1 [0034-0038] wherein the transistor (110) fig. 1 [0035] is a FinFET [0013, 0061] (or HEMT). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor device of Xie such that the channel comprises a 2D material such as molybdenum disulfide [0058] in a transitor configured as a FinFET [0013, 0035, 0061] in order to enable better usage of the semiconductor element for applications such as memory processing [0056-0058] (capable of memory operations) with lower contact resistance [0057] and gate leakage current [0057], as taught by Yu . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4, 9, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Claim 4 is considered to contain allowable subject matter because the prior art of record neither anticipates nor renders obvious the claimed limitations “wherein a threshold voltage of the transistor is greater than 0 volts and less than 0.5 volts.” in the context of claim 4, dependent upon claim 1. Claim 10 is considered to contain allowable subject matter because the prior art of record neither anticipates nor renders obvious the claimed limitations “wherein a threshold voltage of the transistor is greater than 0 volts and less than 0.5 volts.” in the context of claim 10, dependent upon claim 8. Claim 21 is considered to contain allowable subject matter because the prior art of record neither anticipates nor renders obvious the claimed limitations “wherein a threshold voltage of the transistor is greater than 0 volts and less than 0.5 volts.” in the context of claim 21, dependent upon claim 20. Further, it is noted that if independent claim 15 were amended to recite the limitation(s) “… wherein the gate dielectric is ferroelectric”, in conjunction with the allowable subject matter indicated above – already present in amended independent claim 15 - independent claim 15 would also be considered to be in condition for allowance . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Remaining references made available on the PTO-892 form (of record) are considered relevant to the present disclosure because they all feature transistor devices with at least some of the claimed materials and/or structures. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEAN AYERS WINTERS/Examiner, Art Unit 2892 06/05/2026 Application/Control Number: 17/958,094 Page 2 Art Unit: 2892 Application/Control Number: 17/958,094 Page 3 Art Unit: 2892 Application/Control Number: 17/958,094 Page 4 Art Unit: 2892 Application/Control Number: 17/958,094 Page 5 Art Unit: 2892 Application/Control Number: 17/958,094 Page 6 Art Unit: 2892 Application/Control Number: 17/958,094 Page 7 Art Unit: 2892 Application/Control Number: 17/958,094 Page 8 Art Unit: 2892 Application/Control Number: 17/958,094 Page 9 Art Unit: 2892 Application/Control Number: 17/958,094 Page 10 Art Unit: 2892 Application/Control Number: 17/958,094 Page 11 Art Unit: 2892 Application/Control Number: 17/958,094 Page 12 Art Unit: 2892 Application/Control Number: 17/958,094 Page 13 Art Unit: 2892
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