DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 20 2025 has been entered.
Claim Objections
Claim 1 is objected to. The Examiner suggests further differentiating between claims first and second electrical contacts and functional circuitry of the electrical integrated circuit chip, as it is vague as to whether the electrical contacts are the same element as the claimed functional circuitry.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3, and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “wherein the electrical integrated circuit chip is bonded to the first heat spreading substrate such that the first electrical contacts do not contact the first heat spreading substrate”. It is unclear, however, what sort of contact between the first electrical contacts and the first heat spreading substrate is not allowed by the claim. Specifically, it is unclear whether Applicant intends to claim that the first electrical contacts are not in electrical, physical, or thermal contact with the first heat spreading substrate. The Examiner notes, however, that Applicant only has support for the first electrical contacts not being in direct physical contact with the first heat spreading substrate. The drawings clearly show that the electrical contacts of the chip 102 and the cold plate (which is assumed to be the claimed first heat spreading substrate) are in thermal contact and indirect physical contact, and can potentially be electrically contacting each other, see pages 5-6 of the instant specification that describes a ground connection through the thermal contacts between the cold plate 202 and the functional circuitry of the chip 102. Regarding the support for direct physical contact, Applicant discloses on page 5 of the instant specification “the only direct contacts between chip 102 and cold plate 202 are via the thermal contacts 302/304”. Thus, the Examiner suggests amending the claim to require that the first electrical contacts and the first heat spreading substrate are specifically not in direct physical contact.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-9, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Alapati et al. (“Alapati” US Patent No. 11,107,799) and Mallik et al. (“Mallik” US 2021/0305119).
Regarding claim 1, Alapati discloses a method of heat-sinking an electrical integrated circuit chip (1440, see Figure 14), the method comprising:
fabricating [two or more] first thermal contact pad[s] (col. 17, lines 9-12 disclose an epoxy bonding layer between the EIC 1440 and the mesa structure 1472 which is interpreted to be a thermal contact pad since the material would provide a thermal dissipation path from the EIC 1440) on the electrical integrated circuit chip (1440, see Figure 14 and col. 17 lines 9-12) which are electrically isolated from functional circuitry (1442, since the thermal contact pad is an electrically insulating material, epoxy is electrically insulating, the thermal contact pad is thus isolated from electrical circuitry, i.e. does not transmit electrical signals) of the electrical integrated circuit chip (1440);
bonding the electrical integrated circuit chip (1440) to a first heat spreading substrate (1470), wherein the [two or more] first thermal contact pad[s] (epoxy layer, col. 17 lines 9-12) are bonded to the first heat spreading substrate (1470) via first thermally conductive bonds (one or more metal layers 1472, see col. 17 lines 3-12, coated on the mesa structure 1472 which is bonded to the first heat spreading substrate 1470, thus are interpreted to be thermally conductive bonds, and thus the first thermal contact pad are bonded to the first heat spreading substrate 1470 through intervening bonding elements/layers);
wherein the electrical integrated circuit chip (1440) includes first electrical contacts (1442) on a first surface of the electrical integrated circuit chip (1440, upper surface, see Figure 14) and second electrical contacts (see contacts on the bottom surface of the EIC 1440 and the top surface of the PIC 1430 in Figure 14) on a second surface of the electrical integrated circuit chip (1440, lower surface) opposite the first surface (upper surface);
wherein the [two or more] first thermal contact pad[s] are (epoxy bonding layer, col. 12 lines 90-12) disposed on the first surface (upper surface, see col. 17 lines 9-12);
wherein the electrical integrated circuit chip (1440) is bonded to the first heat spreading substrate (1470, through other layers/elements, see Figure 14) such that the first electrical contacts (1442) do not contact the first heat spreading substrate (1470, see Figure 14 which shows the first electrical contacts not in direct physical contact with the first heat spreading substrate 1470).
Alapati does not disclose two or more thermal contact pads.
Mallik discloses, however, fabricating two or more first thermal contact pads (260 on chip 210, see Figure 2D) on the electrical integrated circuit chip (210) bonded to the first heat spreading substrate (271, has high thermal conductivity and is connected to the heat sink, and thus serves as a heat spreading substrate) via thermally conductive bonds (274, see Figure 2D).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Mallik into the teachings of Alapati to substitute one known element (thermal contact pads 260 on chip 210 of Mallik) for another known element (metal layer 1274 of Alapati) with the predictable result of providing heat dissipation for the integrated circuit chips. See MPEP 2143 (I)(B).
Regarding claim 2, Alapati discloses wherein the first heat spreading substrate (1470) is selected from the group consisting of:
molybdenum, tungsten, silicon, sapphire, and diamond (col. 15 lines 51-52 discloses the heat spreading substrate 1270 is made of silicon, and col. 17 lines 1-2 disclose the first heat spreading substrate 1470 may be the same as 1270, thus 1470 is also made of silicon).
Regarding claim 5, Alapati discloses wherein the first heat spreading substrate (1470) is thermally coupled to a cryogenic environment at 100 K or less (disclosed in col. 14, lines 45-50, device may be attached to a cooling device such that the chips may operate at cryogenic temperatures).
Regarding claim 6, Alapati further discloses bonding a photonic integrated circuit (1430) to the electrical integrated circuit chip (1440, see Figure 14) on a side of the electrical integrated circuit chip (1440, lower side) opposite the first heat spreading substrate (1470, see Figure 14).
Regarding claim 7, Alapati further discloses fabricating [two or more] second thermal contact pad[s] (layer on lower surface of the PIC die 1430, shown in modified Figure 14) on the photonic integrated circuit chip (1430) which are electrically isolated from functional circuitry (1432) of the photonic integrated circuit chip (1430, shown in modified Figure 14).
Alapati does not disclose fabricating two or more second thermal contact pads.
Mallik discloses fabricating two or more second thermal contact pads (260 on chip 205, see Figure 2D, while chip 205 is not a photonic integrated circuit chip, one of ordinary skill in the art would readily recognize that the thermal contact pads could be connected to any type of chip for heat dissipation).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Mallik into the teachings of Alapati to substitute one known element (thermal contact pads 260 on chip 205 of Mallik) for another known element (layer on lower surface of the PIC die of Alapati) with the predictable result of providing heat dissipation for the integrated circuit chips. See MPEP 2143 (I)(B).
Regarding claim 8, Alapati further discloses bonding the photonic integrated circuit chip (1430) to a second heat spreading substrate (1410, see Figure 14), wherein the [two or more] second thermal contact pad[s] (shown in modified Figure 14) are bonded to the second heat spreading substrate (1410) via second thermally conductive bonds (layer below the second thermal contact pad, and the two or more second thermal contact pads incorporated by Mallik, shown in modified Figure 14).
Regarding claim 9, Alapati discloses wherein the second heat spreading substrate (1410) is selected from the group consisting of:
molybdenum, tungsten, silicon, sapphire, and diamond (the handle wafer or second heat spreading substrate 1410 is the same as the handle wafer 1210 in Figure 12, which is made of silicon, thus 1410 is made of silicon, see col. 15, line 17).
Regarding claim 12, Alapati discloses wherein the second heat spreading substrate (1410) is thermally coupled to a cryogenic environment at 100 K or less (disclosed in col. 14, lines 45-50, device may be attached to a cooling device such that the chips may operate at cryogenic temperatures).
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Claims 3-4 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Alapati and Mallik as applied to claims 1 and 9 above, and further in view of Choi (US Pub. 2021/0343631).
Regarding claim 3, Choi discloses surface treating (upper metal grain layer 120) the first heat spreading substrate (110B, Figure 1B) to improve bonding of the first thermally conductive bonds (upper 130, present but not labeled in Figure 1B, labeled in Figure 2) to the first heat spreading substrate (110B, shown in Figures 1B and 2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Choi into the teachings of Alapati to include further comprising surface treating the first heat spreading substrate to improve bonding of the first thermally conductive bonds to the first heat spreading substrate, for the purpose of improving reliability of bonded parts (Choi, abstract).
Regarding claim 4, Choi discloses: wherein the surface treating comprises surface coating (upper 120 in Figure 1B) the first heat spreading substrate (110B) with a metal (upper 120, para. [0039]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Choi into the teachings of Alapati to include wherein the surface treating comprises surface coating the first heat spreading substrate with a metal, for the purpose of improving reliability of bonded parts (Choi, abstract).
Regarding claim 10, Choi discloses surface treating (lower metal grain layer 120) the second heat spreading substrate (110A) to improve bonding of the second thermally conductive bonds (lower 130, present but not labeled in Figure 1B, labeled in Figure 2) to the second heat spreading substrate (110A).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Choi into the teachings of Alapati to include further comprising surface treating the second heat spreading substrate to improve bonding of the second thermally conductive bonds to the second heat spreading substrate, for the purpose of improving reliability of bonded parts (Choi, abstract).
Regarding claim 11, Choi discloses wherein the surface treating comprises surface coating (lower 120, Figure 1B) the second heat spreading substrate (110A) with a metal (lower 120, para. [0039]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Choi into the teachings of Alapati to include wherein the surface treating comprises surface coating the second heat spreading substrate with a metal, for the purpose of improving reliability of bonded parts (Choi, abstract).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any embodiment or interpretation of the reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899