DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Amendments filed October 15th, 2025 in response to the Non-Final Office Action mailed 05/15/2025 are noted.
Applicant’s amendment(s) to the claims have overcome the 35 U.S.C. § 112 rejection(s)
previously set forth in the Non-Final Office Action mailed 05/15/2025, so the 35 U.S.C. § 112
rejection(s) have been withdrawn.
Applicant’s other amendments to the claims are noted.
Claims 14-18 are withdrawn; Claim 19 is canceled; Claims 20-21 are newly-added.
Claims 1-13 and 20-21 have been fully considered in Examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-13 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over
Yedinak (U.S. PG Pub No US2022/0181480A1) (of record) in view of Su (U.S. PG Pub No US 2022/0223708 A1).
Regarding claim 1, Yedinak teaches an integrated circuit (200) fig. 2 [0030], comprising:
first (left 232) fig. 2A [0031] and second (right 232) fig. 2A [0031] trenches in a semiconductor substrate (comprising 244) fig. 2A [0035];
a semiconductor mesa (234) fig. 2 [0031] between the first (left 232) and second (right 232) trenches;
a source region (comprising left 228 with bordering region of 244) fig. 2A [0034] having a first (p-type) [0034] conductivity type and a body region (bordering region of 244 of MOSFET) [0034] having an opposite second conductivity type (n-type MOSFET) [0034-0035] within the semiconductor mesa (234);
a trench shield (212) fig. 2A [0033] within the first trench (left 232);
a gate electrode (233) fig. 2A [0033] over the trench shield (212) between first (left) and second (right) sidewalls of the first trench (left 234);
a gate dielectric (214) fig. 2A [0033] on a sidewall of the first trench (left 232) between the gate electrode (233) and the body region (bordering region of 244 of MOSFET {0034]);
a pre-metal dielectric (PMD) layer (246) fig. 2A [0035] over the gate electrode (233);
a gate contact (236) fig. 2A [0032] through the PMD layer (246) that touches the gate electrode (233) between the first (left) and second (right) sidewalls; and
a trench shield contact (222) fig. 2E [0038] (shown in 2e-2e cross-sectional view of fig. 2) [0038] through the PMD layer (246) that touches the trench shield (212) between the first (left) and second (right) sidewalls (232); and
a source contact (227) fig. 2B [0036].
However, Yedinak does not explicitly disclose a source contact (227) that extends through the source region (comprising 228) fig. 2B [0036] into the body region (bordering region of 244 of MOSFET) [0034].
Su teaches an integrated circuit (10) fig. 1A [0038] comprising a source contact (186) [0038] that extends through the source region (182) [0038] into the body region (170) [0038].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit of Yedinak such that the source contact is made to extend into the source and body regions rearranged according to Su [0038] in order to optimize chip area component performance [0006-0008] and improve the s/d contact-connection(s) [0038], as taught by Su.
Regarding claim 2, Yedinak teaches the integrated circuit (200) fig. 2 [0030] of claim 1. Yedinak also teaches wherein the gate contact (236) fig. 2A [0032] and the trench shield contact (222) fig. 2E [0038] have a same depth (pass through a same depth) below a top surface of the semiconductor substrate (comprising 244) fig. 2A [0035].
Regarding claim 3, Yedinak teaches the integrated circuit (200) fig. 2 [0030] of claim 1. Yedinak also teaches wherein the source contact (227) fig. 2B [0036] and the gate contact (236) fig. 2A [0032] having a same depth (pass through a same depth) below a top surface of the semiconductor substrate (comprising 244) fig. 2A [0035].
Regarding claim 4, Yedinak teaches the integrated circuit (200) fig. 2 [0030] of claim 1. Yedinak also teaches wherein tops (peripheral surfaces) of the gate contact (236) fig. 2A [0032], the trench shield contact (222) fig. 2E [0038] and the source contact (227) fig. 2B [0036] are coplanar (all coplanar with top of 246 interfacing 204).
Regarding claim 5, Yedinak teaches the integrated circuit (200) fig. 2 [0030] of claim 1. Yedinak also teaches wherein the PMD layer (246) fig. 2A [0035] comprises a planarized dielectric layer (246 is shown with a flat top and smoothed/rounded corners indicative of a planarization process).
Regarding claim 6, Yedinak teaches the integrated circuit (200) fig. 2 [0030] of claim 5. Yedinak also teaches and further including interconnections (202, 204) fig. 2A [0031-0032] in a metal layer (“metallization”) [0031-0032] over the planarized dielectric layer (246), the interconnections (202, 204) having top surfaces that are coplanar.
Regarding claim 7, Yedinak teaches the integrated circuit (200) fig. 2 [0030] of claim 1. Yedinak also teaches wherein the trench shield contact (222) fig. 2E [0038] electrically contacts the trench shield (212) fig. 2E [0033] between the first (left) and second (right) sidewalls.
Regarding claim 8, Yedinak teaches the integrated circuit (200) fig. 2 [0030] of claim 7. Yedinak also teaches wherein the trench shield (212) fig. 2A [0033] has a first portion (see modified fig. 2E below) with a top surface (top of boxed “1st portion” below) at a first depth below a top surface of the semiconductor substrate (comprising 244) fig. 2E [0035], and has a second portion (see modified fig. 2E below) having a top surface at a second depth (immediately) below the top surface of the semiconductor substrate (244), wherein the first depth is greater than the second depth (top of 1st portion deeper than top of 2nd portion) and the trench shield contact (222) fig. 2E [0038] (shown in 2e-2e cross-sectional view of fig. 2) [0038] touches the trench shield (212) fig. 2E [0033] along the second portion of the trench shield (212) (see modified fig. 2E of Yedinak below).
[AltContent: rect][AltContent: textbox (2nd portion)][AltContent: textbox (Top-level of substrate 244)][AltContent: arrow][AltContent: arrow][AltContent: textbox (1st portion)][AltContent: rect][AltContent: connector]
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Modified fig. 2E of Yedinak designating first and second portions
Regarding claim 9, Yedinak teaches the integrated circuit (200) fig. 2 [0030] of claim 1. Yedinak also teaches wherein the gate contact (236) fig. 2A [0032] and the trench shield contact (222) fig. 2E [0038] (shown in 2e-2e cross-sectional view of fig. 2) [0038] have a same depth (pass through a same depth) below a surface of a pre-metal dielectric (PMD) layer (246) fig. 2A [0035] over the semiconductor substrate (comprising 244) fig. 2A [0035].
Regarding claim 10, Yedinak teaches a semiconductor device (200) fig. 2 [0030], comprising:
a trench (232) fig. 2A [0031] located in a semiconductor layer (comprising 244) fig. 2A [0035];
a polysilicon gate electrode (233) fig. 2A [0032-0033] within the trench (212) fig. 2A [0033] and having a first (upper) portion in contact with a pre-metal dielectric (PMD) layer (246) fig. 2A [0035];
a polysilicon shield (212) fig. 2A [0033] within the trench (212) and having a first portion in contact with the PMD layer (246) and a second portion spaced apart from the PMD layer (246) by the gate electrode (233);
a gate contact (236) fig. 2A [0032] extending from a top surface of the PMD layer (246) to the gate electrode (233);
a source region (comprising left 228 with bordering region of 244) fig. 2A [0034] and a body region (bordering region of 244 of MOSFET) [0034] adjacent to the trench (232);
a source contact (227) fig. 2B [0036]; and
a trench shield contact (222) fig. 2E [0038] (shown in 2e-2e cross-sectional view of fig. 2) [0038] extending from the top surface of the PMD layer (246) to the first portion of the polysilicon shield (see fig. 2E perspective).
However, Yedinak does not explicitly disclose a source contact (227) extending through the source region (comprising 228) fig. 2B [0036] into the body region (bordering region of 244 of MOSFET) [0034].
Su teaches an integrated circuit (10) fig. 1A [0038] comprising a source contact (186) [0038] extending through the source region (182) [0038] into the body region (170) [0038].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit of Yedinak such that the source contact is made to extend into the source and body regions rearranged according to Su [0038] in order to optimize chip area component performance [0006-0008] and improve the s/d contact-connection(s) [0038], as taught by Su.
Regarding claim 11, Yedinak teaches the semiconductor device (200) fig. 2 [0030] of claim 10. Yedinak also teaches wherein a top surface of the gate contact (236) fig. 2A [0032] is coplanar with a top surface of the shield contact (222) fig. 2E [0038] (shown in 2e-2e cross-sectional view of fig. 2) [0038].
Regarding claim 12, Yedinak teaches the semiconductor device (200) fig. 2 [0030] of claim 10. Yedinak also teaches wherein the gate contact (236) fig. 2A [0032] is electrically connected to a first metal layer (202) fig. 2A [0031-0032] over the PMD layer (246) fig. 2A [0035], and the shield contact (222) fig. 2E [0038] (shown in 2e-2e cross-sectional view of fig. 2) [0038] is electrically connected to a different second metal layer (204) fig. 2A [0031-0032] over the PMD layer (246), the first metal layer (202) being coplanar with the second metal layer (204) (see fig. 2A).
Regarding claim 13, Yedinak teaches the semiconductor device (200) fig. 2 [0030] of claim 10. Yedinak also teaches further comprising a source contact (227) fig. 2B [0036] extending from the top surface of the PMD layer (246) fig. 2B [0035] to the semiconductor layer (comprising 244) fig. 2B [0035] adjacent the trench (232) fig. 2A [0031], wherein a top surface of the source contact (227) is coplanar with top surfaces of the gate contact (236) fig. 2A [0032] and the shield contact (222) fig. 2E [0038] (all coplanar with top of 246 interfacing 204).
Regarding claim 20, Yedinak teaches the integrated circuit (200) fig. 2 [0030] of claim 10. Yedinak also teaches wherein the source contact (227) fig. 2B [0036] and the gate contact (236) fig. 2A [0032] extend a same depth (pass through a same depth) below the top surface of the PMD layer (246) fig. 2A [0035].
Regarding claim 21, Yedinak teaches the integrated circuit (200) fig. 2 [0030] of claim 10. Yedinak also teaches wherein the source region (comprising left 228 with bordering region of 244) fig. 2A [0034] is n-type (n-well for P-channel mostfet [0019]) and the body region (bordering region of 244 of MOSFET) [0034] is p-type (when optionally p-channel mosfet [0019, 0034]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13 and 20-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature trench shield transistors.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 11/20/2025
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892