DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CONTINUED EXAMINATION UNDER 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/29/2026 has been entered.
RESPONSE TO ARGUMENTS
Applicant's arguments filed 5/29/2026 have been fully considered but they are not persuasive.
In response to applicant’s arguments with regard to the independent claims 1, 10 and 16 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed features because Elliott’s shared local memory is not the same as register-file space and is not addressable as instruction operands; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, and to further clarify, the examiner is not relying on Lueh, not on Elliott, for the teaching/suggesting of register-file space and being addressable as instruction operands (Fig. 15; [0196]-[0198]; [0216]-[0217]; and [0240]).
I. REJECTIONS BASED ON 35 USC 112
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites the limitation "… the individual register spaces …" in lines 9-10. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "… the individual register spaces …" in lines 8-9. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation "… the individual register spaces …" in lines 8-9. There is insufficient antecedent basis for this limitation in the claim.
II. REJECTIONS BASED ON 35 USC 101
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 10 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because applicant has provided evidence that applicant intends the term "computer-readable medium” to include non-statutory matter. The applicant describes a computer-readable medium as including open ended language and thus it is reasonable to interpret it to include all possible mediums, including non-statutory mediums (see paragraph [0445]).
The examiner suggests amending the claim to recite “… non-transitory computer-readable medium …” for independent claim 10, and its dependent claims, to overcome the 101 rejection.
III. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Valerio et al. (US Pub.: 2019/0324757) in view of Elliott et al. (US Pub.: 2017/0003972) and Lueh et al. (US Pub.: 2020/0394041).
As per claim 1, Valerio teaches/suggests an apparatus comprising: processing circuit (e.g. Fig. 3, ref. 300) comprising processing resources (e.g. associated with execution units (EUs 1510A-1510n) in Fig. 15), the processing circuit comprising: allocate a first thread team to a first processing resource of the processing resources, the first thread team including hardware threads that are to be executed solely by the first processing resource (e.g. associated with dispatching and receiving of hardware threads by respective EU for concurrent processing: [0053]; [0146]-[0147]; [0162]-[0163]-[0163]; [0189]); and having a register space (e.g. associated with Fig. 14, ref. 1410A-1410N), the register space being operation with threads (e.g. associated with treads from thread dispatcher 1408A-1408N in Fig. 14) (Fig. 3; Fig. 14-15; Fig. 20; [0048]; [0053]; [0137]-[0138]; [0145]-[0147]; [0149]-[0153]; [0162]-[0167]; and [0189]).
Valerio do not teach the apparatus comprising:
establish a shared local register (SLR) space for the first processing resource, the SLR space being accessible to the threads of the thread team and being inaccessible to threads that are outside of the thread team, wherein the SLR space and the individual register spaces are portions of a general register file for the first processing resource, wherein the SLR space is directly addressable as instruction operands; and
establish individual register spaces for the thread team, wherein the individual registers spaces are accessible to a respective thread of the thread team, wherein the individual registers spaces are established at top of the individual register spaces .
Elliott teaches/suggests an apparatus comprising: establish a shared local space (e.g. by combining the shared local memory area (104) in Fig. 5) for the first processing resource (e.g. associated with execution unit (EU)), the shared local space being accessible to the threads of the thread team and being inaccessible to threads that are outside of the thread team (e.g. as each EU (102) has its corresponding shared local space for operating with the group of threads), wherein the shared local space is portion of the first processing resource (e.g. associated with the combined shared local memory area (104) being portion of EU in Fig. 5); and establish individual register spaces (e.g. associated with set of register (103) in Fig. 5) for the thread team, wherein the individual registers spaces are accessible to a respective thread of the thread team (e.g. associated with each register of the set of registers is used for one thread: [0148]), wherein the individual registers spaces are established at top of the individual register spaces (e.g. it would have been an obvious design choice to one of ordinary skilled in the art to implement/orient the claimed features) (Fig. 5-8b; and [0144]-[0160]).
Lueh teaches/suggests an apparatus comprising: establish a shared local register (SLR) space, the SLR space operating accordingly (e.g. associated with shared registers (1514) in Fig. 15), wherein the SLR space and the individual register spaces are portions of a general register file (e.g. associated with general register file (GRF) being divided into shared/dynamic registers and static/dedicated registers: [0196]-[0197]), wherein the SLR space is directly addressable as instruction operands (e.g. associated with operand register(s) being returned: [0216]-[0217]) (Fig. 15; [0196]-[0198]; [0216]-[0217]; and [0240]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Elliott’s register operations and Lueh’s shared registers into Valerio’s apparatus for the benefit of reducing power consumption (Elliott, [0044]) and preventing register spilling (Lueh, [0196]) to obtain the invention as specified in claim 1.
As per claim 2, Valerio, Elliott and Lueh teach/suggest all the claimed features of claim 1 above, where Valerio, Elliott and Lueh further teach/suggest the apparatus comprising wherein the SLR space and the individual register spaces are portions of a general register file for the processing resource (Valerio, Fig. 3; Fig. 14-15; Fig. 20; [0048]; [0053]; [0081]; [0137]-[0138]; [0145]-[0147]; [0149]-[0153]; [0162]-[0167]; [0189]; Elliott, Fig. 5-8b; [0144]-[0160]; and Lueh, Fig. 15; [0196]-[0198]; [0216]-[0217]; [0240]).
As per claim 3, Valerio, Elliott and Lueh teach/suggest all the claimed features of claim 1 above, where Valerio, Elliott and Lueh further teach/suggest the apparatus comprising wherein the graphics processor is further to set a size of the SLR space (Valerio, Fig. 3; Fig. 14-15; Fig. 20; [0048]; [0053]; [0081]; [0137]-[0138]; [0145]-[0147]; [0149]-[0153]; [0162]-[0167]; [0189]; Elliott, Fig. 5-8b; [0144]-[0160]; and Lueh, Fig. 15; [0196]-[0198]; [0216]-[0217]; [0240]).
As per claim 4, Valerio, Elliott and Lueh teach/suggest all the claimed features of claim 3 above, where Valerio, Elliott and Lueh further teach/suggest the apparatus comprising wherein the set size is one of a plurality of authorized sizes for the SLR space (Valerio, Fig. 3; Fig. 14-15; Fig. 20; [0048]; [0053]; [0081]; [0137]-[0138]; [0145]-[0147]; [0149]-[0153]; [0162]-[0167]; [0189]; Elliott, Fig. 5-8b; [0144]-[0160]; and Lueh, Fig. 15; [0196]-[0198]; [0216]-[0217]; [0240]).
As per claim 5, Valerio, Elliott and Lueh teach/suggest all the claimed features of claim 1 above, where Valerio, Elliott and Lueh further teach/suggest the apparatus comprising wherein the first thread team is a sub-portion of a thread group, the thread group including a plurality of hardware threads to be executed by a plurality of processing resources (Valerio, Fig. 3; Fig. 14-15; Fig. 20; [0048]; [0053]; [0081]; [0137]-[0138]; [0145]-[0147]; [0149]-[0153]; [0162]-[0167]; [0189]; Elliott, Fig. 5-8b; [0144]-[0160]; and Lueh, Fig. 15; [0196]-[0198]; [0216]-[0217]; [0240]).
As per claim 6, Valerio, Elliott and Lueh teach/suggest all the claimed features of claim 1 above, where Valerio, Elliott and Lueh further teach/suggest the apparatus comprising wherein an SLR mode is enabled in response to a first mode value and is disabled in response to a second mode value (Valerio, Fig. 3; Fig. 14-15; Fig. 20; [0048]; [0053]; [0081]; [0137]-[0138]; [0145]-[0147]; [0149]-[0153]; [0162]-[0167]; [0189]; Elliott, Fig. 5-8b; [0144]-[0160]; and Lueh, Fig. 15; [0196]-[0198]; [0216]-[0217]; [0240]).
As per claim 9, Valerio, Elliott and Lueh teach/suggest all the claimed features of claim 1 above, where Valerio, Elliott and Lueh further teach/suggest the apparatus comprising wherein the processing circuit is coupled to a memory, the processing circuitry comprises graphic processing circuitry (Valerio, Fig. 3; Fig. 14-15; Fig. 20; [0048]; [0053]; [0081]; [0137]-[0138]; [0145]-[0147]; [0149]-[0153]; [0162]-[0167]; [0189]; Elliott, Fig. 5-8b; [0144]-[0160]; and Lueh, Fig. 15; [0196]-[0198]; [0216]-[0217]; [0240]).
As per claim 10, claim 10 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1.
As per claims 11-14, claims 11-14 are rejected in accordance to the same rational and reasoning as the above rejection of claims 2-6.
As per claim 16, claim 16 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1, where Valerio, Elliott and Lueh further teach/suggest the method comprising allocating operations; and allocation operations (Valerio, Fig. 3; Fig. 14-15; Fig. 20; [0048]; [0053]; [0081]; [0137]-[0138]; [0145]-[0147]; [0149]-[0153]; [0162]-[0167]; [0189]; Elliott, Fig. 5-8b; [0144]-[0160]; and Lueh, Fig. 15; [0196]-[0198]; [0216]-[0217]; [0240]).
As per claims 17-20, claims 17-20 are rejected in accordance to the same rational and reasoning as the above rejection of claims 2-6.
Claims 7-8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Valerio et al. (US Pub.: 2019/0324757) in view of Elliott et al. (US Pub.: 2017/0003972) and Lueh et al. (US Pub.: 2020/0394041) as applied to claims 1 and 10 above, and further in view of Kang et al. (US Pub.: 2013/0297919).
As per claim 7, Valerio, Elliott and Lueh teach/suggest all the claimed features of claim 1 above, where Valerio, Elliott and Lueh further teach/suggest the apparatus comprising wherein the threads of the thread team are threads that operates on the first processing resource (Valerio, Fig. 3; Fig. 14-15; Fig. 20; [0048]; [0053]; [0081]; [0137]-[0138]; [0145]-[0147]; [0149]-[0153]; [0162]-[0167]; [0189]; Elliott, Fig. 5-8b; [0144]-[0160]; and Lueh, Fig. 15; [0196]-[0198]; [0216]-[0217]; [0240]), but Valerio, Elliott and Lueh do not expressly teach the apparatus comprising threads that wholly time-slice.
Kang teach/suggest the apparatus comprising threads that wholly time-slice ([0029]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kang’s time-slices threads into Valerio, Elliott and Lueh’s apparatus for the benefit of increasing overall execution throughput (Kang, [0029]) to obtain the invention as specified in claim 7.
As per claim 8, Valerio, Elliott, Lueh and Kang teach/suggest all the claimed features of claim 7 above, where Valerio, Elliott, Lueh and Kang further teach/suggest the apparatus comprising wherein the threads of the thread team logically operate as a single virtual thread running on the first processing resource (e.g. equating to the group of threads that are running on the corresponding EU) (Valerio, Fig. 3; Fig. 14-15; Fig. 20; [0048]; [0053]; [0081]; [0137]-[0138]; [0145]-[0147]; [0149]-[0153]; [0162]-[0167]; [0189]; Elliott, Fig. 5-8b; [0144]-[0160]; Lueh, Fig. 15; [0196]-[0198]; [0216]-[0217]; [0240]; and Kang, [0029]).
As per claim 15, claim 15 is rejected in accordance to the same rational and reasoning as the above rejection of claim 7.
IV. PERTINENT RELATED PRIOR ART
Vaidyanathan et al. (US Pub.: 2019/0087188): discloses a set of dedicated registers per thread and shared registers that are temporarily assigned to a thread on demand, wherein shared registers are dynamically assigned to a smaller number of threads whenever program execution enters a hotspot, and are released upon hotspot exit.
V. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 June 27, 2026
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