DETAILED ACTION
This office action is in response to applicant's amendment and remarks filed on 06/08/2026.
Claims 1-20 are pending in the application. Claims 1-17 are under examination; claims 18-20 remain withdrawn from consideration as being directed to a non-elected species. Claim 1 has been amended; claim 18 has been amended. No claims have been added or canceled.
Claim 1 has been amended to recite "wherein the first transistor and the second transistor are on a same semiconductor fin." This amendment has necessitated the new ground of rejection set forth below; accordingly, THIS ACTION IS MADE FINAL. See MPEP 706.07(a).
Response to Amendment
Applicant's amendment to independent claim 1 is acknowledged. The amendment does not introduce new matter. The amended limitation of claim 1 is addressed by the rejections below in view of newly cited US 2019/0131305 A1 (Widjaja).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0135143 A1 (Jeon) in view of US 2018/0012642 A1 (Rodriguez), and further in view of US 2019/0131305 A1 (Widjaja).
Regarding claim 1, Jeon discloses, a memory device (as annotated on Fig. 12; [0086] – [0090]), comprising:
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a first transistor (N101; access transistor; Fig. 12; [0088]), wherein the first transistor (N101) is an access transistor to write data (functionality of N101);
a ferroelectric capacitor (N101; ferroelectric capacitor; Fig. 12; [0088]) for storing data (functionality of C101); and
a second transistor (part of sense amplifier, as annotated on Fig. 12; [0089]), wherein the second transistor (part of sense amplifier) is a sense transistor to read the data stored on the ferroelectric capacitor (C101) (Fig. 12; [0089]).
But Jeon fails to teach explicitly, a transistor level design of a sense amplifier;
However, in analogous art, Rodriguez discloses, a transistor level design of a sense amplifier (Fig. 7A; [0031]);
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon and Rodriguez before him/her, to modify the teachings of a memory device using a sense amplifier as taught by Jeon and to include the teachings of a transistor level design of a sense amplifier as taught by Rodriguez since a sense amplifier is an important building block in memory design and absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Rodriguez while forming a memory device of Jeon.
The combination of Jeon and Rodriguez fails to teach explicitly, wherein the first transistor and the second transistor are on a same semiconductor fin.
However, in analogous art, Widjaja discloses, a memory device (memory cell 102/104; three-dimensional fin-type memory cell embodiment; Figs. 26-27; [0172] – [0174]) wherein the first transistor (floating body transistor 40) and the second transistor (access transistor 42) are on a same semiconductor fin (fin structure 52) (Figs. 26-27; Widjaja teaches that memory cells 102 and 104 have a fin structure 52 extending substantially perpendicular to and above the top surface of the substrate, and that both memory cells comprise floating body transistor 40 and access transistor 42 formed on the fin structure 52, the two transistors being connected in series).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon, Rodriguez and Widjaja before him/her, to modify the teachings of a memory device having a first transistor and a second transistor as taught by Jeon and Rodriguez and to include the teachings of the first transistor and the second transistor being on a same semiconductor fin as taught by Widjaja, since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious, and since forming both transistors of the memory cell on a common semiconductor fin is a known layout technique that reduces the memory cell footprint and increases integration density. Absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Widjaja while forming a memory device of Jeon.
Regarding claim 7, the combination of Jeon, Rodriguez and Widjaja discloses, the memory device of claim 1, wherein the ferroelectric capacitor (612 and 616) is coupled to a plate line (PL) (Fig. 6B; [0030]; Rodriguez Ref.).
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Regarding claim 8, Jeon discloses, the memory device of claim 1, wherein a gate of the first transistor (N101) is coupled to a write word line (WLi), and wherein a drain (Va) of the first transistor (N101) is coupled to a write bit line (BLi, through capacitor C101) (Fig. 12; [0086] – [0090]).
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Claims 2-3 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon, Rodriguez and Widjaja as applied to claim 1 and further in view of US 2023/0067884 A1 (Muller).
Regarding claim 2, the combination of Jeon, Rodriguez and Widjaja fails to teach explicitly, the memory device of claim 1, wherein the first transistor, the second transistor, and the ferroelectric capacitor are coupled together by a node.
However, in analogous art, Muller discloses, the memory device of claim 1, wherein the first transistor (162), the second transistor (166), and the ferroelectric capacitor (102a) are coupled together by a node (as annotated on Fig. 3B) (Fig. 3B; [0016]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon, Rodriguez, Widjaja and Muller before him/her, to modify the teachings of a memory device using the first transistor, the second transistor, and the ferroelectric capacitor as taught by Jeon and to include the teachings of the first transistor, the second transistor, and the ferroelectric capacitor being coupled together by a node as taught by Muller since this is how the memory device components are usually connected and absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Muller while forming a memory device of Jeon.
Regarding claim 3, the combination of Jeon, Rodriguez, Widjaja and Muller teaches, the memory device of claim 2, wherein the node (as annotated on Fig. 3B) is coupled to a terminal of the ferroelectric capacitor (102a), a drain of the first transistor (162) and a gate of the second transistor (166) (Fig. 3B; [0016]; Muller Ref.).
Regarding claim 10, the combination of Jeon, Rodriguez and Widjaja fails to teach explicitly, the memory device of claim 1, wherein the ferroelectric capacitor is stacked above the first transistor and the second transistor.
However, in analogous art, Muller discloses, the memory device of claim 1, wherein the ferroelectric capacitor is stacked above the first transistor and the second transistor (Fig. 8; [0016]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon, Rodriguez, Widjaja and Muller before him/her, to modify the teachings of a memory device using the first transistor, the second transistor, and the ferroelectric capacitor as taught by Jeon and to include the teachings of the ferroelectric capacitor being stacked above the first transistor and the second transistor as taught by Muller since this is how the memory device components are usually connected and absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Muller while forming a memory device of Jeon.
Regarding claim 11, the combination of Jeon, Rodriguez, Widjaja and Muller discloses, the memory device of claim 10, wherein the ferroelectric capacitor is directly over the first transistor (Fig. 8; [0016]; Muller Ref; with broadest reasonable interpretation).
Regarding claim 12, the combination of Jeon, Rodriguez and Widjaja fails to teach explicitly, the memory device of claim 1, wherein the first transistor is laterally adjacent to the second transistor.
However, in analogous art, Muller discloses, the memory device of claim 1, wherein the first transistor is laterally adjacent to the second transistor (Fig. 8; [0016]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon, Rodriguez, Widjaja and Muller before him/her, to modify the teachings of a memory device using the first transistor, the second transistor, and the ferroelectric capacitor as taught by Jeon and to include the teachings of first transistor being laterally adjacent to the second transistor as taught by Muller since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Muller while forming a memory device of Jeon.
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon, Rodriguez and Widjaja as applied to claim 1 and further in view of US 2020/0091162 A1 (Morris).
Regarding claim 4, the combination of Jeon, Rodriguez and Widjaja fails to teach explicitly, the memory device of claim 1, wherein the ferroelectric capacitor comprises hafnium, zirconium, and oxygen, or perovskite materials, or aluminum, scandium, and nitrogen.
However, in analogous art, Morris discloses, the memory device of claim 1, wherein the ferroelectric capacitor comprises hafnium, zirconium, and oxygen, or perovskite materials, or aluminum, scandium, and nitrogen ([0025]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon, Rodriguez, Widjaja and Morris before him/her, to modify the teachings of a memory device using a ferroelectric capacitor as taught by Jeon and to include the teachings of ferroelectric capacitor comprising hafnium zirconium oxide as taught by Morris since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Morris while forming a memory device of Jeon.
Regarding claim 13, Jeon discloses that a formation procedure of transistor can be a shape of fin ([0130]), but the combination of Jeon, Rodriguez and Widjaja fails to teach explicitly, the memory device of claim 1, wherein the first transistor and the second transistor are planar, fin-based transistors, nanowire-based transistors, nanoribbon-based transistors, or nanosheet-based transistors.
However, in analogous art, Morris discloses, the memory device of claim 1, wherein the first transistor (110; access transistor) and the second transistor are planar, fin-based transistors, nanowire-based transistors, nanoribbon-based transistors, or nanosheet-based transistors (Fig. 2; [0045]; if one transistor is a FinFET, then other transistors in the device must be FinFET).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon, Rodriguez, Widjaja and Morris before him/her, to modify the teachings of a memory device using transistors as taught by Jeon and to include the teachings of transistors being FinFET as taught by Morris since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Morris while forming a memory device of Jeon.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon, Rodriguez and Widjaja as applied to claim 1 and further in view of US 2009/0057677 A1 (Isogai).
Regarding claim 5, the combination of Jeon, Rodriguez and Widjaja fails to teach explicitly, the memory device of claim 1, wherein the ferroelectric capacitor is a planar capacitor.
However, in analogous art, Isogai discloses, the memory device of claim 1, wherein the ferroelectric capacitor is a planar capacitor ([0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon, Rodriguez, Widjaja and Isogai before him/her, to modify the teachings of a memory device using a ferroelectric capacitor as taught by Jeon and to include the teachings of ferroelectric capacitor being a planar capacitor as taught by Isogai since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Isogai while forming a memory device of Jeon.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon, Rodriguez and Widjaja as applied to claim 1 and further in view of US 2021/0399135 A1 (Polakowski).
Regarding claim 6, the combination of Jeon, Rodriguez and Widjaja fails to teach explicitly, the memory device of claim 1, wherein the ferroelectric capacitor is a trench capacitor.
However, in analogous art, Polakowski discloses, the memory device of claim 1, wherein the ferroelectric capacitor (14’ and 14’a) is a trench capacitor (Fig. 11; [0058]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon, Rodriguez, Widjaja and Polakowski before him/her, to modify the teachings of a memory device using a ferroelectric capacitor as taught by Jeon and to include the teachings of ferroelectric capacitor being a trench capacitor as taught by Polakowski since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Polakowski while forming a memory device of Jeon.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon, Rodriguez and Widjaja as applied to claim 1 and further in view of US 2020/0066326 A1 (Rios).
Regarding claim 9, the combination of Jeon, Rodriguez and Widjaja fails to teach explicitly, the memory device of claim 1, wherein a source of the second transistor is coupled to a read word line, and wherein a drain of the second transistor is coupled to a read bit line.
However, in analogous art, Rios discloses, the memory device of claim 1, wherein a source of the second transistor (T2) is coupled to a read word line (RWL), and wherein a drain of the second transistor (T2) is coupled to a read bit line (RBL) (Fig. 1; [0024]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon, Rodriguez, Widjaja and Rios before him/her, to modify the teachings of a memory device using a second transistor as taught by Jeon and to include the teachings of a source of the second transistor being coupled to a read word line, and a drain of the second transistor being coupled to a read bit line as taught by Rios since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Rios while forming a memory device of Jeon.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0135143 A1 (Jeon) and further in view of US 2023/0067884 A1 (Muller).
Regarding claim 14, Jeon discloses, a memory device (as annotated on Fig. 12; [0086] – [0090]), comprising:
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a first transistor (N101; access transistor; Fig. 12; [0088]);
a semiconductor fin ([0130]; Jeon teaches that a formation procedure of transistor can be a shape of fin);
a ferroelectric capacitor (N101; ferroelectric capacitor; Fig. 12; [0088]); and
a second transistor (part of sense amplifier, as annotated on Fig. 12; [0089]);
But Jeon fails to teach explicitly, the first transistor formed on the semiconductor fin; the second transistor formed on the semiconductor fin adjacent to the first transistor; the ferroelectric capacitor over the first transistor; and a node to electrically couple the first transistor, the second transistor, and the ferroelectric capacitor together.
However, in analogous art, Muller discloses, the first transistor (162; first transistor; Fig. 8; [0016]) formed on the semiconductor fin (112a/118a, as annotated on Fig. 8; active regions; Fig. 8; [0016]);
the second transistor (166; second transistor; Fig. 8; [0016]) formed on the semiconductor fin (112a/118a; active region; Fig. 8; [0017]) adjacent to the first transistor (162);
Note: The examiner considers 112a/118b as a combined active region which is equivalent to “semiconductor Fin” in the claim.
the ferroelectric capacitor (102a; ferroelectric capacitor; Fig. 8; [0016]) over the first transistor (162); and
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a node (as annotated on Fig. 3B) to electrically couple the first transistor (162), the second transistor (166), and the ferroelectric capacitor (102a) together (Fig. 3B; [0016]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon and Muller before him/her, to modify the teachings of a memory device using transistors and ferroelectric capacitor as taught by Jeon and to include the teachings of how the transistors and the ferroelectric capacitor are placed on the substrate as taught by Muller since the placement of these components is important for successful implementation of the device and absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Muller while forming a memory device of Jeon.
Regarding claim 15, the combination of Jeon and Muller teaches, the memory device of claim 14, wherein the node (as annotated on Fig. 3B) is coupled to a terminal of the ferroelectric capacitor (102a), a drain of the first transistor (162) and a gate of the second transistor (166) (Fig. 3B; [0016]; Muller Ref.).
Regarding claim 16, the combination of Jeon and Muller teaches, the memory device of claim 14, wherein the first transistor (162) is a write transistor, and wherein the second transistor (166) is a read transistor (Fig. 3B; [0016]; these are the widely used terminology used in the industry; Muller Ref.).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon and Muller as applied to claim 14 and further in view of US 2020/0091162 A1 (Morris).
Regarding claim 17, the combination of Jeon and Muller fails to teach explicitly, the memory device of claim 14, wherein the ferroelectric capacitor comprises hafnium, zirconium, and oxygen, or perovskite materials, or aluminum, scandium, and nitrogen.
However, in analogous art, Morris discloses, the memory device of claim 14, wherein the ferroelectric capacitor comprises hafnium, zirconium, and oxygen, or perovskite materials, or aluminum, scandium, and nitrogen ([0025]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jeon, Muller and Morris before him/her, to modify the teachings of a memory device using a ferroelectric capacitor as taught by Jeon and to include the teachings of ferroelectric capacitor comprising hafnium zirconium oxide as taught by Morris since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Jeon, a person with ordinary skill in the art would be motivated to reach out to Morris while forming a memory device of Jeon.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2020/0373312 A1 (Sharma) - An integrated circuit is disclosed including a backend thin-film transistor (TFT) a ferroelectric capacitor electrically connected to the backend TFT. The backend TFT has a gate electrode, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, and a gate dielectric between the gate electrode and semiconductor region. The ferroelectric capacitor has a first terminal electrically connected to one of the source and drain regions, a second terminal, and a ferroelectric dielectric between the first and second terminals. In an embodiment, a memory cell includes this integrated circuit, the gate electrode being electrically connected to a wordline, the source region being electrically coupled to a bitline, and the drain region being the one of the source and drain regions. In an embodiment, an embedded memory includes wordlines, bitlines, and a plurality of such memory cells at crossing regions of the wordlines and bitlines.
US 2020/0235110 A1 (Morris) - An apparatus is disclosed comprising a word line; a source line; a bit-line; and a memory bit-cell coupled to the source line, the bit-line, and the word line, wherein the memory bit-cell comprises a capacitor including ferroelectric material and a transistor fabricated on a backend of a die.
US 2011/0188287 A1 (Kim) - High speed FRAM is disclosed including a deselect circuit for replacing SRAM, wherein the deselect circuit is connected to a local bit line pair for forcing a middle voltage to storage nodes of ferroelectric capacitors of unselected memory cell while a plate line of the ferroelectric capacitors is forced to the middle voltage, so that the unselected memory cell is not polarized while selected memory cell is polarized by changing the local bit line pair when writing. With the deselect circuit, half of the memory cells are not accessed, which reduces number of sense amps. Furthermore, half of metal routing lines on the memory cells can be used for selecting columns and connecting global power as the convention SRAM configuration, while other half of metal routing lines are used for global bit lines.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
07/25/2026
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