Prosecution Insights
Last updated: April 20, 2026
Application No. 17/958,281

DESIGN OF VOLTAGE CONTRAST PROCESS MONITOR

Non-Final OA §103
Filed
Sep 30, 2022
Examiner
LOPEZ, JORGE ANDRES
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
4y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
14 granted / 14 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
4y 4m
Avg Prosecution
28 currently pending
Career history
42
Total Applications
across all art units

Statute-Specific Performance

§103
70.3%
+30.3% vs TC avg
§102
19.8%
-20.2% vs TC avg
§112
9.9%
-30.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 14 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election without traverse of “Group I (Claims 1-22)” in the reply filed on December 17, 2025, is acknowledged. Claims 23-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-11 and 16-19 are rejected under 35 U.S.C. 103 as being obvious over US 2019/0384185 A1; Lo et al.; 12/2019; (“185”). Regarding Claim 1. 185 teaches in Fig. 7A (not a cross-sectional figure) about an apparatus, comprising: a substrate (“substrate”, [0018], Ln. 21); a plurality of devices (measurement devices each composed of items 701-703) on the substrate (“measurement tools installed in … a substrate”, [0018], Ln. 19-21), wherein each of the plurality of devices comprises a process monitor structure (items 701-702) with different offsets from a target value (overlay offsets (OVL) between items 701 and 702 have multiple values including -34, -16, 0, +16, and +34 where OVL=0 is the target value); a plurality of electrically conductive vias on the substrate (each via embodied by items 704 and 705), wherein each of the plurality of electrically conductive vias has a first end (lower-end of items 704 in contact with items 703) and a second end opposite the first end (upper-end of items 705 opposite to lower-end of items 704), and wherein each of the plurality of electrically conductive vias is electrically coupled at the first end (lower-end of items 704 are coupled to items 703), respectively, with each of the plurality of devices (respectively, each lower-end of via items 704 is connected to a measurement device item 701-703); wherein the second end of the each of the plurality of electrical vias is within a scan area on the substrate (each second end of via items is within a scan area located at the upper-end of items 705), and wherein the each of the plurality of electrically conductive vias are not directly electrically coupled with each other (via items are not in contact with each other along the XY-plane); and wherein the plurality of devices are electrically coupled with a ground (“if a pattern 702, along with the structures thereon, is connected to a pattern 701 as a result of alignment with the pattern 701, positive charges on the this pattern 702 can dissipate and it will appear brighter”, [0047], Ln. 4-7; therefore, items 701 are grounded for positive charges to be able to dissipate). 185 does not teach about an apparatus, comprising: a plurality of electrically conductive traces on the substrate, wherein each of the plurality of electrically conductive traces has a first end and a second end opposite the first end, and wherein each of the plurality of electrically conductive traces is electrically coupled at the first end, respectively, with each of the plurality of devices; wherein the second end of the each of the plurality of electrical traces is within a scan area on the substrate, and wherein the each of the plurality of electrically conductive traces are not directly electrically coupled with each other. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use traces rather than vias because this rearrangement only changes the direction an electrical conductor extends from a vertical direction to a horizonal direction, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. PNG media_image1.png 435 940 media_image1.png Greyscale Fig. 7A, annotated by Examiner, from Lo et al., US 2019/0384185 A1. Regarding Claim 2. 185 teaches in Claim 14 about an apparatus, wherein the offsets range from between plus 190nm to minus 190nm (offset range taught as the absolute value of a pitch smaller than 190nm). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Regarding Claim 3. 185 teaches in Fig. 7A about an apparatus, wherein the process monitor structures include one or more components of a transistor structure (items 701 and 702 could embody at least the necessary structural alignment of an emitter and a base or a base and a collector). Regarding Claim 4. 185 teaches in Fig. 7B about an apparatus, wherein the second ends of each of the plurality of electrical vias are arranged in a row (top-view showing second ends of vias arranged in a row). 185 does not teach about an apparatus, wherein the second ends of each of the plurality of electrical traces are arranged in a column. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use traces rather than vias because this rearrangement only changes the direction an electrical conductor extends from a vertical direction to a horizonal direction (same as changing a layout from columns to rows), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Regarding Claim 5. 185 teaches in Fig. 7A about an apparatus, wherein the second ends of each of the plurality of electrical vias are arranged in order of the offsets (second ends of electrical vias are arranged from left to right, and following the value order of the offsets from negative to positive). 185 does not teach about an apparatus, wherein the second ends of each of the plurality of electrical traces are arranged in order of the off sets. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use traces rather than vias because this rearrangement only changes the direction an electrical conductor extends from a vertical direction to a horizonal direction, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Regarding Claim 6. 185 teaches in Fig. 7A about an apparatus, wherein the plurality of electrically conductive traces is a first plurality of electrically conductive traces and wherein the plurality of devices is a first plurality of devices (applicant gives another name for the plurality of traces and for the plurality of devices; indeed, no new limitations are added by applicant presenting these new terminologies). 185 does not teach about an apparatus, wherein a second plurality of devices on the substrate, wherein each of the second plurality of devices comprises a second process monitor structure with different offsets from a second target value; and a second plurality of electrically conductive traces on the substrate, wherein each of the second plurality of electrically conductive traces has a first end and a second end opposite the first end, and wherein each of the second plurality of electrically conductive traces is electrically coupled at the first end, respectively, with each of the second plurality of devices; and wherein the second end of the each of the second plurality of electrical traces is within the scan area on the substrate, and wherein the each of the second plurality of electrically conductive traces are not directly electrically coupled with each other. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate (from Claim 1) the first plurality of devices, the first process monitor structures (also with different offsets from a target value), and the traces with first and second ends, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04. Regarding Claim 7. (same as rejection for Claim 4) Regarding Claim 8. 185 teaches in Fig. 7A about an apparatus, wherein there are second ends of the each of the first plurality of electrical vias (please see rejection of Claim 1 for using traces rather than vias, and please see rejection of Claim 6 regarding duplication of parts). 185 does not teach about an apparatus, wherein the second ends of the each of the second plurality of electric traces are adjacent to second ends of the each of the first plurality of electrical traces. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange the placing of a duplicated set of test structures and place it adjacent to a previously disclosed set of test structures, to combined all test structures within a single test area, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Regarding Claim 9. 185 teaches in Fig. 7A about an apparatus, wherein a first plurality of electrically conductive vias has a number of electrically conductive vias (please see rejection of Claim 1 for using traces rather than vias, and please see rejection of Claim 6 regarding duplication of parts). 185 does not teach about an apparatus, wherein the second plurality of electrically conductive traces has the same number of electrically conductive traces as the first plurality of electrically conductive traces. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use traces rather than vias because this rearrangement only changes the direction an electrical conductor extends from a vertical direction to a horizonal direction (please see rejection of Claim 1), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. It would have been also obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the same number of vias in the (duplicated) second plurality of electrically conductive vias as in the (original) first plurality of electrically conductive vias, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04. Regarding Claim 10. 185 teaches in Fig. 7A about an apparatus, wherein each of the plurality of devices comprises a process monitor structure with different offsets from a target value. 185 does not teach about an apparatus, wherein the second target value is different than the target value. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary the target value of a (duplicated) second target value from a (original) first target value to achieve a better understanding of the fabrication process limitations and performance with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). Regarding Claim 11. 185 teaches in Fig. 7A about an apparatus, wherein wherein the electrically conductive vias comprise a material not disclosed. 185 does not teach about an apparatus, wherein wherein the electrically conductive traces comprise copper It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a metal such as copper due to the inherent conducting capabilities of the same for uses in applications such as traces or vias, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416. Regarding Claim 16. 185 teaches in Fig. 7B about an apparatus, wherein a brightness of the second end of one of the electrically conductive vias during an electronic beam scan identifies whether the device corresponding with the one of the plurality of electrically conductive vias has a short defect or an open defect (OVL values -16, 0, and 16 have a short defect and therefore their corresponding second ends are brighter, compared to OVL values -34 and 34 where there is an open defect and therefore their corresponding second ends are darker). 185 does not teach about an apparatus, wherein a brightness of the second end of one of the electrically conductive traces during an electronic beam scan identifies whether the device corresponding with the one of the plurality of electrically conductive traces has a short defect or an open defect. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use traces rather than vias because this rearrangement only changes the direction an electrical conductor extends from a vertical direction to a horizonal direction, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Regarding Claim 17. 185 teaches in Fig. 7A about an apparatus, comprising: a substrate; a device (device corresponding to OVL=0) on the substrate, wherein the device comprises a process monitor structure (process monitor structure corresponding to OVL=0) with an offset from a target value (offset OVL=0), wherein the device has a first terminal and a second terminal (first and second terminals of device corresponding to OVL=0), and wherein the second terminal is coupled to a ground; and an electrically conductive via with a first end and a second end opposite from the first end, wherein the first end of the electrically conductive via is directly coupled to the first terminal of the device, and wherein the second end of the electrically conductive via terminates without contacting another electrically conductive structure. 185 does not teach about an apparatus, wherein an electrically conductive trace with a first end and a second end opposite from the first end, wherein the first end of the electrically conductive trace is directly coupled to the first terminal of the device, and wherein the second end of the electrically conductive trace terminates without contacting another electrically conductive structure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use traces rather than vias because this rearrangement only changes the direction an electrical conductor extends from a vertical direction to a horizonal direction, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Regarding Claim 18. (same as rejection for Claim 3). Regarding Claim 19. (same as rejection for Claim 16). Allowable Subject Matter Claim 12 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 21 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 22 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/ Supervisory Patent Examiner, Art Unit 2897 /JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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Prosecution Timeline

Sep 30, 2022
Application Filed
Jun 01, 2023
Response after Non-Final Action
Jan 13, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 2 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
4y 4m
Median Time to Grant
Low
PTA Risk
Based on 14 resolved cases by this examiner. Grant probability derived from career allow rate.

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