DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 02/27/2026, has been entered. The Applicant has amended claims 1, 13, 20, and 22, and canceled claim 17. Accordingly, claims 1-16 and 18-25 remain pending in the application.
Applicant’s amendments to the claims 13 and 20 and the title have overcome each and every objection previously set forth in the Non-Final Office Action mailed on 12/8/ 2025.
Applicant' s amendment to claim 22 has also overcome the 25. U.S.C. 112(b) rejection made on claim 22 in the Non-Final Office Action mailed on 12/8/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, claim 6 recites limitations regarding “the first top surface of the first metal gate” on line 2, and “the second top surface of the second metal gate” on lines 2-3. There is insufficient antecedent basis for “the top surface of the first metal gate” and “the top surface of the second metal gate” in claim 6 and in claim 1 on which claim 6 depends (after amendments, claim 1 does not define the first and second top surfaces). For examining purpose, “the first top surface of the first metal gate” is considered to be “the uppermost surface of the first metal gate” and “the second top surface of the second metal gate” is considered to be “the uppermost surface of the second metal gate”.
Regarding claim 7, claim 7 recites limitations regarding “the first top surface of the first metal gate” on line 1, and “the second top surface of the second metal gate” on line 2. There is insufficient antecedent basis for “the top surface of the first metal gate” and “the top surface of the second metal gate” in claim 7 and in claim 1 on which claim 7 depends (after amendments, claim 1 does not define the first and second top surfaces). For examining purpose, “the first top surface of the first metal gate” is considered to be “the uppermost surface of the first metal gate” and “the second top surface of the second metal gate” is considered to be “the uppermost surface of the second metal gate”.
Regarding claim 8, claim 8 recites limitations regarding “the first top surface of the first metal gate” on lines 2-3, and “the second top surface of the second metal gate” on line 3. There is insufficient antecedent basis for “the top surface of the first metal gate” and “the top surface of the second metal gate” in claim 8 and in claim 1 on which claim 8 depends (after amendments, claim 1 does not define the first and second top surfaces). For examining purpose, “the first top surface of the first metal gate” is considered to be “the uppermost surface of the first metal gate” and “the second top surface of the second metal gate” is considered to be “the uppermost surface of the second metal gate”.
Regarding claim 11, claim 11 recites limitations regarding “the first top surface of the first metal gate” on lines 1-2. There is insufficient antecedent basis for “the top surface of the first metal gate in claim 11 and in claim 1 on which claim 11 depends (after amendments, claim 1 does not define the first top surface). For examining purpose, “the first top surface of the first metal gate” is considered to be “the uppermost surface of the first metal gate”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 9-11, and 22-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 2022/0173097 A1).
Regarding claim 1, Yang teaches an integrated circuit structure (integrated circuit device 500A, Figs. 8 and 10, [0098]) comprising:
a first vertical stack of nanoribbons (nanosheet stacks NSS of transistor TR2, see first vertical stack in Illustrative Fig. 1, which includes annotated figures Fig. 8 and Fig. 10, [0033]: while Yang does not explicitly states that the nanosheet are nanoribbons, a person of ordinary skill in the art would understand that nanoribbons can replace nanosheet in such devices) above a gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1, [0022]-[0023]) that extends from a first gate spacer (outer insulating spacer 118 on the left as shown in Fig. 2A-B for transistors TR1 and TR2, [0049]; while not shown in Figs. 8 and 10, the location of the corresponding outer insulating spacer 118 are indicated as first gate spacer in Illustrative Fig. 1) to a second gate spacer (outer insulating spacer 118 on the right as shown in Fig. 2A-B for transistors TR1 and TR2, shown as second gate spacer in Illustrative Fig. 1);
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a second vertical stack of nanoribbons (nanosheet stacks NSS of transistor TR1, see second vertical stack in Illustrative Fig. 1, [0033]) above the gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1) that extends from the first gate spacer (outer insulating spacer 118 on the left as shown in Fig. 2A for transistor TR1, shown as first gate spacer in Illustrative Fig. 1) to the second gate spacer (second gate spacer, Illustrative Fig. 1);
a first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 1, [0036]) extending from the gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1) between the first vertical stack of nanoribbons (first vertical stack, Illustrative Fig. 1) and the second vertical stack of nanoribbons (second vertical stack, Illustrative Fig. 1);
a second wall (second gate cut insulating pattern 150B, Illustrative Fig. 1, [0036]) extending from the gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1) and a third wall extending (first gate cut insulating pattern 150A, Illustrative Fig. 1, [0036]) from the gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1), wherein the first vertical stack of nanoribbons (first vertical stack, Illustrative Fig. 1) is between the second wall (second gate cut insulating pattern 150B, Illustrative Fig. 1) and the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 1), and wherein the second vertical stack of nanoribbons (second vertical stack, Illustrative Fig. 1) is between the third wall (first gate cut insulating pattern 150A, Illustrative Fig. 1) and the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 1); and
a first gate metal (first work function metal film ML1, Illustrative Fig. 1, [0099]) surrounding the first vertical stack of nanoribbons (first vertical stack, Illustrative Fig. 1) and a second gate metal (second work function metal film ML2, Illustrative Fig. 1, [0098]) surrounding the second stack of nanoribbons (second vertical stack, Illustrative Fig. 1), wherein the first gate metal (first work function metal film ML1, Illustrative Fig. 1) has an uppermost surface (see first uppermost surface in Illustrative Fig. 1) at a same level as an uppermost surface of the second gate metal (see second uppermost surface in Illustrative Fig. 1, which is at the same level as the first uppermost surface).
Regarding claim 2, Yang teaches the integrated circuit structure of claim 1, wherein the first vertical stack of nanoribbons (first vertical stack, Illustrative Fig. 1 (see also nanosheet stacks NSS in Fig. 2B)) extend at least partially into the first gate spacer (first gate spacer, Illustrative Fig. 1, (see outer insulating spacer 118 on the left in Fig. 2B: when viewed from the top the first vertical stack extends into the first gate spacer)) and into the second gate spacer (second gate spacer, Illustrative Fig. 1 (see outer insulating spacer 118 on the right in Fig. 2B: when viewed from the top the first vertical stack extends into the second gate spacer)).
Regarding claim 3, Yang teaches the integrated circuit structure of claim 1, wherein the second vertical stack of nanoribbons (second vertical stack, Illustrative Fig. 1 (see also nanosheet stacks NSS in Fig. 2A)) extend at least partially into the first gate spacer (first gate spacer, Illustrative Fig. 1 (see outer insulating spacer 118 on the left in Fig. 2A: when viewed from the top the second vertical stack extends into the first gate spacer)) and into the second gate spacer (second gate spacer, Illustrative Fig. 1 (see outer insulating spacer 118 on the right in Fig. 2A: when viewed from the top the second vertical stack extends into the second gate spacer)).
Regarding claim 4, Yang teaches the integrated circuit structure of claim 1, wherein the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 1), the second wall (second gate cut insulating pattern 150B, Illustrative Fig. 1), and the third wall (first gate cut insulating pattern 150A, Illustrative Fig. 1) are substantially perpendicular to the first gate spacer (first gate spacer, Illustrative Fig. 1) or to the second gate spacer (second gate spacer, Illustrative Fig. 1).
Regarding claim 6, Yang teaches the integrated circuit structure of claim 1, wherein the first top surface of the first gate metal (first uppermost surface, Illustrative Fig. 1) and the second top surface of the second gate metal (second uppermost surface, Illustrative Fig. 1) are substantially in a same plane (Illustrative Fig. 1).
Regarding claim 7, Yang teaches the integrated circuit structure of claim 1, wherein a top of the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 1), a top of the second wall (second gate cut insulating pattern 150B, Illustrative Fig. 1), a top of the third wall (first gate cut insulating pattern 150A, Illustrative Fig. 1), the first top surface of the first gate metal (first uppermost surface, Illustrative Fig. 1), and the second top surface of the second gate metal (second uppermost surface, Illustrative Fig. 1) are substantially in a same plane (Illustrative Fig. 1).
Regarding claim 9, Yang teaches the integrated circuit structure of claim 1, wherein the first gate metal (first work function metal film ML1, Illustrative Fig. 1) completely surrounds each of the first vertical stack of nanoribbons (first vertical stack, Illustrative Fig. 1), and wherein the second gate metal (second work function metal film ML2, Illustrative Fig. 1) completely surrounds each of the second vertical stack of nanoribbons (second vertical stack, Illustrative Fig. 1).
Regarding claim 10, Yang teaches the integrated circuit structure of claim 1, wherein the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 1), the second wall (second gate cut insulating pattern 150B, Illustrative Fig. 1), and the third wall (first gate cut insulating pattern 150A, Illustrative Fig. 1) include a selected one or more of: silicon, nitrogen, carbon, oxygen, hafnium, SinN, SiC, SiON, SiCN, HfO or HfN ([0043]: “each of the first and second gate cut insulating patterns 150A and 150B and the inter-region insulating pattern 150C may include a silicon nitride film.”).
Regarding claim 11, Yang teaches the integrated circuit structure of claim 1, wherein the first top surface of the first gate metal (first uppermost surface, Illustrative Fig. 1) includes a layer of the second gate metal (second work function metal film ML2, Illustrative Fig. 1).
Regarding claim 22, Yang teaches a method (method of manufacturing an integrated circuit device, Figs. 11A through 25, [0101]) comprising:
providing an integrated circuit structure (integrated circuit device 100, Figs. 8 and 10, [0021]), wherein the integrated circuit structure (integrated circuit device 100, Figs. 8 and 10) includes:
a gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1, [0022]-[0023]),
a first gate spacer (outer insulating spacer 118 on the left as shown in Figs. 2A-B for transistors TR1 and TR2, shown as first gate spacer in Illustrative Fig. 1) and a second gate spacer (outer insulating spacer 118 on the right as shown in Fig. 2A-B for transistors TR1 and TR 2, shown as second gate spacer in Illustrative Fig. 1) on the gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1),
a first vertical stack of nanoribbons (nanosheet stacks NSS of transistor TR2, see first vertical stack in Illustrative Fig. 1, which includes annotated figures Fig. 8 and Fig. 10, [0033]: while Yang does not explicitly states that the nanosheet are nanoribbons, a person of ordinary skill in the art would understand that nanoribbons can replace nanosheet in such devices) above the gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1), wherein each of the first vertical stack of nanoribbons (first vertical stack, Illustrative Fig. 1) extend from the first gate spacer (first gate spacer, Illustrative Fig. 1) to the second gate spacer (second gate spacer, Illustrative Fig. 1),
a second vertical stack of nanoribbons (nanosheet stacks NSS of transistor TR1, see second vertical stack in Illustrative Fig. 1, [0033]) above the gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1), wherein each of the second vertical stack of nanoribbons (second vertical stack, Illustrative Fig. 1) extend from the first gate spacer (first gate spacer, Illustrative Fig. 1) to the second gate spacer (second gate spacer, Illustrative Fig. 1);
a first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 1, [0036]) extending from the gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1), a second wall (second gate cut insulating pattern 150B, Illustrative Fig. 1, [0036]) extending from the gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1), and a third wall (first gate cut insulating pattern 150A, Illustrative Fig. 1, [0036]) extending from the gate bottom (substrate 102 and isolation film 112, Illustrative Fig. 1), wherein the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 1) is between the first vertical stack of nanoribbons (first vertical stack, Illustrative Fig. 1) and the second vertical stack of nanoribbons (second vertical stack, Illustrative Fig. 1), the first vertical stack of nanoribbons (first vertical stack, Illustrative Fig. 1) is between the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 1) and the second wall (second gate cut insulating pattern 150B, Illustrative Fig. 1), and the second vertical stack of nanoribbons (second vertical stack, Illustrative Fig. 1) is between the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 1) and the third wall (first gate cut insulating pattern 150A, Illustrative Fig. 1);
placing a first gate metal (first work function metal film ML1, Illustrative Fig. 1, [0099]) around the first vertical stack of nanoribbons (first vertical stack, Illustrative Fig. 1); and
placing a second gate metal (second work function metal film ML2, Illustrative Fig. 1, [0098]) around the second vertical stack of nanoribbons (second vertical stack, Illustrative Fig. 1), wherein the second gate metal (second work function metal film ML2, Illustrative Fig. 1) has an uppermost surface (second uppermost surface, Illustrative Fig. 1) at a same level as an uppermost surface (first uppermost surface, Illustrative Fig. 1) of the first gate metal (first work function metal film ML1, Illustrative Fig. 1).
Regarding claim 23, Yang teaches the method of claim 22, wherein placing the second gate metal (second work function metal film ML2, Illustrative Fig. 1) around the second vertical stack of nanoribbons (nanosheet stacks on the left, Fig. 18 (corresponds to second vertical stack, Illustrative Fig. 1)) further includes:
placing the first gate metal (first work function metal film ML1, Fig. 18, [0121) around the second vertical stack of nanoribbons (nanosheet stacks NSS on the left, Fig. 18, [0121]);
removing the first gate metal (first work function metal film ML1, Fig. 19, [0123]) around the second vertical stack of nanoribbons (nanosheet stacks NSS on the left, Fig. 19, [0123]); and
placing the second gate metal (second work function metal film ML2, Fig. 20, [0125) around the second vertical stack of nanoribbons (nanosheet stacks NSS on the left, Fig. 20, [0125]).
Regarding claim 24, Yang teaches the method of claim 23, wherein removing the first gate metal (first work function metal film ML1, Fig. 19, [0123]) around the second vertical stack of nanoribbons (nanosheet stacks NSS on the left, Fig. 19, [0123]) further includes applying a wet etch ([0123]: “to selectively remove the first work function metal film ML1 exposed on the first device region AR1, wet etching may be performed.”) to the first gate metal (first work function metal film ML1, Fig. 19, [0123]) around the second vertical stack of nanoribbons (nanosheet stacks NSS on the left, Fig. 19, [0123]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5, 13-14, 18-19, 21, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2022/0173097 A1).
Regarding claim 5, Yang teaches the integrated circuit structure of claim 1, wherein the first gate metal (first work function metal film ML1, Illustrative Fig. 1) includes an N-type workfunction metal (transistor TR2 is a PMOS ([0032]), and therefore the first workfunction metal film ML1 of Yang is a P-type workfunction metal, however, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the transistors and their conductivity types are exchangeable, and therefore, the integrated circuit structure also applies to a device where the TR2 is an NMOS and TR1 is a PMOS) and wherein the second gate metal (second work function metal film ML2, Illustrative Fig. 1) includes a P-type workfunction metal (transistor TR1 is an NMOS ([0032]), and therefore the second workfunction metal film ML2 of Yang is a N-type workfunction metal, however, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the transistors and their conductivity types are exchangeable, and therefore, the integrated circuit structure also applies to a device where the TR1 is an PMOS and TR2 is a NMOS).
Regarding claim 13, Yang teaches an integrated circuit structure (integrated circuit device 100, Figs. 8 and 10, [0021]) comprising:
a bottom layer (substrate 102, Fig. 10, [0022]);
a first epitaxial structure (first source/drain region SD1 of transistor Tr1 within cross-section X1-X1’ in Fig. 1, Fig. 2A, see the location of second epitaxial structure as indicated in Illustrative Fig. 2, which is an annotated version of Figs. 2A and 8, [0050]; [0109]: “The first source/drain regions SD1 may be formed by epitaxially growing”) on the bottom layer (substrate 102, Fig. 2A) and between a first gate spacer (inner insulating spacers 120 on the left of transistor TR1 and TR2, see first gate spacer labeled as location in Illustrative Fig. 2, [0036]: while Yang’s TR2 does not have inner insulating spacers 120, a person of ordinary skill in the art before the effective filing date of the claimed invention would know that it is common to have devices where transistor TR2 can also have inner insulating spacers, as evidenced by Huang (US 2024/0079277 A1, see inner spacer layer 160 ([0061] in Figs. 1P-2 and 1P-3 corresponding to the device in Fig. 1P-1) and the case where the nanosheets of one nanosheet stacks have different sizes in the first horizontal direction (X-direction) in Yang ([0029])) and a second gate spacer (inner insulating spacers 120 on the left of transistor TR2 );
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a second epitaxial structure (second source/drain region SD2 of transistor Tr2 within cross-section X2-X2’ in Fig. 1, Fig. 2B, but with inner insulating spacers 120 as shown in Fig. 2A, see the location of second epitaxial structure as indicated in Illustrative Fig. 2, [0048]) on the bottom layer (substrate 102, Figs. 2A-B) that extends from the first gate spacer (first gate spacers, Illustrative Fig. 2) to the second gate spacer (second gate spacers, Illustrative Fig. 2);
a first wall (inter-region insulating pattern 150C/550C, Fig. 10 and Illustrative Fig. 2, [0036]) extending from the bottom layer (substrate 102, Illustrative Fig. 2) and between the first gate spacer (first gate spacer, Illustrative Fig. 2) and the second gate spacer (second gate spacer, Illustrative Fig. 2: first wall extends along a line form the first gate spacer to the second gate spacer), wherein the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 2) separates the first epitaxial structure (first epitaxial structure, Illustrative Fig. 2) and the second epitaxial structure (second epitaxial structure, Illustrative Fig. 2: first wall is between the first and second epitaxial structures) from each other;
a second wall (first gate cut insulating pattern 150A, Fig. 10 and Illustrative Fig. 2, [0036]) extending from the bottom layer (substrate 102, Fig. 9 and Illustrative Fig. 2) and between the first gate spacer (first gate spacers, Illustrative Fig. 2) and the second gate spacer (second gate spacers, Illustrative Fig. 2: first wall extends along a line form the first gate spacer to the second gate spacer), wherein the first epitaxial structure (first epitaxial structure, Illustrative Fig. 2) is between the second wall (first gate cut insulating pattern 150A, Illustrative Fig. 2) and the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 2);
a third wall (second gate cut insulating pattern 150B, Fig. 10 and Illustrative Fig. 2, [0036]) extending from the bottom layer (substrate 102, Fig. 10 and Illustrative Fig. 2) and between the first gate spacer (first gate spacer, Illustrative fig. 2) and the second gate spacer (second gate spacer, Illustrative fig. 2), wherein the second epitaxial structure (second epitaxial structure as indicated, Illustrative Fig. 2) is between the third wall (second gate cut insulating pattern 150B, Illustrative Fig. 2) and the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 2);
wherein a first top surface of the first epitaxial structure (first source/drain region SD1, Fig. 2A) and a second top surface of the second epitaxial structure (second source/drain region SD2, Fig. 2B) are planar (Figs. 2A-B: both structures have planar top surfaces, except the contact regions);
a first vertical stack of nanoribbons (nanosheet stacks NSS of transistor TR1, see first vertical stack in Illustrative Fig. 3, which includes an annotated figures Fig. 8 and Fig. 10, [0033]: while Yang does not explicitly state that the nanosheet are nanoribbons, a person of ordinary skill in the art would understand that nanoribbons can replace nanosheet in such devices) within the first gate spacer (first gate spacer, Illustrative Fig. 3);
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a second vertical stack of nanoribbons (nanosheet stacks NSS of transistor TR2, see first vertical stack in Illustrative Fig. 3, which includes an annotated figures Fig. 8 and Fig. 10, [0033]: while Yang does not explicitly state that the nanosheet are nanoribbons, a person of ordinary skill in the art would understand that nanoribbons can replace nanosheet in such devices) within the second gate spacer (second gate spacer, Illustrative Fig. 3);
wherein the first epitaxial structure (Fig. 2A: first source/drain region SD1 (first epitaxial structure in Illustrative Fig. 2)) is directly coupled with a portion of the first vertical stack of nanoribbons (Fig. 2A: the nanosheet N1, N2, and N3 are in direct contact with the first source/drain region SD1), and wherein the second epitaxial structure (Fig. 2B: second source/drain region SD2 (second epitaxial structure in Illustrative Fig. 2)) is directly coupled with a portion of the second vertical stack of nanoribbons (Fig. 2B: the nanosheet N1, N2, and N3 are in direct contact with the second source/drain region SD2); and
a first gate metal (second work function metal film ML2, Illustrative Fig. 4, which includes annotated figures Fig. 8 and Fig. 10, [0099]) surrounding the first vertical stack of nanoribbons (first vertical stack, Illustrative Fig. 4) and a second gate metal (first work function metal film ML1, Illustrative Fig. 4, [0098]) surrounding the second stack of nanoribbons (second vertical stack, Illustrative Fig. 4), wherein the first gate metal (second work function metal film ML2, Illustrative Fig. 4) has an uppermost surface (first uppermost surface, Illustrative Fig. 4) at a same level as an uppermost surface (second uppermost surface, Illustrative Fig. 4) of the second gate metal (first work function metal film ML1, Illustrative Fig. 4).
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Regarding claim 14, Yang teaches the integrated circuit structure of claim 13, wherein the first top surface of the first epitaxial structure (first source/drain region SD1, Fig. 2A) and the second top surface of the second epitaxial structure (second source/drain region SD2, Fig. 2B) are in a same plane (Figs. 2A-B: both structures have the same height, and therefore the top surfaces are in a same plane).
Regarding claim 18, Yang teaches the integrated circuit structure of claim 13, wherein the first epitaxial structure (first source/drain region SD1 of transistor Tr1, Fig. 2A) is a P- type epitaxial structure ([0048]: “n-type”, however, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the transistors and their conductivity types are exchangeable), and the second epitaxial structure (second source/drain region SD2 of transistor Tr2, Fig. 2B) is an N-type epitaxial structure ([0048]: “p-type”, however, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the transistors and their conductivity types are exchangeable).
Regarding claim 19, Yang teaches the integrated circuit structure of claim 13, further comprising a terminal contact ([0060]: conductive line, Fig. 10, [0060]) above the first wall (inter-region insulating pattern 550C, Figs. 8: the conductive line connects source/drain regions SD1 and SD2 by via contacts 192 (Figs. 12A-B., [0060]), and therefore has to cross the first wall from top view), wherein the terminal contact (conductive line) is between the second wall (first gate cut insulating pattern 150A, Fig. 8) and the third wall (second gate cut insulating pattern 150B, Fig. 8), and wherein the terminal contact (conductive line) is electrically coupled with the first epitaxial structure (first source/drain region SD1 of transistor Tr1 within cross-section X1-X1’ in Fig. 8) and electrically coupled with the second epitaxial structure (second source/drain region SD1 of transistor Tr1 within cross-section X1-X1’ in Fig. 8, [0060]: “The first and second source/drain regions SD1 and SD2 may be connected to a conductive line thereabove through the source/drain contacts 174 and the source/drain via contacts 192.”).
Regarding claim 21, Yang teaches the integrated circuit structure of claim 13, wherein the first wall (inter-region insulating pattern 150C/550C, Fig. 10), the second wall (first gate cut insulating pattern 150A, Fig. 10), or the third wall (second gate cut insulating pattern 150B) extend above the first top surface of the first epitaxial structure (first source/drain region SD1 of transistor Tr1 within cross-section X1-X1’ in Fig. 8, Fig. 2A) or the second top surface of the second epitaxial structure (second source/drain region SD2 of transistor Tr2 within cross-section X2-X2’ in Fig. 8, Fig. 2B: see Illustrative Fig. 2 for a comparison of the heights of the walls and epitaxial structures).
Regarding claim 25, Yang teaches the method of claim 22, wherein the first gate metal (first work function metal film ML1, Illustrative Fig. 1) is a N-type gate metal (transistor TR2 is a PMOS ([0032]), and therefore the first workfunction metal film ML1 of Yang is a P-type workfunction metal, however, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the transistors and their conductivity types are exchangeable, and therefore, the integrated circuit structure also applies to a device where the TR2 is an NMOS and TR1 is a PMOS), and wherein the second gate metal (second work function metal film ML2, Illustrative Fig. 1) is a P-type gate metal (transistor TR1 is an NMOS ([0032]), and therefore the second workfunction metal film ML2 of Yang is a N-type workfunction metal, however, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the transistors and their conductivity types are exchangeable, and therefore, the integrated circuit structure also applies to a device where the TR1 is an PMOS and TR2 is a NMOS).
Claims 8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2022/0173097 A1) as applied to claims 1-4, 6-7, 9-11 above, and further in view of Huang (US 2024/0079277 A1).
Regarding claim 8, while Yang teaches the integrated circuit structure of claim 1, wherein a top of the first wall (inter-region insulating pattern 150C/550C, Illustrative Fig. 1), a top of the second wall (first gate cut insulating pattern 150A, Illustrative Fig. 1), and a top of the third wall (first gate cut insulating pattern 150A, Illustrative Fig. 1) are in a first plane (Illustrative Fig. 1), wherein the first top surface of the first gate metal (first uppermost surface, Illustrative Fig. 1) and the second top surface of the second gate metal (first uppermost surface, Illustrative Fig. 1) are in a second plane (Illustrative Fig. 1),
Yang does not teach that the second plane is below the first plane with respect to the gate bottom (In Yang, the first plane and second plane are at the same level).
Huang, on the other hand, teaches an integrated circuit structure (semiconductor device structure, Figs. 1P, 1P-1, 1P-2, [0113]) which is analogous to the integrated circuit structure of Yang, and wherein a top of the first wall (isolation structure 210 in the middle, Fig. 1P, [0122]), a top of the second wall (isolation structure 210 on the left, Fig. 1P, [0122]), and a top of the third wall (isolation structure 210 on the right, Fig. 1P, [0122]) are in a first plane (Fig. 1P), wherein the first top surface of the first gate metal (work function metal layer 240, Figs. 1L and 1P, [0123]) and the second top surface of the second gate metal (work function metal layer 250, Figs. 1L and 1P, [0123]) are in a second plane (Fig. 1P), and the second plane is below the first plane with respect to the gate bottom (Base 112, Fig. 1, [0138]).
Huang further discloses that etching the first metal gate (work function metal layer 240, Figs. 1K-1L, [0101]) and the second metal gate (work function metal layer 250, Figs. 1K-1L, [0101]) so that second plane is moved down below the first plane (Fig. 1L) to form a gate electrode layer (gate electrode layer 260, Fig. 1L) would simplify the manufacturing devices where the gate contacts of neighboring NMOS and PMOS devices need to be connected to each other (Abstract and [0002]-[0004]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include gate electrode layers, as taught by Huang, above the first and second gate metals in the integrated circuit structure of Yang (in Yang’s device the gates are also connected, see Fig. 10), which provides the benefit of improving the miniaturization of the device and simplifying the manufacturing process. Thus, the combination of Yang and Huang leads to a integrated circuit structure wherein the second plane is below the first plane with respect to the gate bottom.
Regarding claim 12, while Yang teaches the integrated circuit structure of claim 1,
Yang is silent about a width of the first vertical stack or a width of the second vertical stack, and therefore, does not teach that a width of each of the first vertical stack of nanoribbons or a width of each of the second vertical stack of nanoribbons is greater than 25nm.
Huang, on the other hand, teaches an integrated circuit structure (semiconductor device structure, Figs. 1P, 1P-1, 1P-2, [0113]) which is analogous to the integrated circuit structure of Yang, and also comprises a first wall (isolation structure 210 in the middle, Fig. 1P, [0122]), a second wall (isolation structure 210 on the left, Fig. 1P, [0122]), a third wall (isolation structure 210 on the right, Fig. 1P, [0122]), a first gate metal (work function metal layer 240, Figs. 1L and 1P, [0123]) a second gate metal (work function metal layer 250, Figs. 1L and 1P, [0123]), a first vertical stack of nanoribbons (channel nanostructures 124A of the nanostructure stack 120A, Fig. 1P, [0044]; nanosheet can be nanoribbons ([0030]) and a second vertical stack of nanoribbons (channel nanostructures 124B of the nanostructure stack 120B, Fig. 1P, [0045]; nanosheet can be nanoribbons ([0030]), wherein a width of each of the first vertical stack of nanoribbons or a width of each of the second vertical stack of nanoribbons is greater than 25nm ([0124]: “a width W120A of the nanostructure stack 120A or 120B ranges from about 8 nm to about 60 nm”).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the integrated circuit structure of Yang is analogous to the integrated circuit structure of Huang, and therefore would be motivated to form the first vertical stack of nanoribbons and second vertical stack of nanoribbons in the integrated circuit structure of Yang so that a width of each of the first vertical stack of nanoribbons or a width of each of the second vertical stack of nanoribbons ranges from 8 nm to about 60 nm, which would help miniaturization of the device (Huang: [0002]-[0004]). Therefore, the range of widths provided by the prior art overlaps with the range of thickness provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of widths of the first and second stacks of nanoribbons can be optimized by routine experimentation to achieve desired device miniaturization while maintaining a desired device performance (see MPEP 2144.05(II)). Therefore, the range of values provided does not hold an inventive subject matter.
Claims 15-16 and 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2022/0173097 A1) as applied to claims 13-14, and 18-19 above and further in view of Hsu (US 2022/0320090 A1).
Regarding claim 15, while Yang teaches the integrated circuit structure of claim 14,
Yang does not teach that a top of the second wall and a top of the third wall are in the same plane.
Hsu, on the other hand, teaches an integrated circuit structure (semiconductor device 200, Figs. 28A-C, [0005]), comprising a first epitaxial structure (first source/drain structures 242, Fig. 13B, [0047]) and a second epitaxial structure (second source/drain structures 244, Fig. 13C, [0047]), wherein the top surfaces of the first epitaxial structure (first source/drain structures 242, Fig. 13B) and the second epitaxial structure (second source/drain structures 244, Fig. 13C) are in a same plane ([0050]: “… same level with the top surface of the topmost second epitaxial layer 208”). Hsu further discloses that the top surfaces of the first wall (dielectric fin 218c, Fig. 14A, [0027]), the second wall (dielectric fin 218a, Fig. 14A, [0027]), and the third wall (dielectric fin 218b, Fig. 14A, [0027]) are also at the same level with the topmost second epitaxial layer. Therefore, Hsu teaches that a top of the second wall and a top of the third wall are in the same plane.
It would be obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that making the top surfaces of the second and third walls on the same plane would provide a structure with minimal thickness while preserving the self-alignment using the walls as the spacers ([0008]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the integrated circuit structure of Yang to make the top of the second wall and the top of the third wall in the same plane as taught by Hsu which would provide the benefit of using self-alignment processes during manufacturing while keeping the thickness low.
Regarding claim 16, while Yang teaches the integrated circuit structure of claim 15,
Yang does not teach that a top of the first wall is in the same plane.
Yang, however, teaches that the first wall (inter-region insulating pattern 150C/550C, Fig. 10), second wall (first gate cut insulating pattern 150A, Fig. 10), and third wall (second gate cut insulating pattern 150B, Fig. 10) have the same height. Therefore, the combination of Yang and Hsu (see claim 15 rejection above) meets the limitation that a top of the first wall is in the same plane.
Regarding claim 20, Yang teaches the integrated circuit structure of claim 13, further comprising a first terminal contact (source/drain via contacts 192, Fig. 2A, [0060]) on the first epitaxial structure (first source/drain region SD1 of transistor Tr1 within cross-section X1-X1’ in Fig. 8, Fig. 2A) and a terminal contact (source/drain via contacts 192, Fig. 2B) on the second epitaxial structure (second source/drain region SD1 of transistor Tr2 within cross-section X2-X2’ in Fig. 8, Fig. 2B), wherein the first terminal contact (source/drain via contacts 192, Figs. 2A and 8) is between the second wall (first gate cut insulating pattern 150A, Fig. 8) and the first wall (inter-region insulating pattern 150C/550C, Figs. 8), wherein the second terminal contact (source/drain via contacts 192, Fig. 2B) is between the third wall (second gate cut insulating pattern 150B, Fig. 8) and the first wall (inter-region insulating pattern 150C/550C, Figs. 8), and
Yang, however, does not teach that the first terminal contact and the second terminal contact are electrically isolated from each other.
Hsu, on the other hand, teaches an integrated circuit structure (semiconductor device 200, Figs. 28A-C, [0005]), comprising a first terminal contact (contact 296, Fig. 28B, [0095]) on the first epitaxial structure (first source/drain structures 242, Fig. 28B, [0047]) and a second terminal contact (contact 298, Fig. 28C, [0095]) on the second epitaxial structure (second source/drain structures 244, Fig. 28C, [0047]), wherein the first terminal contact (contact 296, Fig. 28B) and the second terminal contact (contact 298, Fig. 28C) are electrically isolated from each other (by the dielectric layer 290, Figs. 28A-C, [0096]).
It would be obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the two transistors can be operated independently if their contacts are electrically isolated from each other. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to use the transistors independent from each other would be motivated to modify the integrated circuit structure of Yang to electrically isolate the first terminal contact and the second terminal contact from each other as taught by Hsu.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 13, 20, and 22, and canceled claim 17 per response dated on 2/27/2026. Applicant's arguments with respect to claims have been fully considered.
Regarding independent claim 1, amended claim 1, now also disclosing the limitation that “the first gate metal has an uppermost surface at a same level as an uppermost surface of the second gate metal” overcame the 35 U.S.C. 102 rejection based on Hsu (US 2022/0320090 A1). However, amended claim 1 is now rejected under new grounds based on Yang (US 2022/0173097 A1). Accordingly, claims 2-12 which are dependent on claim 1 are also rejected based on Yang or Yang combined with the remaining prior art of the non-final office action.
Regarding independent claim 13, amended claim 13, now also disclosing the limitations that
“a first vertical stack of nanoribbons within the first gate spacer;
a second vertical stack of nanoribbons within the second gate spacer;
wherein the first epitaxial structure is directly coupled with a portion of the first vertical stack of nanoribbons, and wherein the second epitaxial structure is directly coupled with a portion of the second vertical stack of nanoribbons; and
a first gate metal surrounding the first vertical stack of nanoribbons and a second gate metal surrounding the second stack of nanoribbons, wherein the first gate metal has an uppermost surface at a same level as an uppermost surface of the second gate metal.”,
however, failed to overcome the 35 U.S.C. 102 rejection based on Yang (US 2022/0173097 A1), as detailed in the office action above. Therefore, claim 13 remains rejected based on Yang, and claims 14-16, and 18-21 are also rejected based on the prior art of the non-final office action.
Regarding independent claim 22, amended claim 22, now also disclosing the limitations that “the second gate metal has an uppermost surface at a same level as an uppermost surface of the first gate metal”, overcame the 35 U.S.C. 102 rejection based on Hsu (US 2022/0320090 A1). However, amended claim 22 is now rejected under new grounds based on Yang (US 2022/0173097 A1). Accordingly, claims 23-25 which are dependent on claim 22 are also rejected based on Yang or Yang combined with the remaining prior art of the non-final office action.
For the purpose of compact prosecution, the Examiner notes, however, clarifying the structure of the first, second, and third walls in regard to first and second gate spacers, and/or clarifying the structure of first and second gate spacers in regard to first and second epitaxial structures and first and second nanosheet stacks by including further limitations might make independent claim 1, 13, and 22 inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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