DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-3, 5-10, 12-17, 19-24, and 25-34 have been amended.
Claim 35 has been cancelled.
Claim 36 has been added.
Claims 1-34 and 36 have been examined.
The drawing and claim objections in the previous Office Action have been addressed and are withdrawn.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn, except as otherwise indicated below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-34 and 36 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites, at line 9, “the logical OR classification.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the logical OR .” Claims 8, 15, 22, 29, and 36 have similar language and are similarly rejected.
Claim 2 recites, at lines 1-2, “the field for the identification of the packed data source operand.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the field for the identification of the location of the packed data source operand.” Claims 3, 9, 10, 16, 17, 23, 24, 30, and 31 have similar language and are similarly rejected.
Claims 2-7, 9-14, 16-21, 23-28, and 30-34, and 36 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-34 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2014/0208077 by Bradbury et al. (hereinafter referred to as “Bradbury” in view of US Publication No. 2016/0085721 by Abali et al. (hereinafter referred to as “Abali”)).
Regarding claims 1, 8, 15, 22, and 29, taking claim 1 as representative, Bradbury discloses:
an apparatus comprising: decode circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, an identification of a location of a packed data source operand, an indication of one or more classification checks to perform, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operand, a classification of a …[floating point] data element according to the indicated one or more classification checks… and store a result … in a corresponding data element position of the destination operand (Bradbury discloses, at Figure 11 and related description, a computer having decode and execution circuitry. Bradbury also discloses, at Figures 4A-4D and related description, operation of an instruction that has fields for an opcode (element 402), a source vector (element 406), an indication of classification checks to perform (element 408), a destination (element 404) which, when executed, checks the class of each floating point element of the source vector according to the indicated checks and updates the destination in a corresponding position based on the results of the checks. Bradbury also discloses, at Figure 10 and related description, using non-transitory computer readable storage media and, at Figure 2B and related description, translating instructions between ISAs and processing the translated instructions.); and
the execution circuitry to execute the decoded instruction according to the opcode (Bradbury discloses, at Figure 11 and related description, a computer having decode and execution circuitry, which discloses executing the decoded instruction according to the opcode.).
Bradbury does not explicitly disclose the data elements are FP8, logically ORing results of the one or more classification checks, and the aforementioned result is of a logical OR. However, Bradbury discloses a range of sizes for the floating point data elements. For example, Bradbury discloses, e.g., at ¶¶ [0053]-[0056], between 1 and 16 elements in a vector register having 128 bits. In the case of 16 bit elements, the size of the elements would be 8 bits.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury’s instruction to use FP8 data elements to improve the versatility of the instruction.
Also in the same field of endeavor (e.g., processors) Abali discloses:
performing logical OR operations and storing the results (Abali discloses, at ¶ [0075], performing a logical OR on intermediate results, which discloses the results of the classification checks. Storing is implicit.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury to include logical ORing results, as disclosed by Abali, in order to improve performance by providing a more concise result regarding whether any of checks had a positive result.
Regarding claims 2, 9, 16, 23, and 30, taking claim 2 as representative, Bradbury, as modified, discloses the elements of claim 1, as discussed above. Bradbury also discloses:
the field for the identification of the packed data source operand is to identify a vector register (Bradbury discloses, at Figures 4A-4D and related description, the field for the identification of the first source operand is to identify a vector register.).
Regarding claims 3, 10, 17, 24, and 31, taking claim 3 as representative, Bradbury, as modified, discloses the elements of claim 1, as discussed above. Bradbury does not explicitly disclose the field for the identification of the packed data source operand is to identify a memory location. However, Bradbury discloses, at ¶ [0188], that “contents of one or more fields of an instruction may be provided in a general purpose register, in memory, in an element of a vector register (differing per element) or from an address computation, as examples.”
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury’s instruction to use memory because doing so would improve the flexibility of the instruction.
Regarding claims 4, 11, 18, 25, and 32, taking claim 4 as representative, Bradbury, as modified, discloses the elements of claim 1, as discussed above. Bradbury also discloses:
the one or more classification checks is one or more of quiet non-a-number (QNAN), signaling not-a-number (SNAN), positive zero, negative zero, positive infinity, negative infinity, denormal, or finite negative (Bradbury discloses, at Figure 4B and related description, various classes that can be checked, which discloses quiet non-a-number (QNAN), signaling not-a-number (SNAN), positive zero, negative zero, positive infinity, negative infinity, denormal, or finite negative.).
Regarding claims 5, 12, 19, 26, and 33, taking claim 5 as representative, Bradbury, as modified, discloses the elements of claim 1, as discussed above. Bradbury also discloses:
the one or more classification checks to perform is to be provided by an immediate (Bradbury discloses, at Figures 4A-4D and related description, the field for the identification of the checks is an immediate.).
Regarding claims 6, 14, 21, and 28, taking claim 6 as representative, Bradbury, as modified, discloses the elements of claim 1, as discussed above. Bradbury does not explicitly disclose the one or more classification checks to perform is to be provided by an identified register. However, Bradbury discloses, at ¶ [0188], that “contents of one or more fields of an instruction may be provided in a general purpose register, in memory, in an element of a vector register (differing per element) or from an address computation, as examples.”
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury’s instruction to use a register because doing so is a design choice between well-known alternatives involving commonplace tradeoffs, such as speed versus size. For example, including information in an instruction word enables fast execution because doing so eliminates the need for a memory access. However, the tradeoff is an increase in size of the instruction word.
Regarding claims 7, 13, 20, 27, and 34, taking claim 7 as representative, Bradbury, as modified, discloses the elements of claim 1, as discussed above. Bradbury also discloses:
the instance of the single instruction is to further include one or more fields for a writemask…(Bradbury discloses, at Figures 4A-4D and related description, a mask field 410, which discloses a writemask. See also claim 9.).
Bradbury does not explicitly disclose including the aforementioned writemask is stored in a register.
However, Bradbury discloses, at ¶ [0188], that “contents of one or more fields of an instruction may be provided in a general purpose register, in memory, in an element of a vector register (differing per element) or from an address computation, as examples.”
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury’s instruction to use a register because doing so is a design choice between well-known alternatives involving commonplace tradeoffs, such as speed versus size. For example, including information in an instruction word enables fast execution because doing so eliminates the need for a memory access. However, the tradeoff is an increase in size of the instruction word.
Regarding claim 36, Bradbury, as modified, discloses the elements of claim 1, as discussed above. Bradbury does not explicitly disclose the result of the logical OR classification is a single bit per data element position.
However, in the same field of endeavor (e.g., processors) Abali discloses:
performing logical OR operations to produce a single bit (Abali discloses, at ¶ [0075], performing a logical OR on intermediate results to generate a single bit.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury to include logical ORing, as disclosed by Abali, in order to improve performance by providing a more concise result regarding whether any of checks had a positive result.
Response to Arguments
On page 10 of the response filed January 5,2026 (“response”), the Applicant argues, “Bradbury does not appear to describe using a logical OR of classification checks.”
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Please see above for new grounds of rejection of the amended claims. Ababali discloses combining results by performing a logical OR. See, e.g., ¶ [0075]. It would have been obvious to combine Bradbury and Abali to provide a concise indication as to whether any of the checks was positive.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 20160188328 by Ould discloses ORing results of conflict checks.
US 20110191567 by Lancaster discloses using logical OR to see if any flags are set.
US 20160246604 by Winrow discloses using OR.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183