CTFR 17/958,369 CTFR 93119 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-14 and 16-29 have been amended. Claims 1-30 have been examined. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 AIA Claim s 1-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites, at lines 3-4, “an identification of location of a packed data source/destination operand.” Claim 1 then recites, at lines 6-7, a second instance of, “an identification of location of a packed data source/destination operand.” It cannot be definitely determined whether this requires a single field or two fields. Two fields would appear to contradict the written description. For example, Figure 2 shows an instruction that has a single field that identifies a source and destination. For purposes of examination, the claim is interpreted as a single field that identifies both the source operand in question and the destination operand. Claim 1 recites, at lines 10-11, “the source/destination operand.” There is insufficient antecedent basis for this term. Claim 1 previously recites two instances of, “a packed data source/destination operand,” and no instances of, “a source/destination operand.” Claim 16 includes similar language and is similarly rejected. Claims 2-15 and 17-30 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 14-16, 29, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over NPL “The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA” by Waterman et al. (hereinafter referred to as “Waterman”) in view of US Publication No. 2020/0310757 by Gradstein et al. (hereinafter referred to as “Gradstein”) in view of US Publication No. 2022/0075595 by Agrawal et al. (hereinafter referred to as “Agrawal ‘595”) . Regarding claims 1 and 16, taking claim 1 as representative , Waterman discloses: …[a] single instruction to include fields for an opcode, an identification of location of a …operand (a first packed data source operand), an identification of a location of a second … source operand, an identification of a location of a third … source operand, and an identification of location of a … [destination] operand, wherein the opcode is to indicate operand ordering and that execution circuitry is to, per data element position, perform a …fused multiply- accumulate operation using the first, second, and third … source operands and store a result in a corresponding data element position of the …[destination] operand … (Waterman discloses, at pages 16-17, a fused multiply-add instruction that includes fields for an opcode, three source operands, and a destination operand. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose an apparatus comprising: decoder circuitry to decode a single instruction, the aforementioned operands are packed data operands, the aforementioned first source and destination are a single operand, the aforementioned instruction is an FP8 value instruction, wherein the FP8 value has an 8-bit floating point format that comprises one bit for a sign, 4 bits for an exponent, and three bits for a fraction, and execution circuitry to execute the decoded single instruction according to the opcode. However, Waterman discloses, at page 31, using packed data. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman’s fused multiply-add instruction to use packed data in order improve performance by increasing parallelism. Also, in the same field of endeavor (e.g., processing) Gradstein discloses: an apparatus comprising: decoder circuitry to decode a single instruction, the aforementioned first source and destination are a single operand, and execution circuitry to execute the decoded single instruction according to the opcode (Gradstein discloses, at Figure 13 and related description, decode and execution circuitry. Gradstein also discloses, Figure 24 and related description, specifying sources that can also serve as a destination.). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include Gradstein’s processing circuitry and combined source/destination in order to improve performance by implementing Waterman’s instructions and reducing the number of fields needed in an instruction word, thereby reducing code size. Also, in the same field of endeavor (e.g., processing) Agrawal ‘595 discloses: an FP8 value instruction, wherein the FP8 value has an 8-bit floating point format that comprises one bit for a sign, 4 bits for an exponent, and three bits for a fraction (Agrawal ‘595 discloses, at ¶ [0024], using 1/4/3 FP8.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include 1/4/3 FP8 values, as disclosed by Agrawal ‘595, in order to improve performance by reducing loss of accuracy. See Agrawal, ‘595, ¶ [0024]. Regarding claims 14 and 29, taking claim 14 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the first and second packed data source operands are registers (Waterman discloses, at pages 16-17, a fused multiply-add instruction that uses registers. See also page 5.) . Regarding claim 15 , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: memory to store the single instruction (Waterman discloses, at pages 16-17, a fused multiply-add instruction. Memory to store the instruction is inherent.) . Regarding claim 30 , Waterman, as modified, discloses the elements of claim 16, as discussed above. Waterman does not explicitly disclose translating the single instruction to at least one instruction of a different instruction set architecture, wherein executing the decoded single instruction according to the opcode comprises executing the at least one instruction of the different instruction set architecture. However, in the same field of endeavor (e.g., processing) Gradstein discloses: translating the single instruction to at least one instruction of a different instruction set architecture, wherein executing the decoded single instruction according to the opcode comprises executing the at least one instruction of the different instruction set architecture (Gradstein discloses, at Figure 35 and related description, converting instructions from one instruction set to a target instruction set, which discloses executing the instructions in the target instruction set.). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include converting between instruction sets, as disclosed by Gradstein, in order to improve performance by providing execution flexibility . 07-21-aia AIA Claim s 2-13 and 17-28 are rejected under 35 U.S.C. 103 as being unpatentable over Waterman in view of Gradstein in view of Agrawal ‘595 in view of US Publication No. 2021/0048991 by Tanner (hereinafter referred to as “Tanner”) . Regarding claims 2 and 17, taking claim 2 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element position multiplication of the FP8 value from …[a multiplier] source operand with the FP8 value in …[a multiplicand] source operand to generate an …intermediate result, an addition of the … intermediate result negated to the FP8 values in the …[addend] source operand to generate an … addition result, and a round of the … addition result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy. Regarding claims 3 and 18, taking claim 3 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element multiplication of the FP8 value from …[a multiplier] source operand with the FP8 value in …[a multiplicand] source operand to generate an ...intermediate result, an addition of the ...intermediate result negated to the FP8 value in the …[addend] source operand to generate an ...addition result, and a round of the ...addition result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy. Regarding claims 4 and 19, taking claim 4 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element multiplication of the FP8 value from …[a multiplier] to the FP8 value in …[a multiplicand] source operand to generate an ...intermediate result, an addition of the ...intermediate result negated to the FP8 value in the …[addend] source operand to generate an ...addition result, and a round of the ...addition result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy. Regarding claims 5 and 21, taking claim 5 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element multiplication of the FP8 value from …[a multiplier] source operand to the FP8 value in …[a multiplicand] source operand to generate an ...intermediate result, an addition of a the FP8 value in the …[addend] source operand to generate an ...addition result, and a round of the ...addition result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy. Regarding claims 6 and 20, taking claim 6 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element multiplication of the FP8 value from …[a multiplier] source operand to the FP8 value in …[a multiplicand] source operand to generate an ...intermediate result, an addition of a the FP8 value in the …[addend] source operand to generate an ...addition result, and a round of the ...addition result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy. Regarding claims 7 and 22, taking claim 7 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element multiplication of the FP8 value from …[a multiplier] to the FP8 value in …[a multiplicand] source operand to generate an ...intermediate result, an addition the FP8 value in the…[addend] source operand to generate an ...addition result, and a round of the ...addition result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy. Regarding claims 8 and 23, taking claim 8 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element multiplication of the FP8 value from …[a multiplier] source operand to the FP8 value in …[a multiplicand] source operand to generate an ...intermediate result, a subtraction of the ...intermediate result negated to the FP8 value in the …[addend] source operand to generate an ...subtraction result, and a round of the ...addition result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy. Regarding claims 9 and 24, taking claim 9 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element multiplication of the FP8 value from …[a multiplier] source operand to the FP8 value in …[a multiplicand] source operand to generate an ...intermediate result, a subtraction of the ...intermediate result negated to the FP8 value in the …[addend] source operand to generate an ...subtraction result, and a round of the ...subtraction result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy. Regarding claims 10 and 25, taking claim 10 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element multiplication of the FP8 value from …[a multiplier] to the FP8 value in …[a multiplicand] source operand to generate an ...intermediate result, a subtraction of the ...intermediate result negated to the FP8 value in the …[addend] source operand to generate an ...subtraction result, and a round of the ...subtraction result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy. Regarding claims 11 and 26, taking claim 11 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element multiplication of the FP8 value from …[a multiplier] source operand to the FP8 value in …[a multiplicand] operand to generate an ...intermediate result, a subtraction of the FP8 value in the …[addend] source operand to generate an ...subtraction result, and a round of the ...addition result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy. Regarding claims 12 and 27, taking claim 12 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element multiplication of the FP8 value from …[a multiplier] source operand to the FP8 value in …[a multiplicand] source operand to generate an ...intermediate result, a subtraction of the FP8 value in the …[addend] source operand to generate an ...subtraction result, and a round of the ...subtraction result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy. Regarding claims 13 and 28, taking claim 13 as representative , Waterman, as modified, discloses the elements of claim 1, as discussed above. Waterman also discloses: the opcode is to indicate the fused multiply accumulation operation is per data element multiplication of the FP8 value from …[a multiplier] source to the FP8 value in …[a multiplicand] source operand to generate an ...intermediate result, a subtraction of the FP8 value in the …[addend] source operand to generate an ...subtraction result, and a round of the ...addition result (Waterman discloses, at pages 16-17, a fused multiply-add instruction that multiplies a multiplier and multiplicand, then adds or subtracts an addend, performs rounding, and optionally negates the result. The opcode specifies the instruction, which specifies the operand ordering.). Waterman does not explicitly disclose encoding different operand orderings in the opcode and an infinite precision result. However, Waterman discloses encoding control information in the opcode, such as rounding mode and data type. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include control information specifying the operand ordering in order to improve performance by allowing increased control and flexibility in execution of the instruction. Also, in the same field of endeavor (e.g., processing) Tanner discloses: infinite precision (Tanner discloses, at ¶ [0095], results using infinite precision.) . It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Waterman to include infinite precision, as disclosed by Tanner, in order to improve performance by reducing loss of accuracy . Response to Arguments On page 10 of the response filed December 29, 2026 (“response”), the Applicant argues, “Waterman is cited for the first, second, and third operands, however, Waterman uses a separate destination than the first source operand whereas the claims require a "source/destination operand."” Though fully considered, the Examiner respectfully disagrees. The term “source/destination” operand can be interpreted as an operand that stores either a source or a destination. Therefore the term reads on Waterman’s disclosed source operands. However, to expedite prosecution the Examiner cites Gradstein. Gradstein explicitly discloses operands that are used as a source initially then overwritten with results. See Gradstein, ¶ [0206]. This discloses the claimed source/destination” operand. On page 10 of the response the Applicant argues, “With respect to the FP8 aspect, Agrawal describes FP as either being 1/5/2 or 1/6/1 which is not 1/4/3.” These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Please see above for new grounds of rejection of the amended claims. Agrawal ‘595 discloses 1/4/3. See, e.g., ¶ [0024]. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAWN DOMAN/ Primary Examiner, Art Unit 2183 Application/Control Number: 17/958,369 Page 2 Art Unit: 2183 Application/Control Number: 17/958,369 Page 3 Art Unit: 2183 Application/Control Number: 17/958,369 Page 4 Art Unit: 2183 Application/Control Number: 17/958,369 Page 5 Art Unit: 2183 Application/Control Number: 17/958,369 Page 6 Art Unit: 2183 Application/Control Number: 17/958,369 Page 7 Art Unit: 2183 Application/Control Number: 17/958,369 Page 8 Art Unit: 2183 Application/Control Number: 17/958,369 Page 9 Art Unit: 2183 Application/Control Number: 17/958,369 Page 10 Art Unit: 2183 Application/Control Number: 17/958,369 Page 11 Art Unit: 2183 Application/Control Number: 17/958,369 Page 12 Art Unit: 2183 Application/Control Number: 17/958,369 Page 13 Art Unit: 2183 Application/Control Number: 17/958,369 Page 14 Art Unit: 2183 Application/Control Number: 17/958,369 Page 15 Art Unit: 2183 Application/Control Number: 17/958,369 Page 16 Art Unit: 2183 Application/Control Number: 17/958,369 Page 17 Art Unit: 2183
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