DETAILED ACTION
Claims 1-5, 7-14, and 16-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amended title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. At this point in time, the examiner proposes --Instructions to Convert From Packed FP8 to FP16 or FP32 Using Variable Bias--.
The amended abstract of the disclosure is objected to because of the following minor informalities:
In line 4, replace “the” with --an--.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In paragraph 168, the example embodiments include language used in the claims. For similar reasoning set forth in previous/current objections/rejections, these paragraphs should be updated as the claims are updated, particularly where incorrect or unclear.
Appropriate correction is required.
Drawings
Replacement FIG.5 is objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The drawing is pixelated because applicant did not use black (RGB = 000), despite the drawing appearing black to the naked eye. In such a case, the dithering used to convert applicant's grayscale image to black and white will add white pixels to try to estimate applicant's "gray" color, and the final drawing may not print properly or may print with reduced quality. Therefore, applicant must be sure to use only black and white. Applicant may try the following process to correct the color content:
1. Open the drawings PDF file with Adobe Acrobat Pro DC (a similar Adobe product may work, but the examiner has only tested this in Adobe Acrobat Pro DC);
2. Click “File” and then click “Print”;
3. Select “Adobe PDF” as the printer. If not available, “Microsoft Print to PDF” may also work, though this has not been tested. If neither option is available, this process may not be applicable, and applicant should try to find an alternate way to print in only black and white.
4. Uncheck “Print in grayscale (black and white)”;
5. Uncheck “Save ink/toner”;
6. Click “Advanced”;
7. Under “Color Management”, for the “Color Profile” field, select “Black & White” near the bottom of the list. The examiner also had “Treat grays as K-only grays” checked, and “Preserve Black” checked.
8. Click “OK” and then click “Print”. The resulting PDF should comprise only black and white drawing(s). Please review the final drawing(s) for potential unintended consequences of this process.
NOTE: If applicant is unable to perform the above conversion, the examiner would be willing to perform the conversion and email the resulting pdf file to applicant for formal filing once all other objections are resolved, provided an Authorization for Internet Communications (PTO/SB/439) is on record (see MPEP 502.03).
Replacement FIG.5 is objected to because of the following minor informalities:
In step 507, line 2, insert --OPERAND-- after “SOURCE”.
A corrected drawing sheet in compliance with 37 CFR 1.121(d) is required in reply to the Office action to avoid abandonment of the application. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities:
In line 8, insert --the-- after “or”.
Claim 4 is objected to because of the following informalities:
In line 2, replace “8-bit floating-point” with --FP8-- since applicant established the abbreviation in claim 1.
Claim 5 is objected to because of the following informalities:
In line 2, replace “8-bit floating-point” with --FP8-- since applicant established the abbreviation in claim 1.
Claim 7 is objected to because of the following informalities:
In line 4, insert --the-- after “or”.
In line 4, delete “values”.
Claim 8 is objected to because of the following informalities:
In line 5, insert --operand-- after “source”.
In line 8, replace “converted” with --half-precision floating-point data or the single-precision floating-point--, so that “the converted data” is not confused for the FP8 data that is converted, i.e., the FP8 data.
Claim 11 is objected to because of the following informalities:
In line 2, replace “8-bit floating-point” with --FP8-- since applicant established the abbreviation in claim 8.
Claim 12 is objected to because of the following informalities:
In line 2, replace “8-bit floating-point” with --FP8-- since applicant established the abbreviation in claim 8.
Claim 14 is objected to because of the following informalities:
In line 4, insert --the-- after “or”.
In line 4, delete “values”.
Claim 16 is objected to because of the following informalities:
In line 7, insert --the-- after “or”.
Claim 17 is objected to because of the following informalities:
In lines 2-3, replace “8-bit floating-point” with --FP8-- since applicant established the abbreviation in claim 16.
Claim 18 is objected to because of the following informalities:
In lines 2-3, replace “8-bit floating-point” with --FP8-- since applicant established the abbreviation in claim 16.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7 and 14 are indefinite because they are inconsistent with the disclosure. The claims set forth using a mask to indicate which of the half-/single-precision data are written to the destination, which suggests that an FP8 value can be converted, but the result may not be written based on the mask. However, FIGs.6-9 show checking the mask first, and, only if the mask indicates to write to a destination element, converting an FP8 value. If the mask is ‘0’, for instance, then the conversion never takes place for that element. As such, there can never be a converted data element (result of conversion) that isn’t written to the destination based on the mask. It is unclear what the invention actually is and it will be interpreted according to the operation of FIGs.6-9. See MPEP 2173.03. Applicant is asked to point to the relevant portion in the specification/drawings and provide any necessary explanation for how these claims are consistent with that described in the disclosure.
Claim 8 is indefinite because it is not clear what applicant means by “the converted data”. This could describe the FP8 values since the FP8 values are the values that are converted (into other values). This could also describe the FP16/32 values, which result from conversion. For prior art purposes, the examiner will assume applicant means the latter based on FIGs.2-3. The examiner recommends using the language proposed in the claim 8 objection above.
Claims 9-14 are rejected due to their dependence on an indefinite claim.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 13 and 19 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends. Specifically, parent claims 8 and 16 set forth an execution circuit to convert FP8 data using a variable bias. Claims 13 and 19 set forth that the executing uses a variable bias to convert from FP8. Since the execution unit is understood to perform the executing, claims 13 and 19 appear to add nothing beyond what is already present in the corresponding independent claims. Applicant may cancel claims 13 and 19, amend them to be in proper dependent form, or present a sufficient showing that they comply with the statutory requirements.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-5, 7-14, and 16-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding step 1 of the Subject Matter Eligibility Test, all claims are directed to a statutory category of invention, with claims 1-7 being for a machine, claims 8-15 being for a process, and claims 16-20 being for an article of manufacture.
Regarding step 2A (prong 1) of the Subject Matter Eligibility Test, claim 1 recites to convert 8-bit floating-point (FP8) data to half/single-precision floating-point data and using a variable bias. Such conversion involves various mental and/or mathematical steps (e.g., see the algorithms on pp.13-15 of the specification, and note that various bias values (at least one of which may be a variable bias) is used in the algorithm to convert). Specifically, a human provided with various FP8 input data values could mentally and mathematically perform, with or without the aid of pen and paper, the claimed conversion. Thus, claim 1 recites an abstract idea.
Regarding step 2A (prong 2) of the Subject Matter Eligibility Test, of all remaining elements recited by claim 1, a single instruction having fields for opcode, source operand, and destination operand amounts to a mere instruction to implement the abstract idea, and an apparatus with a decoder to decode the instruction and execution circuitry to execute the instruction amount to generic computer components to perform the abstract idea. The data claimed as being packed is indicative of a generic SIMD/vector machine. The courts have found these types of elements to not integrate the abstract idea into a practical application (hereafter “does/do not integrate”) (see MPEP 2106.04(d)(I)), 6th bullet). Additionally, an additional element of storing the half/single-precision elements that result from the conversion is insignificant post-solution activity incidental to the conversion itself that and no more than a nominal or tangential addition to the claim. Such does not integrate (see MPEP 2106.04(d)(I)), 7th bullet). Finally, linking the conversion to a SIMD/vector technological environment does not integrate (see MPEP 2106.04(d)(I)), 8th bullet).
Regarding step 2B of the Subject Matter Eligibility Test, the additional elements, considered alone and in combination, do not amount to significantly more than the abstract idea because the courts have determined that using an instruction and generic computer to implement the abstract idea does not amount to significantly more (see MPEP 2106.05(I)(A), second (i) and 2106.05(f)), and because storing output data to memory has been deemed by the courts to be well-understood, routine, and conventional and not significantly more (see MPEP 2106.05(I)(A) and 2106.05(d), including section II, item (iv) (“Storing…information in memory”)). Finally, linking the abstract idea to a generic SIMD technological environment has been deemed by the courts to not amount to significantly more (see MPEP 2106.05(I)(A), second (iv) and 2106.05(h)). Therefore, claim 1 is subject matter-ineligible under 35 U.S.C. 101 (hereafter “SMI”).
Referring to claim 2, applicant claiming a vector register for the source amounts to claiming a generic computer component and/or more linking to a generic technological environment, which do not integrate or amount to significantly more for reasoning set forth above. Thus, claim 2 is SMI.
Referring to claim 3, applicant claiming a memory location for the source amounts to claiming a generic computer component and/or more linking to a generic technological environment, which do not integrate or amount to significantly more for reasoning set forth above. Thus, claim 3 is SMI.
Referring to claim 4, claiming the type/format of the data amounts to adding more to the mental process and/or mathematical calculation. Thus, claim 4 is SMI.
Referring to claim 5, claiming the type/format of the data amounts to adding more to the mental process and/or mathematical calculation. Thus, claim 5 is SMI.
Referring to claim 7, applicant adds a writemask to control writing of the results of the conversion. Such a writemask is a generic computer component in a SIMD machine, and therefore the writemask does not integrate or amount to significantly more for reasoning set forth above. Additionally, the storing based on a writemask is more insignificant post-solution activity that does not integrate. The storing is well-understood, routine, and conventional, as described above. Furthermore, Official Notice is taken that storing based on a writemask in a SIMD/vector machine is well-known in the art, and, as such, the use of a writemask also does not amount to significantly more. Thus, claim 7 is SMI.
Claims 8-14 are SMI for similar reasoning as claims 1-5, 1, and 7, respectively.
Claim 16 is mostly SMI for similar reasoning as claim 1. The additional element of a medium to store the instruction is a generic computer component to carry out the conversion. For reasons above, this does not integrate or amount to significantly more.
Claims 17-20 are SMI for similar reasoning as claims 4-5 and 1-2, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Intel, “Intel Architecture Instruction Set Extensions Programming Reference”, February 2016, 1180 pages, in view of Mach et al., “A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing”, IEEE, 2018, 5 pages, and Wikipedia, “Exponent bias”, April 15, 2022, 2 pages.
Referring to claim 1, Intel has taught an apparatus (an apparatus (including processor) having the architecture of Intel) comprising:
decoder circuitry (a decoder must exist to decode instructions to create control signals to control processing logic to carry out desired operations) to decode a single instruction (see the VCVTPH2PS (hereafter referred to as “CVT”) instruction on p.5-120), the single instruction to include one or more fields to identify a source operand (on p.5-120, the top table shows the bottom three instruction formats including an xmm2/ymm2 field. From the description, this corresponds to a source of the data elements), one or more fields to identify a destination operand (the same formats shown an xmm1/ymm1/zmm1 field, which corresponds to a destination where results of the instruction are stored), and one or more fields for an opcode (the instruction includes a binary opcode that represents “VCVTPH2PS”), the opcode to indicate that execution circuitry is to convert packed 16-bit floating point (FP16) data from the identified source operand to (see the description of the CVT instruction) and store the (see the description of the CVT instruction. An example is shown in an illustration on p.5-121); and
execution circuitry to execute the decoded instruction according to the opcode (execution circuitry must exist to react to a decode instruction to actually perform the desired operation indicated by the opcode).
Intel has not taught to convert FP8 data into half/single-precision data. However, Mach has taught converting FP8 (binary8, per section II, 2nd paragraph, which states “Binary8 is an 8-bit format…”) data into single-precision floating-point data (standard IEEE binary32 (section I, 3rd paragraph)). For instance, FIG.3, shows a Slice32 unit to convert between FP32 and FP8 and a Slice16 unit to convert between FP16 and FP8. An example instruction to perform such a conversion is shown in TABLE I (bottom row). One of ordinary skill in the art would have recognized that Intel’s CVT instruction could be modified to convert FP8 instead of FP16, for instance, to realize a new instruction in the instruction set that would increase programming flexibility by giving more conversion options and allowing for use of FP8, which trades accuracy for even more memory space savings and quicker computations compared to FP16. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Intel to convert FP8 data into half/single-precision data in the manner taught for the CVT instruction. This realizes the advantages set forth above and also allows 8-bit results to be used in larger-bit operations going forward, where desired.
Intel, as modified, has not taught using a variable bias. However, Wikipedia has taught exponent bias in floating-point representation in order to simplify comparison of floating-point numbers as well as allow for representation of exponents in a signed range (so that the stored floating-point number can be made smaller or larger). Wikipedia shows that the bias is calculated based on the number of bits in the exponent (e.g. for 32-bit floating-point numbers, the exponent has 8 bits, so the bias is set to 127. For 64-bit floating-point numbers, the exponent has 11 bits, so the bias is set to 1023). One of ordinary skill in the art understands that, because FP8 is only 8 bits, the exponent must include fewer than 8 bits. This means the bias would be smaller than 127 for FP8. Thus, any conversion from FP8 to FP16 or FP32 would involve varying bias values (e.g. the system would convert from a first bias for FP8 to a second bias for FP16). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Intel to use a variable bias to perform the conversion from FP8 to half or single precision FP. Again, this would at least be useful for faster comparison of numbers where comparisons are to be performed.
Referring to claim 2, Intel, as modified, has taught the apparatus of claim 1, wherein the one or more fields to identify the source operand identify a vector register (xmm2/ymm2 are vector registers (see illustration on p.5-121)).
Referring to claim 3, Intel, as modified, has taught the apparatus of claim 1, wherein the one or more fields to identify the source operand identify a memory location (xmm2/ymm2 are vector registers, i.e., memory locations (see illustration on p.5-121)).
Referring to claim 7, Intel, as modified, has taught the apparatus of claim 1, wherein the single instruction is further to include one or more fields to identify a writemask operand (from pp.5-120 to 5-121, the instruction uses a writemask k1. A field in the instruction (e.g. opcode or some additional field) identifies use of k1), wherein one or more bits of the writemask operand are to indicate to execution circuitry which of the half-precision floating-point data or single-precision floating-point data values are to be written in the destination operand (from p.5-120, “[t]he destination operand is a…register conditionally updated with writemask k1.” Also, note use of k1 in the code on p.5-121”).
Claims 8-10 and 13-14 are rejected for similar reasoning set forth in the rejections of claims 1-3, 1, and 7, respectively.
Claim 16 is mostly rejected for similar reasoning as claim 1. Furthermore, Intel has taught a non-transitory machine readable medium storing an instance of the single instruction (a processor having the architecture that is the subject of Intel would fetch instructions from a non-transitory medium that stores program code so as to process the instructions).
Claims 19-20 are rejected for similar reasoning set forth in the rejections of claims 1-2, respectively.
Claims 4-5, 11-12, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Intel in view of Mach, Wikipedia, and Noune et al., “8-Bit Numerical Formats for Deep Neural Networks”, June 6, 2022, pp.1-30.
Referring to claim 4, Intel, as modified, has taught the apparatus of claim 1, but has not taught wherein elements of the source operand are in an 8-bit floating-point format having 1 bit for a sign, 5 bits for an exponent, and 2 bits for a fraction. However, Noune has taught use of 1.5.2 FP format in neural network applications (see section 2.2, Table 1, and section 5). The 1.5.2 format is advantageous for gradients with respect to activations and weights in a neural network. Also, 1.5.2 has the highest dynamic range (D) of the 8-bit formats. The examiner asserts that any type of data could be converted, and, as a result, for benefits to be realized in AI applications in Intel, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Intel such that elements of the source operand are in an 8-bit floating-point format having 1 bit for a sign, 5 bits for an exponent, and 2 bits for a fraction.
Referring to claim 5, Intel, as modified, has taught the apparatus of claim 1, but has not taught wherein elements of the source operand are in an 8-bit floating-point format having 1 bit for a sign, 4 bits for an exponent, and 3 bits for a fraction. However, Noune has taught use of 1.4.3 FP format in neural network applications (see section 2.2, Table 1, and section 5). The 1.4.3 format is advantageous for activations and weights in a neural network. Also, 1.4.3 shows the most balance between dynamic range (D) and signal-to-noise ratio (SNR) of the 8-bit formats. The examiner asserts that any type of data could be converted, and, as a result, for benefits to be realized in AI applications in Intel, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Intel such that elements of the source operand are in an 8-bit floating-point format having 1 bit for a sign, 4 bits for an exponent, and 3 bits for a fraction.
Claims 11-12 and 17-18 are rejected for similar reasoning set forth in the rejections of claims 4-5 and 4-5, respectively.
Response to Arguments
On page 11 of applicant’s response, applicant states that they would prefer to not update paragraph 168 as the claim language changes.
The paragraphs do not need to be in line with the claims word for word. However, the examiner does expect the informalities and typographical issues to be corrected. For instance:
On page 37, last line, and on page 38, line 6, applicant should insert --operand-- after “source” to match the previous reference.
Embodiment 8 appears to be incorrect by storing packed FP8 data into the destination along with the other data that results from the conversion.
In embodiment 15, last line, replace “as” with --to-- to improve grammar.
On page 13 of applicant’s response, applicant argues that converting between FP8 and other floating-point formats is an improvement to existing processors, and that the claims reflect an improvement to technology.
Even if an improvement can be said to exist, the improvement cannot be provided by the judicial exception alone. The improvement must be provided by at least one additional element (MPEP 2106.05(a)). Applicant is arguing the conversion is the improvement. But, the conversion is the judicial exception and, thus, cannot be relied upon to provide the improvement. The remaining elements in the claim amount to generic computer components and a mere instruction to implement the judicial exception, conventional insignificant extra-solution activity, and a mere link to a particular (packed/SIMD/vector) environment. All of these things have been held, by the courts, to not integrate an abstract idea into a practical application, and to not amount to significantly more. Thus, the argument is not persuasive and the 101 rejection is maintained.
On page 15 of applicant’s response, applicant argues that Mach does not discuss what is meant by “conversion operations”, nor does Mach actually describe converting from the 8-bit size to something else.
The examiner respectfully disagrees. FIG.3 shows units labeled as FP32 ↔ FP8 and FP16 ↔ FP8 in components labeled “Floating-Point Conversion Unit” (the examiner notes that this is easier to see in the online version of the document (applicant may Google the title of the article)). The double arrow is indicative of conversion going both ways. Table 1 also shows an example conversion instruction being fcvt.b.s, which the examiner understands to be conversion from b format (binary8) to single-precision (s) format (binary32). Presumably, to realize the disclosed conversion from b format to h format (binary 16), an fcvt.b.h instruction would be used. These teachings make it clear to one of ordinary skill in the art that FP8 may be converted into another format.
On page 15 of applicant’s response, applicant argues that Noune does not say a bias is considered in a conversion.
First, this argument is moot because applicant amended claim 6 (now in claim 1) to set forth using a bias when converting from FP8 as opposed to going to FP8 (and, thus, the examiner has brought in a different reference for this teaching). However, Noune was used previously for the teaching that FP8 can be used with different exponent biases (which have different advantages). Thus, any of these could be used in Intel and any could be converted to. Since there could be FP8 formats with different biases, a variable bias is used. Note that Noune doesn’t teach conversion, but the combination of art teaches conversion between various formats, and biases may be obviously taken into consideration. The examiner also notes the breadth of variable bias in the claims. The examiner recommends possibly claiming how each position/field of a packed register provides an exponent bias value for a corresponding FP8 element from the source operand (paragraphs 31-32 of the specification). Please note that this is not to be taken as an indication of allowability. However, the prior art used in the rejections does not appear to teach this (further consideration would be required).
Conclusion
The following prior art previously and/or currently made of record and not relied upon is considered pertinent to applicant's disclosure:
Jiang, 8,280,936, has taught a SIMD instruction that converts four 8-bit restricted FP format values into four single-precision FP values (FIG.4). This reference is deemed particularly relevant to at least applicant’s independent claims and should be taken into consideration when drafting a response to this office action.
GeeksforGeeks has taught “IEEE Standard 754 Floating Point Numbers”, which make use of a biased exponent and shows how converting to FP16 or FP32 includes using different bias values (variable bias).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights