Prosecution Insights
Last updated: July 05, 2026
Application No. 17/958,395

INVERTED FERROELECTRIC AND ANTIFERROLECETRIC CAPACITORS

Final Rejection §103
Filed
Oct 01, 2022
Examiner
IMTIAZ, S M SOHEL
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Final)
91%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
502 granted / 554 resolved
+22.6% vs TC avg
Moderate +7% lift
Without
With
+7.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
570
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
92.2%
+52.2% vs TC avg
§102
3.7%
-36.3% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 554 resolved cases

Office Action

§103
DETAILED ACTION This office action is in response to applicant’s amendments filed on 05/11/2026. Currently claims 1-6, 8, 9, 11-18, 20-22, 27, and 29-33 are pending in the application. Response to Arguments Applicant’s arguments are moot because the rejection on the new claims does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 31-32 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/028/6984 A1 (Chang) and further in view of US 2017/0114241 A1 (Almadhoun). Regarding claim 31, Chang discloses, an apparatus comprising: PNG media_image1.png 909 1074 media_image1.png Greyscale an integrated circuit component (1600; IC device; Fig. 11; [0035]) comprising: a substrate (1602; substrate; Fig. 11; [0045]); PNG media_image2.png 467 776 media_image2.png Greyscale a plurality of pillars (as annotated on Fig. 7A; [0027]) comprising a first metal (electrode 102-1 made of titanium metal, in the form of titanium nitride; [0017]), individual of the pillars located on the substrate (1602), the pillars comprising a top surface and an outer surface (as annotated on Fig. 7A; [0027]), the pillars (evident from Figs. 7A and 11) located within a recess (as annotated on Fig. 11; [0046]) of a first layer (1626; dielectric material; Fig. 11; [0046]) comprising a dielectric material; a second layer (110; inter-electrode stack, made of ferroelectric material or an antiferroelectric material) comprising a ferroelectric material or an antiferroelectric material, the second layer (110) located on the top surface and the outer surface of the pillars (as annotated on Fig. 7A; [0027]); a third layer (102-2; electrode; Fig. 7A; [0017]) comprising a second metal (copper, aluminum, gold, tungsten, cobalt, platinum, or iridium; [0017]), the third layer (102-2) located on the top surface and the outer surface of the pillars, the second layer (110) positioned between the pillars and the third layer (102-2), the third layer (102-2) filling a volume between adjacent pillars (as evident in Fig. 7A). But Chang fails to teach explicitly, wherein the apparatus comprises: a printed circuit board; and a first integrated circuit component attached to the printed circuit board, However, in analogous art, Almadhoun discloses, wherein the apparatus comprises: a printed circuit board; and a first integrated circuit component attached to the printed circuit board ([0016]; usually integrated circuit component is attached to the printed circuit board along with the capacitor). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chang and Almadhoun before him/her, to modify the teachings of a ferroelectric capacitor as taught by Chang and to include the teachings of ferroelectric capacitor being part of an integrated circuit and a printed circuit board as taught by Almadhoun since this is how the ferroelectric capacitors are connected to the integrated circuit package. Absent this important teaching in Chang, a person with ordinary skill in the art would be motivated to reach out to Almadhoun while forming a ferroelectric capacitor of Chang. But the combination of Chang and Almadhoun fails to teach explicitly, individual of the pillars isolated from all other pillars in the plurality of pillars; However, in MPEP 2144.04 (V) (C), the court held that if it were considered desirable for any reason to make the pillars separable to use them individually or for any other reason, it would be obvious to make the pillars separable for that purpose. In re Dulberg, 289 F.2d 522, 523, 129 USPQ 348, 349 (CCPA 1961). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chang, Almadhoun and MPEP 2144.04 (V) (C) before him/her, to modify the teachings of a ferroelectric capacitor as taught by Chang and to make the individual of the pillars isolated from all other pillars in the plurality of pillars. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0017] and/or [0031] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Regarding claim 32, Chang discloses, the apparatus of claim 31, wherein the base is conductively coupled to a source region or a drain region of transistor (Fig. 8; [0042]), the source region or the drain region located on a surface region of the substrate (1602) and comprising one or more n-type or p-type dopants (source/drain regions will have n-type or p-type dopants). PNG media_image3.png 689 628 media_image3.png Greyscale Allowable Subject Matter Claim 33 is objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims. Regarding claim 33, the closest prior art, US 2020/0286984 A1 (Chang), in conjunction with US 2017/0114241 A1 (Almadhoun), and in combination with the other claimed features, fails to disclose, “the apparatus of claim 31, wherein the second layer comprises a plurality of portions, individual of the portions physically separate from all other portions, individual of the portions encompassing the top surface and the outer surface of at least one of the pillars”, in combination with the additionally claimed features, as are claimed by the Applicant. Specifically, the aforementioned ‘the apparatus of claim 31, wherein the second layer comprises a plurality of portions, individual of the portions physically separate from all other portions, individual of the portions encompassing the top surface and the outer surface of at least one of the pillars,’ is material to the inventive concept of the application at hand to manufacture pillar-type capacitors that can provide a greater capacitance density per unit area relative to planar capacitors. Claims 1-6, 8, 9, 11-18, 20-22, 27, and 29-30 are allowed. The following is the examiner’s statement of reasons of allowance. Amended independent claim 1 is allowable because the closest prior art US Patent Pub # US 2020/028,6984 A1 to Chang teaches, an apparatus (100; capacitor; Fig. 7A; [0028]) comprising: PNG media_image2.png 467 776 media_image2.png Greyscale a plurality of pillars (as annotated on Fig. 7A; [0027]) comprising a first metal (electrode 102-1 made of titanium metal, in the form of titanium nitride; [0017]), individual of the pillars comprising a top surface and an outer surface (as annotated on Fig. 7A; [0027]); a first layer (110; inter-electrode stack, made of ferroelectric material or an antiferroelectric material) comprising a ferroelectric material or an antiferroelectric material, the first layer (110) located on the top surface and the outer surface of the pillars (as evident in Fig. 7A); a second layer (102-2; electrode; Fig. 7A; [0027]) comprising a second metal (Chang teaches that the electrode 102-1 and the electrode 102-2 may have a different material composition, which means 102-2 can be a second metal; [0017]), wherein the second layer (102-2) is located on the top surface and the outer surface of the pillars, the first layer (110) positioned between the pillars and the second layer (as evident in Fig. 7A), PNG media_image4.png 1182 1304 media_image4.png Greyscale wherein the pillars are located (evident from Figs. 7A and 11) within a recess (as annotated on Fig. 11; [0046]) of a dielectric layer (1626; dielectric layer; Fig. 11; [0046]), the second layer (102-2) substantially filling the recess such that a volume between adjacent pillars is substantially filled by the second layer (102-2); and a substrate (1602; substrate; Fig. 11; [0045]), the pillars located on the substrate (1602). However, neither Chang nor any cited prior art, appear to explicitly disclose, in combination with the other claimed features, wherein the first layer comprising a plurality of portions, individual of the portions physically separate from all other portions, individual of the portions encompassing the top surface and the outer surface of at least one of the pillars. Examiner’s Note: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by “wherein the first layer comprising a plurality of portions, individual of the portions physically separate from all other portions, individual of the portions encompassing the top surface and the outer surface of at least one of the pillars”. Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, the claim is deemed patentable over the prior arts. Specifically, the aforementioned ‘wherein the first layer comprising a plurality of portions, individual of the portions physically separate from all other portions, individual of the portions encompassing the top surface and the outer surface of at least one of the pillars,’ is material to the inventive concept of the application at hand to manufacture pillar-type capacitors that can provide a greater capacitance density per unit area relative to planar capacitors. Dependent claims 2-6, 8, 9, 11-18, 20-22, 27 and 29-30 depend, directly or indirectly, on allowable independent claim 1. Therefore, claims 2-6, 8, 9, 11-18, 20-22, 27 and 29-30 are also allowable. Examiner’s Note (Additional Prior Arts) The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure. US 2020/0066916 A1 (Chen) - A MFM structure is disclosed that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors. US 2023/0328997 A1 (Lu) - A ferroelectric memory device is disclosed including a multi-layer stack disposed on a substrate. The multi-layer stack has a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S M SOHEL IMTIAZ/Primary Patent Examiner Art Unit 2812 06/17/2025
Read full office action

Prosecution Timeline

Oct 01, 2022
Application Filed
May 15, 2023
Response after Non-Final Action
Feb 13, 2026
Non-Final Rejection mailed — §103
May 11, 2026
Response Filed
Jun 23, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
91%
Grant Probability
98%
With Interview (+7.0%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 554 resolved cases by this examiner. Grant probability derived from career allowance rate.

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