DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1, 2, and 4-27 are pending.
Claim 3 is cancelled.
Claims 1, 4, 8, 15, and 23 are amended.
Response to Arguments/Amendments
The previous objection to the claims for informalities has been overcome by the amended claims filed 09/05/2025 and is withdrawn.
The previous objection to the specification for minor informalities has been overcome by the amended specification filed 09/05/2025 and is withdrawn.
Response regarding Claim Rejections - 35 USC § 112
The arguments filed 09/05/2025 regarding the 35 U.S.C. 112(b) rejections of claims 4, 10, 12, 19, 20, 21, and 26 do not overcome the previous rejection. Specifically, applicant argues that the specification, in at least paragraph 0045, clarifies that “about” is required to mean +/- 10% the stated numerical value, however the language of the specification only dictates that “about” can, for example, be +/- 10% the stated numerical value, and thus does not provide sufficient clarification for the scope of claims 4, 10, 12, 19, 20, 21, and 26. Additionally, it is noted that for claims such as claim 21, wherein the range is “about 10nm to about 1um,” the upper limit of the range (1um +/- 100nm) is varied by a factor of 10x the lower stated value of the range (10nm). It would not, therefore, be apparent that +/-10% would be necessary value assigned to the term “about.” The rejections of claims 4, 10, 12, 19, 20, 21, and 26 are maintained.
The arguments filed 09/05/2025 regarding the 35 U.S.C. 112(b) rejection of claim 4, specifically in reference to the claim language “wherein a specific resistance of the graphene interconnect is reduced by about 1.1 times to about 10 times” do not overcome the previous rejection. The plain meaning of the term “reduced by” indicates subtraction. Applicant argues that the common meaning of the term “times” is to represent a multiplication operation, and in view of the common use of “reduced by” and “times,” it would be reasonable to a person of ordinary skill in the art to interpret the claims as indicating that the specific resistance is being reduced by subtraction of 1.1 to 10 times the original value.” Absent any further clarifying matter in the disclosure of the application (e.g. specific numerical values of specific resistance, graphs/charts showing change in specific resistance), the application fails to particularly point out or distinctly claim the subject matter which the inventor regards as the invention. The rejection of claim 4 is maintained.
Response regarding Claim Rejections - 35 USC § 102/103
Applicant's arguments filed 09/05/2025 regarding amended claims 1, 15, and 23 have been fully considered but they are not persuasive. Specifically, the argument regarding “wherein a work function of the graphene layer varies due to a dipole moment generated at an interface between the first oxide dielectric material layer and the second oxide dielectric material layer” is not persuasive. As to claim 1, Maad et al. (Modulation of electron transfer in Si/SiO2/HfO2/Graphene by the HfO2 thickness, Applied Physics A, 2020), herein Maad, teaches a graphene interconnect structure comprising: a first oxide dielectric material layer (10); a second oxide dielectric material layer (20) on a surface (101) of the first oxide dielectric material layer, and having a dielectric constant greater (see page 1, column 10) than a dielectric constant of the first oxide dielectric material layer; and a graphene layer (30) on a first surface (201) of the second oxide dielectric material layer opposite to a second surface (202) of the second oxide dielectric material layer, the second surface (202) of the second oxide dielectric material layer being on the first oxide dielectric material layer (10). As to the language of claims 1, 15, and 23, specifically: “wherein a work function of the graphene layer varies due to a dipole moment generated at an interface between the first oxide dielectric material layer and the second oxide dielectric material layer”, the examiner notes that these are merely properties of the materials utilized. Since Maad teaches the exact same claimed materials and claimed structural relationship between the material layers, then Maad also teaches the claimed electrical properties, as they must necessarily be the same.
The rejections of claims 1, 15, and 23 are upheld. Accordingly, the rejections of claims 2, 4-14, 16-22, and 24-27 are upheld.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 10, 12, 19, 20, 21, and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the phrasing “wherein a specific resistance of the graphene interconnect structure is reduced by about 1.1 times to about 10 times” renders the claim indefinite for failing to distinctly claim the subject matter, because it is unclear if the specific resistance is being divided by a factor of 1.1 to 10, if the specific resistance is reduced by 1.1% to 10%, or if the specific resistance is being reduced by subtraction of 1.1 to 10 times the original value.
For the purposes of examination, it will be interpreted that the specific resistance value is divided by a factor of 1.1 to 10.
Regarding claims 4, 10, 12, 19, 20, 21, and 26, the term “about” is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Applicant dictates in Paragraph 0045 that “about” can, for example, be +/- 10% the stated numerical value, but does not provide sufficient clarification for the scope of claims 4, 10, 12, 19, 20, 21, and 26.
For the purposes of examination, it will be interpreted that “about” refers to +/- 10% of the stated numerical value.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 8, 9, 10, 14, 23, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Maad, further in view of Kita et al. (Intrinsic Origin of Electric Dipoles Formed at High-K/SiO2 Interface, Dept of Materials Engineering, The University of Tokyo), herein referred to as Kita, and further in view of Naghdi (Tuning the work function of graphene toward application as anode and cathode, Journal of Alloys and Compounds, Vol. 805), herein referred to as Naghdi.
Regarding claim 1, Maad teaches (annotated Fig. 1 below), a graphene interconnect structure comprising: a first oxide dielectric material layer (10); a second oxide dielectric material layer (20) on a surface (101) of the first oxide dielectric material layer, and having a dielectric constant greater (Page 1, Col. 1) than a dielectric constant of the first oxide dielectric material layer; and a graphene layer (30) on a first surface (201) of the second oxide dielectric material layer opposite to a second surface (202) of the second oxide dielectric material layer, the second surface (202) of the second oxide dielectric material layer being on the first oxide dielectric material layer (10).
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Maad does not explicitly teach wherein a work function of the graphene layer varies due to a dipole moment generated at an interface between the first oxide dielectric material layer and the second oxide dielectric material layer.
Kita teaches wherein a dipole moment is generated at an interface between the first oxide dielectric material layer and the second oxide dielectric material layer (Page 2, Col. 1, Para. 1).
Because Maad and Kita are both directed toward dielectric heterostructures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad and Kita in order to increase the electronic energy of the heterostructure device (Kita, Page 2, Col. 1, Para. 1).
Maad in view of Kita does not explicitly teach wherein a work function of the graphene layer varies.
Naghdi teaches wherein a work function of the graphene layer varies due to a dipole moment generated at an interface between the first oxide dielectric material layer and the second oxide dielectric material layer (Page 5, Col. 2, Para. 6).
Because Maad in view of Kita and Naghdi are directed toward graphene formed over heterostructures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad in view of Kita with the teachings of Naghdi in order to manipulate the graphene layer for the desired use, such as to increase the work function to increase hole injection efficiency for use as an anode (Naghdi, Page 2, Col. 1, Para. 3).
Regarding claim 2, Maad in view of Kita and Naghdi teaches the graphene interconnect structure of claim 1, but does not explicitly teach wherein an areal oxygen density of the first oxide dielectric material layer is different from an areal oxygen density of the second oxide dielectric material layer. Maad does teach wherein the first oxide dielectric material is SiO2 and the second oxide dielectric material layer is HfO2, which have different oxygen vacancies (Maad, Page 2, Col. 1, Para. 1).
Kita teaches wherein an areal oxygen density of the first oxide dielectric material layer is different from an areal oxygen density of the second oxide dielectric material layer (Page 1, Col. 2, Para. 3).
Because Maad and Kita are both directed toward dielectric heterostructures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Maad and Kita in order to form a dipole to increase the electronic energy of the heterostructure device (Kita, Page 2, Col. 1, Para. 1).
Regarding claim 8, Maad in view of Kita and Naghdi teaches (annotated Fig. 1 above) the graphene interconnect structure of claim 1, wherein the second oxide dielectric material (20) comprises a compound represented by Formula 1, Formula 1: AxOy wherein, in Formula 1, A is at least one selected from Al, Ti, Zr, Hf, Mg, Si, Ge, Y, Lu, La, and Sr, and 0<x≤2, and 0<y≤3 (Page 2, Col. 1, Materials and Methods).
Regarding claim 9, Maad in view of Kita and Naghdi teaches (annotated Fig. 1 above) the graphene interconnect structure of claim 1, wherein the second oxide dielectric material layer (20) comprises HfO2 (Page 2, Col. 1, Materials and Methods).
Regarding claim 10, Maad in view of Kita and Naghdi teaches (annotated Fig. 1 above) the graphene interconnect structure of claim 1, wherein a thickness of the second oxide dielectric material layer (20) is in a range of about 0.3 nm to about 5 nm (Page 2, Col. 1, Materials and Methods).
Regarding claim 11, Maad in view of Kita and Naghdi teaches (annotated Fig. 1 above) the graphene interconnect structure of claim 1, wherein the graphene layer (30) is directly on the first surface (201) of the second oxide dielectric material layer (20, Page 2, Col. 1, Materials and Methods).
Regarding claim 14, Maad in view of Kita and Naghdi teaches an electronic device comprising: a substrate; and the graphene interconnect structure of claim 1 on the substrate (Page 1, Col. 2, Introduction). Maad discloses use of graphene in the microelectronics industry, on different types of structures and substrates, and therefore discloses that the graphene interconnection structure is in an electronic device.
Regarding claim 23, Maad teaches (annotated Fig. 1 above) a graphene interconnect structure comprising: a first oxide dielectric material layer (10); a graphene layer (30) on the first oxide dielectric material layer; and a second oxide dielectric material layer (20) between the first oxide dielectric material layer and the graphene layer, wherein the first oxide dielectric material layer (10) and the second oxide dielectric material layer (20) contact each other at an interface (101, 202) and have a structural imbalance at the interface (Page 2, Col. 1, Para. 1). Energy levels associated with oxygen vacancies are not the same for the two disclosed dielectric materials at the interface, which designates a structural imbalance (Page 2, Col. 1, Para. 1).
Maad does not explicitly teach wherein a work function of the graphene layer varies due to a dipole moment generated at an interface between the first oxide dielectric material layer and the second oxide dielectric material layer.
Kita teaches wherein a dipole moment is generated at an interface between the first oxide dielectric material layer and the second oxide dielectric material layer (Page 2, Col. 1, Para. 1).
Because Maad and Kita are both directed toward dielectric heterostructures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad and Kita in order to increase the electronic energy of the heterostructure device (Kita, Page 2, Col. 1, Para. 1).
Maad in view of Kita does not explicitly teach wherein a work function of the graphene layer varies.
Naghdi teaches wherein a work function of the graphene layer varies due to a dipole moment generated at an interface between the first oxide dielectric material layer and the second oxide dielectric material layer (Page 5, Col. 2, Para. 6).
Because Maad in view of Kita and Naghdi are directed toward graphene formed over heterostructures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad in view of Kita with the teachings of Naghdi in order to manipulate the graphene layer for the desired use, such as to increase the work function to increase hole injection efficiency for use as an anode (Naghdi, Page 2, Col. 1, Para. 3).
Regarding claim 26, Maad in view of Kita and Naghdi teaches (annotated Fig. 1 above) the graphene interconnect structure of claim 23, wherein a thickness of the second oxide dielectric material layer (20) is in a range of about 0.3 nm to about 5 nm (Page 2, Col. 1, Materials and Methods).
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Maad in view of Kita and Naghdi, as applied to claim 1 above, respectively, and further in view of Ueno et al. (Bromine doping of multilayer graphene for low-resistance interconnects, Japanese Journal of Applied Physics), herein referred to as Ueno.
Regarding claim 4, Maad in view of Kita and Naghdi teaches the graphene interconnect structure of claim 1, but does not explicitly teach wherein a specific resistance of the graphene interconnect structure is reduced by about 1.1 times to about 10 times according to a change in the work function of the graphene layer.
Ueno teaches (Fig. 6) that by shifting the fermi level of graphene downward, the sheet resistance of the graphene material was reduced to between 10 and 90% of the original value (Page 4, Col. 1, Sheet resistance of Br-doped MLG). Additionally, Ueno teaches that the reduction of the fermi level corresponds to an increased work function (Page 3, Col. 1, Results and Discussion).
Because Maad in view of Kita and Naghdi and Ueno are both directed toward 2D graphene, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad in view of Kita and Naghdi and Ueno in order to effectively utilize graphene as an interconnect material at nanometer-scale with lower resistance and higher endurance against electromigration (Ueno, Page 2, Introduction).
Regarding claim 12, Maad in view of Kita and Naghdi teaches the graphene interconnect structure of claim 1, but does not explicitly teach wherein a grain size of the graphene layer is in a range of about 10 nm to about 1 um.
Ueno teaches wherein grain sizes of graphene range between several tens of nanometers and several microns (Page 3, Col. 1, Experimental Procedure).
Because Maad in view of Kita and Naghdi and Ueno are both directed toward 2D graphene, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad in view of Kita and Naghdi and Ueno to control the size of the graphene grains to achieve uniformity and low resistivity (Ueno, Page 5, Effects of Br intercalation of CVD-MLG films on sheet resistance).
Claims 5-7, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Maad in view of Kita and Naghdi, as applied to claims 1 and 23 above, further in view of Gates et al. (US PGPub 2009/0203225), herein referred to as Gates.
Regarding claim 5, Maad in view of Kita and Naghdi teaches the graphene interconnect structure of claim 1, but does not explicitly teach wherein the first oxide dielectric material layer comprises an SiCOH material.
Gates teaches use of a first oxide dielectric material layer comprising a SiCOH material ([0012]).
Because Maad in view of Kita and Naghdi and Gates are both directed toward low-K dielectric materials, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad in view of Kita and Naghdi and Gates to include wherein the first oxide dielectric material comprises a SiCOH material in order to achieve thermal stability in the final device with an ultra-low-K material (Gates, [0003]).
Regarding claim 6, Maad in view of Kita and Naghdi teaches the graphene interconnect structure of claim 1, but does not explicitly teach wherein the first oxide dielectric material comprises octamethylcyclotetrasiloxane (OMCATS) (Gates, [0073]).
Gates teaches wherein the first oxide dielectric material comprises octamethylcyclotetrasiloxane (OMCATS) (Gates, [0073]).
Because Maad in view of Kita and Naghdi and Gates are both directed toward low-K dielectric materials, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine to teachings of Maad in view of Kita and Naghdi and Gates to include wherein the first oxide dielectric material comprises octamethylcyclotetrasiloxane (OMCATS) in order to provide a precursor for proper growth of the oxide dielectric material (Gates, [0073]).
Regarding claim 7, Maad in view of Kita, Naghdi and Gates teaches the graphene interconnect structure of claim 6, but does not explicitly teach wherein the first oxide dielectric material layer further comprises porous SiO2, SiO2 doped with fluorine, or amorphous boron nitride. However, Maad in view of Kita, Naghdi, and Gates does teach use of low-K materials with dielectric constant lower than that of SiO2 in order to improve switching performance of devices with small dimensions (Gates, [0003]). The specification of the instant application lists multiple low-K dielectrics without a teaching of criticality of any of the oxide dielectric materials listed. The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. In this case, the materials listed are all known low-k oxide dielectrics; therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to choose an appropriate low-K material for the graphene interconnect structure of claim 6 in order to provide improved performance in the device. See MPEP 2144.06.
Regarding claim 24, Maad in view of Kita and Naghdi teaches the graphene interconnect structure of claim 23 and the second oxide dielectric material layer comprises HfO2, but does not explicitly teach wherein the first oxide dielectric material layer comprises a SiCOH material.
Gates teaches use of a first oxide dielectric material layer comprising a SiCOH material ([0012]).
Because Maad in view of Kita and Naghdi and Gates are both directed toward low-K dielectric materials, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad in view of Kita and Naghdi and Gates to include wherein the first oxide dielectric material comprises a SiCOH material in order to achieve thermal stability in the final device with an ultra-low-K material (Gates, [0003]).
Regarding claim 25, Maad in view of Kita, Naghdi, and Gates teaches the graphene interconnect structure of claim 24, but does not explicitly teach wherein the first oxide dielectric material layer further comprises porous SiO2, SiO2 doped with fluorine, or amorphous boron nitride. However, Maad in view of Kita, Naghdi, and Gates does teach use of low-K materials with dielectric constant lower than that of SiO2 in order to improve switching performance of devices with small dimensions (Gates, [0003]). The specification of the instant application lists multiple low-K dielectrics without a teaching of criticality of any of the oxide dielectric materials listed. The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. In this case, the materials listed are all known low-k oxide dielectrics; therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to choose an appropriate low-K material for the graphene interconnect structure of claim 24 in order to provide improved performance in the device. See MPEP 2144.06.
Claims 13, 15, 17-19, 22, and 27 is rejected under 35 U.S.C. 103 as being unpatentable over Maad in view of Kita and Naghdi, as applied to claim 1 above, further in view of Zhu et al. (New Routes to Graphene, Graphene Oxide and Their Related Applications, Advanced Materials, Volume 24), herein referred to as Zhu.
Regarding claim 13, Maad in view of Kita and Naghdi teaches the graphene interconnect structure of claim 1, but does not explicitly teach wherein the graphene layer comprises 1 to 7 layers. Maad teaches wherein the graphene layer is single-layer (Page 2, Col. 2, Results and Discussion).
Zhu teaches wherein the graphene layer can be a monolayer, bilayer, or a few layers (Page 8, Col. 2, Para. 2).
Because Maad in view of Kita and Naghdi and Zhu are both directed toward CVD growth of graphene, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Maad in view of Kita and Naghdi and Zhu in order to improve layer coverage (Page 8, Col. 2, Para. 2).
Regarding claim 15, Maad teaches (annotated Fig. 1 below) a method of manufacturing a graphene interconnect structure, the method comprising: preparing a first oxide dielectric material layer (10, Page 2, Col. 1, Materials and Methods); forming a second oxide dielectric material layer (20) by atomic layer deposition (ALD) on a surface of the first oxide dielectric material layer (Page 2, Col. 1, Materials and Methods), a dielectric constant of the second oxide dielectric material layer being greater than a dielectric constant of the first oxide dielectric material layer (Page 1, Col. 1); and a graphene layer (30) by chemical vapor deposition (CVD) (Page 2, Col. 1, Materials and Methods) on a surface (201) of the second oxide dielectric material layer opposite to a surface (202) on which the first oxide dielectric material layer is formed, wherein the second oxide dielectric material layer comprises a compound represented by Formula 1, Formula 1: AxOy wherein, in Formula 1, A is at least one selected from Al, Ti, Zr, Hf, Mg, Si, Ge, Y, Lu, La, and Sr, and 0<x≤2, and 0<y≤3 (Page 2, Col. 1, Materials and Methods).
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Maad does not explicitly teach wherein a work function of the graphene layer varies due to a dipole moment generated at an interface between the first oxide dielectric material layer and the second oxide dielectric material layer.
Kita teaches wherein a dipole moment is generated at an interface between the first oxide dielectric material layer and the second oxide dielectric material layer (Page 2, Col. 1, Para. 1).
Because Maad and Kita are both directed toward dielectric heterostructures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad and Kita in order to increase the electronic energy of the heterostructure device (Kita, Page 2, Col. 1, Para. 1).
Maad in view of Kita does not explicitly teach wherein a work function of the graphene layer varies.
Naghdi teaches wherein a work function of the graphene layer varies due to a dipole moment generated at an interface between the first oxide dielectric material layer and the second oxide dielectric material layer (Page 5, Col. 2, Para. 6).
Because Maad in view of Kita and Naghdi are directed toward graphene formed over heterostructures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad in view of Kita with the teachings of Naghdi in order to manipulate the graphene layer for the desired use, such as to increase the work function to increase hole injection efficiency for use as an anode (Naghdi, Page 2, Col. 1, Para. 3).
Maad in view of Kita and Naghdi teaches the graphene interconnect structure of claim 1, but does not explicitly teach wherein an areal oxygen density of the first oxide dielectric material layer is different from an areal oxygen density of the second oxide dielectric material layer. Maad does teach wherein the first oxide dielectric material is SiO2 and the second oxide dielectric material layer is HfO2, which have different oxygen vacancies (Maad, Page 2, Col. 1, Para. 1).
Kita teaches wherein an areal oxygen density of the first oxide dielectric material layer is different from an areal oxygen density of the second oxide dielectric material layer (Page 1, Col. 2, Para. 3).
Because Maad and Kita are both directed toward dielectric heterostructures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Maad and Kita in order to form a dipole to increase the electronic energy of the heterostructure device (Kita, Page 2, Col. 1, Para. 1).
Maad in view of Kita and Naghdi does not explicitly teach directly growing the graphene layer on a surface of the second oxide dielectric material layer.
Zhu teaches growing a graphene layer via CVD directly on the surface of a dielectric material layer (Page 9, Col. 1).
Because Maad in view of Kita and Naghdi and Zhu are both directed toward CVD graphene growth, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad and Zhu to include wherein the graphene layer is directly grown on a surface of the second oxide dielectric material layer in order to simplify manufacturing by removal of a graphene layer transfer procedure (Zhu, Page 8, Col. 1).
Regarding claim 17, Maad in view of Kita, Naghdi, and Zhu teaches the method of claim 15 wherein the forming of the second oxide dielectric material by ALD uses a precursor, and the precursor comprises Hf[N(CH3)2]4 (Maad, Page 2, Col. 1, Materials and Methods).
Regarding claim 18, Maad in view of Kita, Naghdi, and Zhu teaches the method of claim 15, wherein the second oxide dielectric material layer comprises HfO2 (Maad, Page 1, Col. 1).
Regarding claim 19, Maad in view of Kita, Naghdi, and Zhu teaches the method of claim 15, wherein a thickness of the second oxide dielectric material layer is in a range of about 0.3 nm to about 5 nm (Maad, Page 2, Col. 1, Materials and Methods).
Regarding claim 22, Maad in view of Kita, Naghdi, and Zhu teaches the graphene interconnect structure of claim 21, wherein the graphene layer comprises 1 to 7 layers (Zhu, Page 8, Col. 2, Para. 2).
Regarding claim 27, Maad in view of Kita, Naghdi, and Zhu teaches the graphene interconnect structure of claim 23 wherein the graphene layer is directly on a surface of the second oxide dielectric layer (20, Page 2, Col. 1, Materials and Methods), but does not explicitly teach wherein the graphene layer comprises 1 to 7 layers. Maad teaches wherein the graphene layer is single-layer (Page 2, Col. 2, Results and Discussion).
Zhu teaches wherein the graphene layer can be a monolayer, bilayer, or a few layers (Page 8, Col. 2, Para. 2).
Because Maad in view of Kita, Naghdi, and Zhu are both directed toward CVD growth of graphene, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad and Zhu in order to improve layer coverage (Page 8, Col. 2, Para. 2).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Maad in view of Kita, Naghdi, and Zhu, as applied to claim 15 above, and further in view of Gates.
Regarding claim 16, Maad in view of Kita, Naghdi, and Zhu teaches the method of claim 15, but does not explicitly teach wherein the first oxide dielectric material layer comprises at least one of an SiCOH material, porous SiO2, SiO2 doped with fluorine, and amorphous boron nitride.
Gates teaches use of a first oxide dielectric material layer comprising a SiCOH material ([0012]).
Because Maad in view of Kita, Naghdi, and Zhu and Gates are both directed toward low-K dielectric materials, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad in view of Kita, Naghdi, and Zhu and of Gates to include wherein the first oxide dielectric material comprises a SiCOH material in order to achieve thermal stability in the final device with an ultra-low-K material (Gates, [0003]).
Additionally, Maad in view of Kita, Naghdi, Zhu, and Gates teaches use of low-K materials with dielectric constant lower than that of SiO2 in order to improve switching performance of devices with small dimensions (Gates, [0003]). The specification of the instant application lists multiple low-K dielectrics without a teaching of criticality of any of the oxide dielectric materials listed. The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. In this case, SiCOH is a known low-k oxide dielectric; therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to choose an appropriate low-K material, such as SiCOH, for the method of manufacturing the graphene interconnect structure of claim 15 in order to provide improved performance in the device. See MPEP 2144.06.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Maad in view of Kita, Naghdi, and Zhu, as applied to claim 15 above, and further in view of Rummeli et al. (Direct Low-Temperature Nanographene CVD Synthesis over a Dielectric Insulator, ACS Nano, Vol. 4), herein referred to as Rummeli.
Regarding claim 20, Maad in view of Kita, Naghdi, and Zhu teaches the method of claim 15 but does not explicitly teach wherein in the directly growing the graphene layer, the CVD is performed at a temperature in a range of about 250 C to about 700 C.
Rummeli teaches wherein in the directly growing the graphene layer, the CVD is performed at a temperature in a range of about 250 C to about 700 C (Page 1, Col. 1).
Because Maad in view of Kita, Naghdi, and Zhu and Rummeli are directed toward direct growth of graphene on dielectric materials, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad in view of Kita, Naghdi, and Zhu and of Rummeli in order to maintain the mechanical integrity of low-K dielectrics (Page 1, Col. 1).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Maad in view of Kita, Naghdi, and Zhu, as applied to claim 15 above, and further in view of Ueno.
Regarding claim 21, Maad in view of Kita, Naghdi, and Zhu teaches the method of claim 15, but does not explicitly teach wherein a grain size of the graphene layer is in a range of about 10 nm to about 1 um.
Ueno teaches wherein grain sizes of graphene range between several tens of nanometers and several microns (Page 3, Col. 1, Experimental Procedure).
Because Maad in view of Kita, Naghdi, and Zhu and Ueno are both directed toward 2D graphene, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maad Kita, Naghdi, and and Ueno to control the size of the graphene grains to achieve uniformity and low resistivity (Ueno, Page 5, Effects of Br intercalation of CVD-MLG films on sheet resistance).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812