DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1, 2, 7-9, 11-13, is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Kellar et al., US 2003/0157782 A1.
Claims 1, 11. Kellar et al., disclose a device (such as the one in fig. 3), comprising:
-a first semiconductor-die (item 310) comprising a first overlap region (as a chip-on-chip structure) which comprises a first array of metallic contacts (item 106); and
-a second semiconductor die (item 320) comprising a second overlap region (as a chip-on-chip structure) which comprises a second array of metallic contacts (item 106);
-wherein the first overlap region and the second overlap region are overlapped and bonded together with the first array of metallic contacts aligned to the second array of metallic contacts, and with the first semiconductor die and the second semiconductor die disposed laterally adjacent to each other (this limitation would read through [0025] wherein is disclosed for example 4-wafer vertical stack 300 shown in FIG. 3, each of the silicon (Si) wafers 310, 320, 330 and 340 contains a respective active device layer 312, 322, 332 and 342 supporting one or more active IC devices (not shown). Wafer #1 310 and wafer #2 320 may be aligned and bonded via a metal bonding layer 106 deposited on opposing surfaces of the wafers #1 310 and #2 320 at designated bonding areas to establish electrical connections between active IC devices on adjacent wafers 310 and 320 and to bond the adjacent wafers 310 and 320, while maintaining electrical isolation between bonding areas via an ILD layer 108. Wafer #3 330 may then be aligned and bonded on the top surface of wafer #2 320, via vertical vias 324. Wafer #4 340 may be aligned and bonded on the top surface of wafer #3 330, via the same metal bonding layer 106 deposited on opposing surfaces of the wafers #3 330 and #4 340 at designated bonding areas to establish electrical connections between active IC devices on adjacent wafers 330 and 340 and to concurrently bond the adjacent wafers 330 and 340, while maintaining electrical isolation between bonding areas via an ILD layer 108).
Claim 2. Kellar et al., disclose the device of claim 1, wherein: the first array of metallic contacts comprises a first array of copper posts disposed in a first insulating layer; and the second array of metallic contacts comprises a second array of copper posts disposed in a second insulating layer (this limitation would read through [0029] wherein is disclosed for example the copper metal bonding layer 106 across the adjacent wafers (210 and 220 shown in FIG. 2, or 310, 320, 330 and 340 shown in FIG. 3).
Claim 7. Kellar et al., disclose the device of claim 1, wherein: the first array of metallic contacts are disposed in a first level of a first back-end-of-line structure of the first semiconductor die; and the second array of metallic contacts are disposed in a first level of a second back-end-of- line structure of the second semiconductor die (this limitation would read through [0025] wherein is disclosed for example 4-wafer vertical stack 300 shown in FIG. 3, each of the silicon (Si) wafers 310, 320, 330 and 340 contains a respective active device layer 312, 322, 332 and 342 supporting one or more active IC devices (not shown). Wafer #1 310 and wafer #2 320 may be aligned and bonded via a metal bonding layer 106 deposited on opposing surfaces of the wafers #1 310 and #2 320 at designated bonding areas to establish electrical connections between active IC devices on adjacent wafers 310 and 320 and to bond the adjacent wafers 310 and 320, while maintaining electrical isolation between bonding areas via an ILD layer 108. Wafer #3 330 may then be aligned and bonded on the top surface of wafer #2 320, via vertical vias 324. Wafer #4 340 may be aligned and bonded on the top surface of wafer #3 330, via the same metal bonding layer 106 deposited on opposing surfaces of the wafers #3 330 and #4 340 at designated bonding areas to establish electrical connections between active IC devices on adjacent wafers 330 and 340 and to concurrently bond the adjacent wafers 330 and 340, while maintaining electrical isolation between bonding areas via an ILD layer 108).
Claim 8. Kellar et al., disclose the device of claim 1, wherein the first array of metallic contacts and second array of metallic contacts are bonded together to form an array of die-to-die interconnects that enable input/output communication between the first semiconductor die and the second semiconductor die (this limitation would read through [0006] wherein is disclosed for example, when several semiconductor chips are mounted and interconnected on a common substrate through very high-density interconnects, higher silicon packaging density and shorter chip-to-chip interconnections can be achieved).
Claim 9. Kellar et al., disclose the device of claim 1, wherein at least one of the first overlap region of the first semiconductor die and the second overlap region of the second semiconductor die comprises one or more structural alignment features which facilitate lateral self-alignment of the first overlap region and the second overlap region when the first overlap region and the second overlap region are overlapped and bonded together (this limitation would read through [0029] wherein is disclosed for example, if the copper (Cu) metal bonding layer 106 is not pliable enough or the variability of the dielectric recess process is too great lo allow for more bonding pads to make direct contact, the use of a more pliable, self-leveling dielectric material may advantageously allow for better contact between the adjacent wafers (210 and 220 shown in FIG. 2, or 310, 320, 330 and 340 shown in FIG. 3) during the bonding process).
Claim 12. Kellar et al., disclose the device of claim 11, further comprising a third semiconductor die comprising a third array of metallic contacts, wherein the third semiconductor die is bonded to the first overlap region of the first semiconductor die with the third array of metallic contacts aligned to at least a portion of the first array of metallic contacts, and with the first semiconductor die, the second semiconductor die, and the third semiconductor die disposed laterally adjacent to each other (this limitation would read through [0025] wherein is disclosed for example 4-wafer vertical stack 300 shown in FIG. 3, each of the silicon (Si) wafers 310, 320, 330 and 340 contains a respective active device layer 312, 322, 332 and 342 supporting one or more active IC devices (not shown). Wafer #1 310 and wafer #2 320 may be aligned and bonded via a metal bonding layer 106 deposited on opposing surfaces of the wafers #1 310 and #2 320 at designated bonding areas to establish electrical connections between active IC devices on adjacent wafers 310 and 320 and to bond the adjacent wafers 310 and 320, while maintaining electrical isolation between bonding areas via an ILD layer 108. Wafer #3 330 may then be aligned and bonded on the top surface of wafer #2 320, via vertical vias 324. Wafer #4 340 may be aligned and bonded on the top surface of wafer #3 330, via the same metal bonding layer 106 deposited on opposing surfaces of the wafers #3 330 and #4 340 at designated bonding areas to establish electrical connections between active IC devices on adjacent wafers 330 and 340 and to concurrently bond the adjacent wafers 330 and 340, while maintaining electrical isolation between bonding areas via an ILD layer 108).
Claim 13. Kellar et al., disclose the device of claim 11, wherein: the first semiconductor die comprises a second overlap region which comprises a second array of metallic contacts; the device further comprises a third semiconductor die comprising a third array of metallic contacts; and the third semiconductor die is bonded to the second overlap region of the first semiconductor die with the third array of metallic contacts aligned to at least a portion of the second array of metallic contacts, and with the first semiconductor die, the second semiconductor die, and the third semiconductor die disposed laterally adjacent to each other (this limitation would read through [0025] wherein is disclosed for example 4-wafer vertical stack 300 shown in FIG. 3, each of the silicon (Si) wafers 310, 320, 330 and 340 contains a respective active device layer 312, 322, 332 and 342 supporting one or more active IC devices (not shown). Wafer #1 310 and wafer #2 320 may be aligned and bonded via a metal bonding layer 106 deposited on opposing surfaces of the wafers #1 310 and #2 320 at designated bonding areas to establish electrical connections between active IC devices on adjacent wafers 310 and 320 and to bond the adjacent wafers 310 and 320, while maintaining electrical isolation between bonding areas via an ILD layer 108. Wafer #3 330 may then be aligned and bonded on the top surface of wafer #2 320, via vertical vias 324. Wafer #4 340 may be aligned and bonded on the top surface of wafer #3 330, via the same metal bonding layer 106 deposited on opposing surfaces of the wafers #3 330 and #4 340 at designated bonding areas to establish electrical connections between active IC devices on adjacent wafers 330 and 340 and to concurrently bond the adjacent wafers 330 and 340, while maintaining electrical isolation between bonding areas via an ILD layer 108).
Allowable Subject Matter
4. Claims 3-6, 10, 12-13, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(A) Claim 3 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the first overlap region and the second overlap region are bonded together by at least one of: thermal compression bonding of the first array of copper posts and the second array of copper posts; and covalent bonding of the first insulating layer and the second insulating layer.
(B) Claim 4 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein: the first overlap region of the first semiconductor die is defined by an etched region of a backside of the first semiconductor die; and the second overlap region of the second semiconductor die is defined by an etched region of a frontside of the second semiconductor die.
(C) Claim 5 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the first overlap region has a first footprint and the second overlap region has a second footprint which is substantially a same size as the first footprint.
(D) Claim 6 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the first overlap region has a first footprint and the second overlap region has a second footprint which is smaller than the first footprint.
(E) Claim 10 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the one or more structural alignment features comprises a tongue structure formed in the first overlap region and a notch structure formed in the second overlap region, wherein the tongue structure is placed into the notch structure to achieve lateral self-alignment of the first overlap region and the second overlap region.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899