DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see section II. Election/Restrictions of Request for Reconsideration – After Non-Final Rejection, filed 04/27/2026, with respect to claims 7,10-16 and 31 have been fully considered and are persuasive. The Restriction of claims 7,10-16 and 31 has been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-9 and 30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2022/0181458 A1, hereinafter Kim ‘458).
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With respect to Claim 1 Kim ‘458 discloses a semiconductor memory device (Fig 1-17) comprising:
a first gate stack structure (ST1, Fig 6, Para [0052]) including first interlayer insulating layers (IL1, Fig 6, Para [0052]) and first conductive layers (EL in ST1, Fig 6, Para [0052], hereinafter FCL), which are alternately stacked in a vertical direction (D3 as shown in Fig 6 and alternative stack in D3 is disclosed in Para [0052]);
a dummy vertical channel (DS, Fig 6, Para [0072]) penetrating the first gate stack structure (ST1);
lower vertical channels (VS in ST1, Fig 6, Para [0057], hereinafter LVC) penetrating the first gate stack structure (ST1) at both sides of the dummy vertical channel (DS)(Fig 6 discloses VS on either side of DS);
a second gate stack structure (ST2, Fig 6, Para [0052]) including second interlayer insulating layers (IL2, Fig 6, Para [0052]) and second conductive layers (EL in ST2, Fig 6, Para [0052], hereinafter SCL), which are alternately stacked in the vertical direction (D3 as shown in Fig 6 and alternative stack in D3 is disclosed in Para [0052]) on the first gate stack structure(ST1)(orientation disclosed in Fig 6);
a first select line isolation structure (SC1, Fig 6, Para [0071]) partially penetrating the second gate stack structure (ST2)(partial penetration disclosed in Fig 6);
upper vertical channels (VS in ST2, Fig 6, Para [0057]), hereinafter UVC) directly connected (disclosed in Fig 6 and disclosed in Para [0092]) to the lower vertical channels (LVC); and
a second select line isolation structure (SC2, Fig 6, Para [0071]) overlapping with the dummy vertical channel (DS) in the vertical direction (D3)(SC2 overlapping DS disclosed in Fig 6 and Fig 7 and Para [0072]), the second select line isolation structure (SC2) partially penetrating the second gate stack structure (ST2) (partial penetration disclosed in Fig 6)
wherein a length of the first select line isolation structure (SC1) is different from a length of the second select line isolation structure (SC2) in the vertical direction (D3) (annotated Fig 6 of Kim ‘458 discloses a length of SC1 that is different than a length of SC2 in the vertical direction).
With respect to Claim 2 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘458 further discloses wherein the first select line isolation structure (SC1) is disposed between the upper vertical channels (UVC) at both sides of the second select line isolation structure (SC2)(Fig 5 and Fig 6 and Para [0072] disclose SC1 is disposed between UVC and Fig 5 discloses SC1 at both sides of SC2).
With respect to Claim 3 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘458 further discloses wherein the first select line isolation structure (SC1) does not overlap with the dummy vertical channel (DS)(Fig 6 discloses SC1 does not overlap with DS).
With respect to Claim 4 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘453 further discloses wherein a width (a width within SC2) of the second select line isolation structure (SC2) doesn't exceed a width (a width within SC1) of the first select line isolation structure (SC1)(a width exists in SC1 that is equal to or less than an existing width in SC2).
With respect to Claim 5 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘453 further discloses wherein a first width (a first width within SC1) of the first select line isolation structure (SC1) is narrower than a second width (a second width within SC2) of the second select line isolation structure (SC2) (a width exists in SC1 that is narrower than an existing width in SC2).
With respect to Claim 6 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 5, and Kim ‘458 further discloses wherein a length (a length within SC2) of the second select line isolation structure (SC2) is longer than a length (a length within SC1) of the first select line isolation structure (SC1)(a length exists in SC2 that is longer than an existing length in SC1).
With respect to Claim 8 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘453 further discloses wherein at least one of the second conductive layers (one of SCL as disclosed in annotated Fig 6 of Kim ‘453) of the second gate stack structure (ST2) extends between the first select line isolation structure (SC1) and the first gate stack structure (ST1)(annotated Fig 6 of Kim ‘453 discloses a SCL extending (in direction D3) between SC1 and ST1).
With respect to Claim 9 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘453 further discloses wherein at least one of the second conductive layers (one of SCL as disclosed in annotated Fig 6 of Kim ‘453) of the second gate stack structure (ST2) is between the second select line isolation structure (SC2) and the dummy vertical channel (DS)(annotated Fig 6 discloses at least one of SCL between SC2 and DS in the D3 direction).
With respect to Claim 30 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘458 further discloses wherein a length (a length within SC1) in the vertical direction (D3 as shown in Fig 6) of the first select line isolation structure (SC1) is different from a length (a length within SC2) in the vertical direction (D3 as shown in Fig 6) of the second select line isolation structure(SC2) (a length exists in SC1 that is different from an existing length in SC2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘458 in view of Liu et al. (US 2020/0135751 A1, hereinafter Liu ‘751), in view of the following arguments.
With respect to Claim 10 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘458 further discloses wherein the dummy vertical channel (DS) partially penetrates (DS partially penetrating ST1 disclosed in annotated Fig 6 of Kim ‘458) the first gate stack structure (ST1).
But Kim ‘458 fails to explicitly disclose further comprising an etch stop layer disposed on the dummy vertical channel.
Nevertheless, in a related endeavor (Fig 5 of Liu ‘751), Liu ‘751 teaches an etch stop layer (42, Fig 5 of Liu ‘751, Para [0044]) disposed on the vertical channel (24/40, Fig 5 of Liu ‘751, Para [0042]) (42 disposed on 24/40 disclosed in Fig 5 of Liu ‘751 and Para [0044]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Liu ‘751’s teaching of an etch stop layer disposed on the vertical channel and directly on the vertical channel into Kim ‘458’s device. Kim ‘458 discloses a memory device with channel structures in upper and lower memory stacks. Liu ‘751 also teaches a memory device with channel structures in upper and lower memory stacks and further teaches an etch stop layer on the lower channel structures. The ordinary artisan would have been motivated, then, to modify Kim ‘458 in the manner set forth above, at least, because the use of an etch stop layer over the lower channel structures will protect the structures during the etching formation of the upper channels and isolation structures.
As incorporated, the etch stop layer (42) taught by Liu ‘751 would be used over the dummy vertical channel (DS) of Kim ‘458.
Allowable Subject Matter
Claims 11-16 and 31 are allowed.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 11: Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature, “a second select line isolation structure extending through the second gate stack structure and in direct contact with the etch stop layer”, along with the rest of the limitations of the said claim.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 7: Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature, “the second select line isolation structure extends to completely penetrate the second gate stack structure”, along with the rest of the limitations of the said claim.
Closest prior art of record Kim et al. (US 2022/0181458 A1) teaches “a semiconductor memory device comprising: a first gate stack structure including first interlayer insulating layers and first conductive layers, which are alternately stacked in a vertical direction; a dummy vertical channel penetrating the first gate stack structure; lower vertical channels penetrating the first gate stack structure at both sides of the dummy vertical channel; a second gate stack structure including second interlayer insulating layers and second conductive layers, which are alternately stacked in the vertical direction on the first gate stack structure; a first select line isolation structure partially penetrating the second gate stack structure; upper vertical channels directly connected to the lower vertical channels; and a second select line isolation structure overlapping with the dummy vertical channel in the vertical direction, the second select line isolation structure partially penetrating the second gate stack structure, wherein a length of the first select line isolation structure is different from a length of the second select line isolation structure in the vertical direction”. However Kim ‘458 fails to disclose the second isolation structure extends through or completely penetrates the second gate stack structure.
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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