DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 7, 10-16 and 31, read on unelected Device Embodiment 2, which shows the isolation structure/Trench T extends through the entire height of the upper memory layer and ends at a preliminary layer 217 that was formed prior to the creation of the upper memory layer, this is a longer length trench than used in Method Embodiment 1 and the layer 271 (etch stop layer) is not present in Method Embodiment 1.
Specifically, Claim 7 states “wherein the second select line isolation structure extends to completely penetrate the second gate stack” and Claim 10 states “further comprising an etch stop layer…”. Claim 11 states, “…and a second select line isolation structure extending through the second gate stack structure and being in direct contact with the etch stop layer.” Claims 12-16 and 31 are dependent on Claim 11. Therefore claims 7, 10-16 and 31 are withdrawn from further consideration, as being drawn to a nonelected species.
Response to Arguments
Applicant’s arguments, see section VI of Request for Reconsideration – After Non-Final, filed 10/30/2025, with respect to the rejections of claims 1-9 under 35 U.S.C. § 102(a)(1) and with respect to the rejections of claims 11-16 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground of rejection is made in view of a newly found prior art reference, which teaches the limitations of “and a second select line isolation structure extending through the second gate stack structure and being in direct contact with the etch stop layer” as described below
Drawings
Amendment of Claim 9 made in Applicant’s arguments - Request for Reconsideration – After Non-Final, filed 10/30/2025 overcome prior objections made in the Non-Final mailed 07/31/2025, therefore those objections are withdrawn.
Claim Rejections - 35 USC § 112
Amendment of Claim 9 made in Applicant’s arguments - Request for Reconsideration – After Non-Final, filed 10/30/2025 overcome prior 35 U.S.C. § 112 rejections made in the Non-Final mailed 07/31/2025, therefore those objections are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-9 and 30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2022/0181458 A1, hereinafter Kim ‘458).
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With respect to Claim 1 Kim ‘458 discloses a semiconductor memory device (Fig 1-17) comprising:
a first gate stack structure (ST1, Fig 6, Para [0052]) including first interlayer insulating layers (IL1, Fig 6, Para [0052]) and first conductive layers (EL in ST1, Fig 6, Para [0052], hereinafter FCL), which are alternately stacked in a vertical direction (D3 as shown in Fig 6 and alternative stack in D3 is disclosed in Para [0052]);
a dummy vertical channel (DS, Fig 6, Para [0072]) penetrating the first gate stack structure (ST1);
lower vertical channels (VS in ST1, Fig 6, Para [0057], hereinafter LVC) penetrating the first gate stack structure (ST1) at both sides of the dummy vertical channel (DS)(Fig 6 discloses VS on either side of DS);
a second gate stack structure (ST2, Fig 6, Para [0052]) including second interlayer insulating layers (IL2, Fig 6, Para [0052]) and second conductive layers (EL in ST2, Fig 6, Para [0052], hereinafter SCL), which are alternately stacked in the vertical direction (D3 as shown in Fig 6 and alternative stack in D3 is disclosed in Para [0052]) on the first gate stack structure(ST1)(orientation disclosed in Fig 6);
a first select line isolation structure (SC1, Fig 6, Para [0071]) partially penetrating the second gate stack structure (ST2)(partial penetration disclosed in Fig 6);
upper vertical channels (VS in ST2, Fig 6, Para [0057]), hereinafter UVC) directly connected (disclosed in Fig 6 and disclosed in Para [0092]) to the lower vertical channels (LVC); and
a second select line isolation structure (SC2, Fig 6, Para [0071]) overlapping with the dummy vertical channel (DS) in the vertical direction (D3)(SC2 overlapping DS disclosed in Fig 6 and Fig 7 and Para [0072]), the second select line isolation structure (SC2) partially penetrating the second gate stack structure (ST2) (partial penetration disclosed in Fig 6).
With respect to Claim 2 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘458 further discloses wherein the first select line isolation structure (SC1) is disposed between the upper vertical channels (UVC) at both sides of the second select line isolation structure (SC2)(Fig 5 and Fig 6 and Para [0072] disclose SC1 is disposed between UVC and Fig 5 discloses SC1 at both sides of SC2).
With respect to Claim 3 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘458 further discloses wherein the first select line isolation structure (SC1) does not overlap with the dummy vertical channel (DS)(Fig 6 discloses SC1 does not overlap with DS).
With respect to Claim 4 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘453 further discloses wherein a width (a width within SC2) of the second select line isolation structure (SC2) doesn't exceed a width (a width within SC1) of the first select line isolation structure (SC1)(a width exists in SC1 that is equal to or less than an existing width in SC2).
With respect to Claim 5 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘453 further discloses wherein a first width (a first width within SC1) of the first select line isolation structure (SC1) is narrower than a second width (a second width within SC2) of the second select line isolation structure (SC2) (a width exists in SC1 that is narrower than an existing width in SC2).
With respect to Claim 6 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 5, and Kim ‘458 further discloses wherein a length (a length within SC2) of the second select line isolation structure (SC2) is longer than a length (a length within SC1) of the first select line isolation structure (SC1)(a length exists in SC2 that is longer than an existing length in SC1).
With respect to Claim 8 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘453 further discloses wherein at least one of the second conductive layers (one of SCL as disclosed in annotated Fig 6 of Kim ‘453) of the second gate stack structure (ST2) extends between the first select line isolation structure (SC1) and the first gate stack structure (ST1)(annotated Fig 6 of Kim ‘453 discloses a SCL extending (in direction D3) between SC1 and ST1).
With respect to Claim 9 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘453 further discloses wherein at least one of the second conductive layers (one of SCL as disclosed in annotated Fig 6 of Kim ‘453) of the second gate stack structure (ST2) is between the second select line isolation structure (SC2) and the dummy vertical channel (DS)(annotated Fig 6 discloses at least one of SCL between SC2 and DS in the D3 direction).
With respect to Claim 30 Kim ‘458 discloses all limitations of the semiconductor memory device of claim 1, and Kim ‘458 further discloses wherein a length (a length within SC1) in the vertical direction (D3 as shown in Fig 6) of the first select line isolation structure (SC1) is different from a length (a length within SC2) in the vertical direction (D3 as shown in Fig 6) of the second select line isolation structure(SC2) (a length exists in SC1 that is different from an existing length in SC2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898