DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/18/2026 has been entered.
Response to Amendment
The amendment with respect to claim(s) 1, and 7 filed on 6/14/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 2-3, 5, and 8 have been considered. Claim(s) 4, and 6 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 7-11, filed 01/29/2026, with respect to the rejection(s) of claim(s) 1-8 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of SDRULLA.
Regarding Independent Claim(s) 1, and 7. The Applicant argues (see Remarks, page 9) that none of the cited references, either alone or in combination, disclose or suggest the amended features to claims 1 and 7, now recites, “a semiconductor device, comprising: wherein the first portion and the second portion being laterally continuous to each other; wherein the first portion…second uniform thickness…connection portion connects…monotonically thickening the gate insulating film…to the second uniform thickness.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior art SDRULLA teaches in Figures 5A, and 5B that the vertical power MOSFET structure comprising; the gate oxide layer, 28 and the terraced dielectric layer, 29 with different thickness extends over each of the drift regions [Col. 7, Lines 25-50], and this features thus improve the safe operating area (SOA) characteristics of the silicon-carbide (SiC) vertical power MOSFET devices.
Regarding Claim(s) 2-3, 5, and 8. The dependent claims 2-3, 5, and 8 follow similar arguments as Claim(s) 1, and 7, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuichi Harada et al, (hereinafter HARADA), US 20170207301 A1 (prior art used in the previous Office Action filed on 10/31/2025), in view of Sudrula Dumitru et al, (hereinafter DUMITRU), JP 2016519428A (prior art used in the previous Office Action filed on 10/31/2025), and Dumitru Sdrulla et al, (hereinafter SDRULLA), US 8436367 B1.
Regarding Claim 1, HARADA teaches, a semiconductor device (Fig. 1, 100), comprising:
a semiconductor substrate (Fig. 2, 10) having an upper surface (Fig. 2, 14, front surface) and a lower surface (Fig. 2, 16, back surface), the semiconductor substrate (Fig. 2, 10) including:
a drift layer (Fig. 2, 12) of a first conductivity type (n-type drift layer, 12, [0046]) on a side of the upper surface (Fig. 2, 14, front surface) and a drain layer (Fig. 2, 62, drain electrode) on a side of the lower surface (Fig. 2, 16, back surface),
a first well region (Fig. 2, 22, annotated Figure 2) and a second well region (Fig. 2, 22, annotated Figure 2) selectively formed in the drift layer (Fig. 2, 12), each being of a second conductivity type (p-type well region, 22, [0046]) that is opposite to the first conductivity type (n-type drift layer, 12, [0046]) and extending downwardly (annotated Figure 2) from the upper surface (Fig. 2, 14, front surface) of the semiconductor substrate (Fig. 2, 10) up to a first depth (annotated Figure 2) within the drift layer (Fig. 2, 12), the first well region (Fig. 2, 22, annotated Figure 2) and the second well region (Fig. 2, 22, annotated Figure 2) being arranged side by side (annotated Figure 2) with a portion of the drift layer (annotated Figure 2) sandwiched therebetween at the upper surface (Fig. 2, 14, front surface) of the semiconductor substrate (Fig. 2, 10),
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a first source region (Fig. 2. 26, annotated Figure 2) of the first conductivity type (n-type source region, 26, [0046]) selectively formed in the first well region (Fig. 2, 22, annotated Figure 2) so as to extend downwardly (annotated Figure 2) from the upper surface (Fig. 2, 14, front surface) of the semiconductor substrate (Fig. 2, 10) up to a second prescribed depth (annotated Figure 2) within the first well region (Fig. 2, 22, annotated Figure 2), and
a second source region (Fig. 2. 26, annotated Figure 2) of the first conductivity type (n-type source region, 26, [0046]) selectively formed in the second well region (Fig. 2, 22, annotated Figure 2) so as to extend downwardly (annotated Figure 2) from the upper surface (Fig. 2, 14, front surface) of the semiconductor substrate (Fig. 2, 10) up to the second depth (annotated Figure 2) within the second well region (Fig. 2, 22, annotated Figure 2);
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HARADA does not explicitly disclose a semiconductor device comprising: a gate insulating film having a first portion and a second portion arranged side by side so as to be laterally continuous to each other, the first portion being thinner than the second portion and arranged on, and in direct contact with, the first well region and the first source region, the second portion being arranged on, and in direct contact with, the second well region and the second source region; and a gate electrode disposed on the gate insulating film that includes the first and second portion.
DUMITRU teaches a semiconductor device (Fig. 24, power MOSFET semiconductor device, [0001]) comprising: a gate insulating film (Fig. 24, 28/28a, gate oxide layer, [0039-0040]) having a first portion (Fig. 24, 28a, gate oxide layer, [0039-0040]) and a second portion (Fig. 24, 28, gate oxide layer, [0039-0040]) arranged side by side so as to be laterally continuous to each other (Fig. 24, 28/28a, gate oxide layer, [0039-0040]), the first portion being thinner than the second portion (Fig. 24, a gate oxide layer, 28/28a of varying thickness, [0039-0040]) and arranged on, and in direct contact with, the first well region (Fig. 10, 25, P-well/body region is P-type, [0013], [0033]) and the first source region (Fig. 10, 26, heavily doped source region, [0037]), the second portion being arranged on, and in direct contact with, the second well region (Fig. 10, 25, P-well/body region is P-type, [0013], [0033]) and the second source region (Fig. 10, 26, lightly doped source region, [0037]); and a gate electrode (Fig. 24, 32, gate conductor, [0039]) disposed on the gate insulating film (Fig. 24, 28/28a, gate oxide layer, [0039-0040]) that includes the first (Fig. 24, 28a, gate oxide layer, [0039-0040]) and second portion (Fig. 24, 28, gate oxide layer, [0039-0040]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HARADA to incorporate the teachings of DUMITRU, such that a semiconductor device comprising: a gate insulating film having a first portion and a second portion arranged side by side so as to be laterally continuous to each other, the first portion being thinner than the second portion and arranged on, and in direct contact with, the first well region and the first source region, the second portion being arranged on, and in direct contact with, the second well region and the second source region; and a gate electrode disposed on the gate insulating film that includes the first and second portion, so that the above arrangement of a power MOSFET semiconductor devices that operates with the entire safe operating area (SOA) by maximizing allowable current and maximum blocking voltage during the on-state (DUMITRU, [0001]).
HARADA as modified by DUMITRU does not explicitly disclose a semiconductor device comprising: wherein the first portion has a first uniform thickness and the second portion has a second uniform thickness greater than the first uniform thickness so that a connection portion connects the first portion and the second portion is step-shaped or slope-shaped, stepwisely or monotonically thickening the gate insulating film from the first uniform thickness to the second uniform thickness.
SDRULLA teaches a semiconductor device (Fig. 5B, vertical SiC Power MOSFET, [Col. 2, Lines, 65-67]) comprising: wherein the first portion (Fig. 5B, 28, gate oxide areas) has a first uniform thickness (annotated Figure 5B) and the second portion (Fig. 5B, 29, terraced dielectric layer) has a second uniform thickness (annotated Figure 5B) greater ([Col. 7, Lines 40-50]) than the first uniform thickness (annotated Figure 5B) so that a connection portion (annotated Figure 5B) connects the first portion (annotated Figure 5B) and the second portion (annotated Figure 5B) is step-shaped or slope-shaped (annotated Figure 5B), stepwisely or monotonically thickening the gate insulating film (Fig. 5B, 28/29, gate oxide areas/terraced dielectric layer) from the first uniform thickness (annotated Figure 5B) to the second uniform thickness (annotated Figure 5B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HARADA as modified by DUMITRU to incorporate the teachings of SDRULLA, such that a semiconductor device comprising: wherein the first portion has a first uniform thickness and the second portion has a second uniform thickness greater than the first uniform thickness so that a connection portion connects the first portion and the second portion is step-shaped or slope-shaped, stepwisely or monotonically thickening the gate insulating film from the first uniform thickness to the second uniform thickness, so that these features thus improve the safe operating area (SOA) characteristics of the silicon-carbide (SiC) vertical power MOSFET devices (SDRULLA, [Col. 1, Lines 15-25]).
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Regarding Claim 2, HARADA as modified by DUMITRU and SDRULLA teaches, the semiconductor device according to claim 1.
HARADA further teaches the semiconductor device (Fig. 1, 100), wherein the first portion (Fig. 2, 43, titanium carbide region, annotated Figure 2) and the second portion (Fig. 2, 42, titanium film, annotated Figure 2) of the gate insulating film (Fig. 2, 32) are both on the portion of the drift layer (Fig. 2, 12) sandwiched (annotated Figure 2) by the first (Fig. 2, 22, annotated Figure 2) and second well regions (Fig. 2, 22, annotated Figure 2).
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Regarding Claim 3, HARADA as modified by DUMITRU and SDRULLA teaches, the semiconductor device according to claim 1.
HARADA further teaches the semiconductor device (Fig. 1, 100), wherein the second portion (Fig. 2, 42, titanium film, annotated Figure 2) of the gate insulating film (Fig. 2, 32) covers entirety of the portion of the drift layer (Fig. 2, 12) sandwiched (annotated Figure 2) by the first (Fig. 2, 22, annotated Figure 2) and second well regions (Fig. 2, 22, annotated Figure 2),
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Regarding Claim 7, HARADA teaches, a method for manufacturing (Figs. 6A-6F) a semiconductor device (Fig. 1, 100) in a semiconductor substrate (Figs. 2/6F, 10) having an upper surface (Figs. 2/6F, 14, front surface) and a lower surface (Figs. 2/6F 16, back surface) and including a drift layer (Figs. 2/6F, 12) of a first conductivity type (n-type drift layer, 12, [0046]) on a side of the upper surface (Fig. 2, 14, front surface) and a drain layer (Figs. 2/6F, 62, drain electrode) on a side of the lower surface (Figs. 2/6F, 16, back surface), the method (Figs. 6A-6F) comprising:
selectively forming (Figs. 6A-6F) well regions (Figs. 2/6F, 22, annotated Figure 2/6F) in the drift layer (Figs. 2/6F, 12) in the semiconductor substrate (Figs. 2/6F, 10) each being of a second conductivity type (p-type well region, 22, [0046]) that is opposite to the first conductivity type (n-type drift layer, 12, [0046]) and extending downwardly (annotated Figure 2/6F) from the upper surface (Figs. 2/6F, 14, front surface) of the semiconductor substrate (Figs. 2/6F, 10) up to a first depth (annotated Figure 2/6F) within the drift layer (Figs. 2/6F, 12);
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selectively forming (Figs. 6A-6F) source regions (Figs. 2/6F, 26, annotated Figure 2) in the well regions (Figs. 2/6F, annotated Figure 2), respectively, each being of the first conductivity type (n-type drift layer, 12, [0046]) and extending downwardly (annotated Figure 2/6F) from the upper surface (Figs. 2/6F, 14, front surface) of the semiconductor substrate (Figs. 2/6F, 10) up to a second depth (annotated Figure 2/6F) within the corresponding well regions (Figs. 2/6F, 22, annotated Figure 2/6F);
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forming (Figs. 6A-6F) a gate insulating film (Figs. 2/6F, 32) on the upper surface (Figs. 2/6F, 14, front surface) of the semiconductor substrate (Figs. 2/6F, 10), the gate insulating film (Figs. 2/6F, 32) having a first portion (Figs. 2/6F, 43, titanium carbide region, annotated Figure 2/6F) and a second portion (Figs. 2/6F, 42, titanium film, annotated Figure 2/6F) that are arranged laterally (annotated Figure 2/6F),
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forming (Figs. 6A-6F) a gate electrode (Figs. 2/6F, 34) on an upper surface (Figs. 2/6F, 14, front surface) of the gate insulating film (Figs. 2/6F, 32);
forming (Figs. 6A-6F) an interlayer insulating film (Fig. 6F, 36) so as to cover the gate electrode (Figs. 2/6F, 34);
forming (Figs. 6A-6F) a source electrode (Fig. 6F, 42/44, titanium film/metal layer, [0052]) on an upper surface (Figs. 2/6F, 14, front surface) of the interlayer insulating film (Fig. 6F, 36); and
forming (Figs. 6A-6F) a drain electrode (Figs. 2/6F, 62) on the lower surface (Figs. 2/6F, 16, back surface) of the semiconductor substrate (Figs. 2/6F, 10).
HARADA does not explicitly disclose a method of manufacturing of a semiconductor device, the method comprising: forming a gate insulating film on the upper surface of the semiconductor substrate, the gate insulating film having a first portion and a second portion that are arranged laterally, the first portion being thinner than the second portion; forming a gate electrode on an upper surface of the gate insulating film.
DUMITRU teaches a method of manufacturing of semiconductor device (Fig. 24, the methods and device structure for SiC power MOSFET semiconductor device, [0011]), the method comprising:
forming a gate insulating film (Fig. 24, 28/28a, gate oxide layer [0039-0040]) on the upper surface of the semiconductor substrate (Fig. 24, 21, SiC substrate), the gate insulating film having a first portion (Fig. 24, 28a, gate oxide layer, [0039-0040]) and a second portion (Fig. 24, 28, gate oxide layer, [0039-0040]) that are arranged laterally (Fig. 24, 28/28a, gate oxide layer, [0039-0040]), the first portion being thinner than the second portion (Fig. 24, a gate oxide layer, 28/28a of varying thickness, [0039-0040]); forming a gate electrode (Fig. 24, 32, gate conductor, [0039]) on an upper surface of the gate insulating film.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HARADA to incorporate the teachings of DUMITRU, such that a method of manufacturing of a semiconductor device, the method comprising: forming a gate insulating film on the upper surface of the semiconductor substrate, the gate insulating film having a first portion and a second portion that are arranged laterally, the first portion being thinner than the second portion; forming a gate electrode on an upper surface of the gate insulating film, so that the above arrangement of a power MOSFET semiconductor devices that operates with the entire safe operating area (SOA) by maximizing allowable current and maximum blocking voltage during the on-state (DUMITRU, [0001]).
HARADA as modified by DUMITRU does not explicitly disclose a semiconductor device comprising: forming a gate insulating film on the upper surface of the semiconductor substrate, the gate insulating film having a first portion and a second portion that are arranged laterally, the first portion being thinner than the second portion, the first portion and the second portion being laterally continuous to each other; wherein the first portion has a first uniform thickness and the second portion has a second uniform thickness greater than the first uniform thickness so that a connection portion connects the first portion and the second portion is step-shaped or slope-shaped, stepwisely or monotonically thickening the gate insulating film from the first uniform thickness to the second uniform thickness.
SDRULLA teaches a semiconductor device (Fig. 5B, vertical SiC Power MOSFET, [Col. 2, Lines, 65-67]) comprising: forming a gate insulating film (Fig. 5B, 28/29, gate oxide areas/terraced dielectric layer) on the upper surface of the semiconductor substrate (Fig. 5B, 21, crystalline SiC substrate), the gate insulating film (Fig. 5B, 28/29, gate oxide areas/terraced dielectric layer) having a first portion (Fig. 5B, 28, gate oxide areas) and a second portion (Fig. 5B, 29, terraced dielectric layer) that are arranged laterally (annotated Figure 5B), the first portion being thinner than the second portion (annotated Figure 5B), the first portion and the second portion being laterally continuous to each other (annotated Figure 5B); wherein the first portion (Fig. 5B, 28, gate oxide areas) has a first uniform thickness (annotated Figure 5B) and the second portion (Fig. 5B, 29, terraced dielectric layer) has a second uniform thickness (annotated Figure 5B) greater ([Col. 7, Lines 40-50]) than the first uniform thickness (annotated Figure 5B) so that a connection portion (annotated Figure 5B) connects the first portion (annotated Figure 5B) and the second portion (annotated Figure 5B) is step-shaped or slope-shaped (annotated Figure 5B), stepwisely or monotonically thickening the gate insulating film (Fig. 5B, 28/29, gate oxide areas/terraced dielectric layer) from the first uniform thickness (annotated Figure 5B) to the second uniform thickness (annotated Figure 5B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HARADA as modified by DUMITRU to incorporate the teachings of SDRULLA, such that a semiconductor device comprising: forming a gate insulating film on the upper surface of the semiconductor substrate, the gate insulating film having a first portion and a second portion that are arranged laterally, the first portion being thinner than the second portion, the first portion and the second portion being laterally continuous to each other; wherein the first portion has a first uniform thickness and the second portion has a second uniform thickness greater than the first uniform thickness so that a connection portion connects the first portion and the second portion is step-shaped or slope-shaped, stepwisely or monotonically thickening the gate insulating film from the first uniform thickness to the second uniform thickness, so that these features thus improve the safe operating area (SOA) characteristics of the silicon-carbide (SiC) vertical power MOSFET devices (SDRULLA, [Col. 1, Lines 15-25]).
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Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over HARADA, in view of DUMITRU, and SDRULLA as applied to Claim(s) 1-3, and 7 and further in view of Katsuyuki Torii, (hereinafter TORII), US 20070205442 A1 (prior art used in the previous Office Action filed on 10/31/2025).
Regarding Claim 5, HARADA as modified by DUMITRU and SDRULLA teaches, the semiconductor device according to claim 1.
DUMITRU further teaches, the semiconductor device (Fig. 24, power MOSFET semiconductor device, [0001]) wherein a film thickness of the second portion (Fig. 24, 28, gate oxide layer, [0039-0040]) of the gate insulating film and a film thickness of the first portion (Fig. 24, 28a, gate oxide layer, [0039-0040]) of the gate insulating film (Fig. 24, a gate oxide layer, 28/28a of varying thickness, [0039-0040]).
HARADA as modified by DUMITRU and SDRULLA does not explicitly disclose, the semiconductor device, wherein a film thickness of the second portion of the gate insulating film is 1.3 to 2 times a film thickness of the first portion of the gate insulating film.
TORII teaches the semiconductor device (Fig. 8, 60, [0046]), wherein a film thickness of the second portion (Fig. 10, 64b, gate insulating film) of the gate insulating (Fig. 10, 64, gate insulating film) film is 1.3 to 2 times (For example, the gate insulating film 64a is formed to have a thickness of about 1000 Å, and the gate insulating film 64b is formed to have a thickness of about 500 Å, [0104]) a film thickness of the first portion (Fig. 10, 64b, gate insulating film) of the gate insulating film (Fig. 10, 64, gate insulating film).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HARADA as modified by DUMITRU and SDRULLA to incorporate the teachings of TORII, such that the semiconductor device, wherein a film thickness of the second portion of the gate insulating film is 1.3 to 2 times a film thickness of the first portion of the gate insulating film, so that raise the threshold voltage and to optimize the current flowing in the semiconductor device (60) (TORII, [0104]).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over HARADA, in view of DUMITRU and SDRULLA as applied to Claim(s) 1-3, and 7, and further in view of Yoshihiro Yamaguchi et al, (hereinafter YAMAGUCHI), US 20090184352 A1 (prior art used in the previous Office Action filed on 10/31/2025).
Regarding Claim 8, HARADA as modified by DUMITRU and SDRULLA teaches, the method according to claim 7.
HARADA further teaches the method (Figs. 6A-6F) wherein the forming (Figs. 6A-6F) the gate insulating film includes:
forming (Figs. 6A-6F) an insulating film (Figs. 2/6F, 32) on an entirety of the upper surface (Figs. 2/6F, 14, front surface) of the semiconductor substrate (Figs. 2/6F, 10);
HARADA as modified by DUMITRU and SDRULLA does not explicitly disclose the method wherein the forming the gate insulating film includes: selectively removing prescribed portions of the insulating film to form a pattern of the insulating films on the upper surface of the semiconductor substrate; and thereafter forming another insulating film films on the pattern of the insulating films and on the upper surface of the semiconductor substrate on which the insulating film has been removed, thereby forming a composite insulating film as the gate insulating film having the first portion and the second portion that is thicker than the first portion.
YAMAGUCHI teaches the method (Figs. 4-10, a method for manufacturing the semiconductor chip, [0014-0020]) wherein the forming the gate insulating film (Fig. 16, 31/82) includes:
selectively removing prescribed portions of the insulating film (Fig. 6B-7A, 51, thermal oxide film is removed, [0065]) to form a pattern of the insulating films (Fig. 7B, 52, insulating film is formed, [0066]) on the upper surface of the semiconductor substrate (Fig. 9A, 29); and
thereafter forming another insulating film films on the pattern of the insulating films (Fig. 9A, 33, insulating film, [0069-0070]) and on the upper surface of the semiconductor substrate (Fig. 9A, 29) on which the insulating film (Fig. 8B, 52, insulating film, [0069]) has been removed (selectively removed, [0069]), thereby forming a composite insulating film as the gate insulating film (Figs. 8B-9A, 51/52/33 to Fig. 16, 31/82, gate insulating film) having the first portion and the second portion (Fig. 16, 33, insulating film) that is thicker than the first portion (Fig. 16, 31/18, gate insulating film).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HARADA as modified by DUMITRU and SDRULLA to incorporate the teachings of YAMAGUCHI , such that the method, wherein selectively removing prescribed portions of the insulating film to form a pattern of the insulating films on the upper surface of the semiconductor substrate; and thereafter forming another insulating film on the pattern of the insulating films and on the upper surface of the semiconductor substrate on which the insulating film has been removed, thereby forming a composite insulating film as the gate insulating film having the first portion and the second portion that is thicker than the first portion. The aforementioned forming, patterning and removal of semiconductor gate insulating films, constitute a low-side transistor and/or a high-side transistor, so that a current is passed either in the thickness direction of the vertical MOSFET and/or in horizontal direction of the lateral MOSFET (YAMAGUCHI, [0051], [0066], [0069]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 6700156 B2 – Figure 1
STATEMENT OF RELEVANCE – The vertical power MOSFET comprising: gate insulating film, 23 has a uniform thickness and sloped shape.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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