DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the rejection of claims under 35 USC 102 and 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot as further search and consideration have prompted the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 2, 7, 9 and 15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 2 includes “the substrate sidewall consists essentially of a mold compound” and there is no support for this limitation in the instant specification as originally filed. For example, paragraph [0032] of the originally filed instant specification discloses “substrate sidewall 113 can comprise or be referred to as a stiffener, a dielectric layer, a mold compound layer,” [0032]. Even if the substrate sidewall is a mold compound layer, there is no support for the mold compound layer consisting essentially of mold compound as the terminology “mold compound layer” is considered broader than the terminology “a mold compound layer consisting essentially of a mold compound,” and therefore the latter is narrower than what is supported by the instant specification. It is possible for a mold compound layer to include an amount of additives, resulting in the mold compound layer not consisting essentially of a mold compound. The instant limitation would preclude such additives, rendering the limitation unsupported.
Claim 7 includes “the lid consists essentially of a material configured to pass an optical signal” and there is no support for this limitation in the instant specification as originally filed. For example, paragraph [0043] of the originally filed instant specification discloses “lid 17 can comprise a translucent, transparent, or transmissive material. For example, lid 17 can comprise glass. In some examples, lid 17 is configured such that an optical signal generated from electronic component 12 or an optical signal generated from an external component can permeate lid 17. That is, lid 17 comprises a material configured to transmit, transfer, or pass (e.g., into and/or out of electronic device 10) an optical signal.” Accordingly, the instant specification simply discloses that an optical signal can permeate the lid 17 and that the lid comprises a translucent, transparent, or transmissive material. However, this is considered broader than the lid consisting essentially of a material configured to pass an optical signal as it is possible for the lid to include opaque material in selected areas which prevents an optical signal permeating the lid in those selected areas, the lid including transparent material that allows an optical signal to permeate the lid in other areas, and the instant limitation would preclude such opaque material which is not supported by the instant specification.
Claims 9, 15 include “the dam comprises a structure that is continuous along the outer edge so that no portion of the component first side is exposed between the component terminals and the component lateral side” and there is no support for the underlined portion of the limitation in the instant specification as originally filed.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 6, 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4, 21 include “a dam top side that resides a first horizontal plane” and it is unclear if this was intended to mean “a dam top side that resides on a first horizontal plane.” For the purposes of examination this will be interpreted to mean “a dam top side that resides on a first horizontal plane.”
Claim 6 includes “The electronic device of claim 5] further comprising” and it is unclear what claim 6 was intended to depend from. For the purposes of examination, claim 6 will be construed to depend from claim 5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20180076245A1 (“Ushiyama”) in view of US6097101A (“Sato”), further in view of US20240030254A1 (“Yun”), further in view of US6674159 (“Peterson”).
RE: Claim 1, Ushiyama discloses An electronic device (PKG1 in FIG. 3), comprising:
a substrate (wiring substrate WB, SR1, BND1, FLP, [0044], [0061]) comprising:
a substrate first side (top side of SR1t of WBt, [0048]);
a conductive structure (terminals BL; BL are made of metal such as copper, [0048]-[0049]);
a substrate sidewall (FLP) comprising a structure (FLP) on the substrate first side; and
a first lateral width (first lateral width of WB in x-direction);
wherein:
the substrate sidewall comprises a first height (first height of portion of FLP over WB);
the substrate sidewall forms a perimeter (FIG. 8 shows FLP forms a perimeter, [0014]-[0020]);
the substrate first side within the perimeter defines a substrate base (FIG. 8 shows the top side of SR1t, WBt within the perimeter defines a substrate base);
the substrate sidewall and the substrate base form a substrate cavity (FIG. 3 shows top of SR1t, WBt and FLP form a substrate cavity),
wherein the substrate cavity comprises a second lateral width (second lateral width between left inner surface of FLP and right inner surface of FLP in FIG. 3 in x-direction); and
the conductive structure is exposed from the substrate first side within the substrate cavity (FIG. 3 shows BL is exposed from SR1t);
an electronic component (semiconductor chip CP, [0053]) comprising:
a component first side (top side of CP which is CPt);
a component second side (bottom side of CP which is CPb) opposite to the component first side;
a component lateral side (left side and/or right side of CP) connecting the component first side to the component second side; and
component terminals (pads PD) at the component first side proximate to the component lateral side;
wherein:
the electronic component is disposed over a first portion of the substrate base within the substrate cavity (FIG. 3 shows CP is disposed over a first portion of SR1t within the substrate cavity);
internal interconnects (wires BW, [0057]) connecting the component terminals to the conductive structure exposed from the substrate first side within the substrate cavity (FIG. 3 shows BW connecting the component terminals PD to the exposed conductive structure BL); and
a lid (cover member CVG, [0044]) attached to the substrate sidewall and comprising a third lateral width (third lateral width of CVG in x-direction); wherein:
the first lateral width is greater than the second lateral width and the third lateral width (FIG. 3 shows the first lateral width of WB is greater than the second lateral width between inner surfaces of FLP and greater than the third lateral width of CVG); and
the third lateral width is greater than the second lateral width (FIG. 3 shows the third lateral width of CVG is greater than the second lateral width between inner surfaces of FLP).
Ushiyama does not explicitly disclose:
the structure of the substrate sidewall is a molded structure molded onto the substrate first side;
a dam on the component first side and covering the component terminals and covering a first portion of the internal interconnects, wherein the dam comprises an outer lateral side and an inner lateral side opposite to the outer lateral side, and wherein the outer lateral side extends to the component lateral side;
an encapsulant covering the component lateral side, a second portion of the internal interconnects, and a first portion of the outer lateral side of the dam;
the inner lateral side and a second portion of the outer lateral side of the dam are devoid of the encapsulant.
Ushiyama discloses the frame member FLP contains the glass fibers as similar to the above-described base member BSP. More specifically, the frame member is formed by curing a so-called prepreg material formed by impregnating a glass fiber sheet with a resin RES that is an epoxy-based thermosetting resin, the glass fiber sheet being formed by shaping the glass fibers GC to have a sheet shape, [0063].
In the same field of endeavor, Sato discloses The molded portion 45 can be formed in the shape of a frame or box on the box-shaped pattern 38, as shown in the drawings, by an injection molding or a transfer molding in which the wiring substrate 32 is inserted in a molding die. Especially, the molded portion 45 is formed to surround the side portions of the resin substrate 35 and box-shaped pattern 38 to prevent moisture permeating through the side portions of the package; Col. 4, lines 28-36, see FIG. 1.
Sato further discloses the molded portion 45 is made of thermosetting resin, Col. 3, lines 26-28.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mold FLP onto the wiring substrate WB as taught by Sato in order to prevent moisture permeating through package as further taught by Sato.
In the same field of endeavor, Yun discloses in FIG. 2:
a dam (200, [0018]) on a component first side (top side of chip C1, [0018]) and covering component terminals (conductive pads CP, [0022]) and covering a first portion of internal interconnects (first portion of bonding wires BW, [0022]), wherein the dam comprises an outer lateral side and an inner lateral side opposite to the outer lateral side (FIG. 2 shows 200 comprises an outer lateral side and an inner lateral side opposite to the outer lateral side), and wherein the outer lateral side extends to a component lateral side (FIG. 2 shows outer lateral side of 200 extends to component lateral left side and component lateral right side of C1);
an encapsulant (400) covering the component lateral side (FIG. 2 shows 400 covering the component lateral left side and component lateral right side of C1), a second portion of the internal interconnects (FIG. 2 shows 400 covering second lower portion of bonding wires BW), and a first portion of the outer lateral side of the dam (FIG. 2 shows 400 covering first portion of outer lateral side of 200);
the inner lateral side of the dam is devoid of the encapsulant (FIG. 2 shows inner lateral side of 200 is devoid of 400; further, Yun teaches dam structure 200 may seal or close the empty space between the transparent substrate 300 and the image sensor chip C1 to prevent moisture or a foreign material from permeating into the empty space from the outside, [0036]; Accordingly, 200 would prevent 400 from permeating into the empty space between 300 and C1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an encapsulant and dam, wherein the encapsulant covers the sides of the chip CP, at least a portion of wires BW, and outer sides of the dam as taught by Yun in order to protect the chip CP with the encapsulant as further taught by Yun, [0042], and to prevent the encapsulant from covering and interfering with the top light receiving part LRP of the chip CP.
In the same field of endeavor, Peterson discloses in FIG. 12A (see Annotated FIG. 12A from Peterson below):
the inner lateral side (inner lateral side of dam 910 facing opening 132) and a second portion of the outer lateral side of the dam (uppermost left side portion of 910, uppermost right side portion of 910 as shown in Annotated FIG. 12A below) are devoid of the encapsulant (128, Col. 21, lines 64-66; Annotated FIG. 12A below shows inner lateral side of dam 910, uppermost left side portion of 910, uppermost right side portion of 910 are devoid of 128).
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Annotated FIG. 12A from Peterson
Peterson further discloses in FIG. 12B (see Annotated FIG. 12B from Peterson below):
the inner lateral side (inner lateral side of dam 916 facing opening 132; 916 serves as a dam, Col. 22, lines 33-36) and a second portion of the outer lateral side of the dam (uppermost left side portion of 916, uppermost right side portion of 916) are devoid of the encapsulant (128).
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Annotated FIG. 12B from Peterson
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the uppermost left outer side portion and uppermost right outer side portion of Yun’s dam to be devoid of Yun’s encapsulant as taught by Peterson in order to prevent Yun’s encapsulant from flowing or permeating over Yun’s dam and interfering with Ushiyama’s light receiving part LRP and to conserve encapsulant material.
RE: Claim 4, Ushiyama in view of Sato, Yun, Peterson discloses The electronic device of claim 1, wherein:
the dam comprises a dam top side that resides on a first horizontal plane (In Ushiyama FIG. 3 the first horizontal plane is the plane defined by the top surface of the chip CP; As modified, Yun’s dam top side would reside on the top surface of Ushiyama’s chip CP);
the encapsulant comprises an encapsulant top side that resides on a second horizontal plane (second horizontal plane defined by top surface of SR1t in FIG. 3; As modified, Yun’s encapsulant would have a top side residing on the top surface of SR1t);
the component first side resides on a third horizontal plane (third horizontal plane defined by top surface of base member BSP in FIG. 3; the top side of the chip CP resides on the top surface of BSP in FIG. 3); and
the second horizontal plane is below the first horizontal plane and above the third horizontal plane (In FIG. 3, the top surface of SR1t is below the top surface of the chip CP and above the top surface of the base member BSP).
RE: Claim 7, Ushiyama in view of Sato, Yun, Peterson discloses The electronic device of claim 1, wherein: the lid consists essentially of a material configured to pass an optical signal (Ushiyama discloses The cover member CVG is a glass plate that is transparent relative to visible light, such that the light-receiving part LRP (see FIG. 2) of the semiconductor chip CP (see FIG. 2) can be visible from the upper surface CVGt of the cover member CVG, [0066]; Accordingly, CVG consists essentially of a material configured to pass an optical signal).
RE: Claim 8, Ushiyama in view of Sato, Yun, Peterson discloses The electronic device of claim 1, further comprising:
an adhesive (From Ushiyama FIG. 3: bonding material DB, [0109]);
wherein:
the electronic component is attached to the first portion of the substrate base with the adhesive (FIG. 3 shows CP is attached to the first portion of the substrate base SR1t with the adhesive DB);
the adhesive extends laterally across the component second side (FIG. 3 shows adhesive DB extends laterally across the component second side of CP); and
the encapsulant contacts the adhesive (In Yun FIG. 22, an adhesive ADL extending laterally across the bottom of the chip C1 is in direct contact with the encapsulant 400; Accordingly, the unlabeled layer immediately below the chip C1 in FIG. 2 of Yun is considered to be the adhesive ADL; Accordingly, as modified, Yun’s encapsulant would also contact Ushiyama’s adhesive DB).
RE: Claim 9, Ushiyama in view of Sato, Yun, Peterson discloses The electronic device of claim 1, wherein:
the component first side comprises an outer edge adjacent to the component lateral side (From Ushiyama FIG. 3, the chip CP comprises outer edges adjacent to the left and right lateral sides); and
the dam comprises a structure that is continuous along the outer edge so that no portion of the component first side is exposed between the component terminals and the component lateral side (In Yun, see FIGs. 3, 8; FIG. 8 shows the dam 200 is shown being continuous along the outer edge of the chip C1 so that no portion of the component first side of C1 is exposed between the component terminals CP and the component lateral side of the chip C1; Accordingly, as modified, Yun’s dam would be continuous along the outer edge of Ushiyama’s chip CP so that no portion of the component first side CPt of CP is exposed between the component terminals PD and the component left and right lateral sides).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ushiyama in view of Sato, Yun, Peterson as applied to claim 1, further in view of US20210323812 A1 (“Schaller”), further in view of US20140264831 A1 (“Meyer”), further in view of US20020093026A1 (“Huang”).
RE: Claim 2, Ushiyama in view of Sato, Yun, Peterson does not explicitly disclose The electronic device of claim 1, wherein:
the substrate sidewall consists essentially of a mold compound;
the substrate sidewall comprises an interior surface; and
the encapsulant extends to the interior surface.
However, Ushiyama discloses the frame member FLP contains the glass fibers as similar to the above-described base member BSP. More specifically, the frame member is formed by curing a so-called prepreg material formed by impregnating a glass fiber sheet with a resin RES that is an epoxy-based thermosetting resin, the glass fiber sheet being formed by shaping the glass fibers GC to have a sheet shape, [0063].
In the same field of endeavor, Schaller discloses a molding compound forming the encapsulation material 42 may comprise at least one of an epoxy, a filled epoxy, a glass fiber-filled epoxy, [0037].
Accordingly, the frame FLP formed by impregnating glass fiber sheet with an epoxy-based resin would be understood by one of ordinary skill in the art as consisting essentially of a molding compound as it is a glass fiber-filled epoxy.
Alternatively, in the same field of endeavor, Meyer discloses the encapsulation layer 706 formed over the second surface 704b of the second semiconductor chip 704 may, for example, depend on a filler size of the encapsulation layer 706 (e.g. including or consisting of a mold compound), [0145].
FIG. 7G shows encapsulation 706 forming a substrate sidewall surrounding the chip 704.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ushiyama’s substrate sidewall FLP to consist of a molding compound as taught by Meyer to ensure the substrate sidewall FLP is free of contaminants.
Further, the claim limitation “the encapsulant extends to the interior surface” does not necessarily require that the encapsulant is in direct contact with the interior surface. The word “to” is defined as “used as a function word to indicate direction toward,” see definition 1a for the adverb “to” by Merriam-Webster available at <https://www.merriam-webster.com/dictionary/to>. As Yun’s encapsulant 400 would surround Ushiyama’s chip CP, Yun’s encapsulant 400 would extend toward the interior surface of Ushiyama’s substrate sidewall FLP. Accordingly, under a broad reasonable interpretation, Yun’s encapsulant 400 would extend to the interior surface of Ushiyama’s substrate sidewall FLP.
Alternatively, in the same field of endeavor, Huang discloses in FIGs. 5-6:
an encapsulant (402) extends to an interior surface of a substrate sidewall (interior surface of substrate sidewall 124).
Huang further shows that the encapsulant 402 is in direct contact with the interior surface of 124, and covering the entirety of the upper surface of the substrate 100.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make Yun’s encapsulant 400 extend to Ushiyama’s substrate sidewall FLP as taught by Huang in order to better seal the upper surface of Ushiyama’s wiring substrate WB and to better connect the substrate sidewall FLP to the chip CP.
Claim(s) 3, 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ushiyama in view of Sato, Yun, Peterson as applied to claim 1, further in view of Huang.
RE: Claim 3, Ushiyama in view of Sato, Yun, Peterson does not explicitly disclose The electronic device of claim 1, wherein:
the encapsulant comprises a first thickness less than the first height.
However, in the same field of endeavor, Huang discloses in FIGs. 5-6:
an encapsulant (402) comprises a first thickness (vertical thickness of 402) less than a first height (vertical height of 124) of a substrate sidewall (124).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make Yun’s encapsulant have a thickness less than a height of the portion of Ushiyama’s substrate sidewall FLP over Ushiyama’s wiring substrate WB as taught by Huang in order to conserve encapsulant material while offering protection to Ushiyama’s chip CP.
RE: Claim 5, Ushiyama in view of Sato, Yun, Peterson discloses The electronic device of claim 1, wherein:
a third portion of the internal interconnects is exposed from the dam (In Yun FIG. 2, a third portion of the internal interconnects BW is exposed from the dam 200; Accordingly, as modified, a third portion of BW would be exposed from Yun’s dam).
Ushiyama in view of Sato, Yun, Peterson does not explicitly disclose
wherein: the third portion of the internal interconnects is exposed from the encapsulant.
In the same field of endeavor, Huang discloses in FIGs. 5-6:
a third portion of internal interconnects (upper portion of interconnects 140) is exposed from the encapsulant (402).
FIG. 3D shows the upper portions of interconnects 140 completely exposed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the third portion of Ushiyama’s internal interconnects BW exposed from Yun’s encapsulant as taught by Huang in order to conserve encapsulant material while still offering protection to the chip CP.
RE: Claim 6, Ushiyama in view of Sato, Yun, Peterson, Huang discloses The electronic device of claim 5, further comprising: an adhesive (In Ushiyama FIG. 3: BND2; BND2 is a bonding material containing an ultraviolet-ray curable resin as a main component, [0117]; BND2 adheres to CVG, [0124]) coupling the lid to the substrate sidewall.
Claim(s) 10, 12, 15, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ushiyama in view of Yun, further in view of Peterson.
RE: Claim 10 Ushiyama discloses An electronic device (PKG1 in FIG. 3), comprising:
a substrate (wiring substrate WB, SR1, BND1, FLP, [0044], [0061]) comprising:
a substrate base (WB including SR1t, [0046]) comprising a first width (first lateral width of WB in x-direction);
a substrate sidewall (FLP) at a perimeter of the substrate base (FIG. 8 shows FLP at a perimeter of SR1t, [0014]-[0020]); and
a conductive structure (terminals BL; BL are made of metal such as copper, [0048]-[0049]); wherein:
the substrate base and the substrate sidewall define a substrate cavity (FIG. 3 shows top of SR1t, WBt and FLP define a substrate cavity);
an electronic component (semiconductor chip CP, [0053]) disposed over the substrate base in the substrate cavity, the electronic component comprising a component first side (top side of CP which is CPt) distal to the substrate base, component terminals (pads PD) on the component first side, and a component lateral side (left side and/or right side of CP);
internal interconnects (wires BW, [0057]) connecting the component terminals to the conductive structure (FIG. 3 shows BW connecting the component terminals PD to the exposed conductive structure BL); and
a lid (cover member CVG, [0044]) overlying at least the first portion of the component first side (FIG. 3 shows CVG overlying at least a first portion of the top side of CPt) and comprising a second width (second lateral width of CVG in x-direction) less than the first width (FIG. 3 shows second lateral width of CVG is less than first lateral width of WB).
Ushiyama does not explicitly disclose:
a dam on the component first side and covering the component terminals and covering a first portion of the internal interconnects, wherein the dam comprises an outer lateral side and an inner lateral side opposite to the outer lateral side, and wherein the outer lateral side extends to the component lateral side;
an encapsulant over at least a portion of the component lateral side, wherein at least a first portion of the component first side is free of the encapsulant; and
wherein:
the inner lateral side and a second portion of the outer lateral side of the dam are devoid of the encapsulant.
In the same field of endeavor, Yun discloses in FIG. 2:
a dam (200, [0018]) on a component first side and covering the component terminals and covering a first portion of the internal interconnects (FIG. 3 shows 200 on a component first side of C1 and covering the component terminals PD and covering a first portion of the interconnects BW), wherein the dam comprises an outer lateral side and an inner lateral side opposite to the outer lateral side (FIG. 3 200 comprises an outer lateral side and an inner lateral side opposite to the outer lateral side), and wherein the outer lateral side extends to the component lateral side (FIG. 3 shows outer lateral side extends to component lateral left side and component lateral right side C1);
an encapsulant (400) over at least a portion of the component lateral side (FIG. 2 shows 400 over at least a portion of the component lateral side of C1), wherein at least a first portion of the component first side is free of the encapsulant (FIG. 2 shows at least a first portion of the component first side of C1 is free of the encapsulant 400).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an encapsulant and dam, wherein the encapsulant covers the sides of the chip CP, at least a portion of wires BW, and outer sides of the dam as taught by Yun in order to protect the chip CP with the encapsulant as further taught by Yun, [0042], and to prevent the encapsulant from covering and interfering with the top light receiving part LRP of the chip CP.
In the same field of endeavor, Peterson discloses in FIG. 12A (see Annotated FIG. 12A from Peterson below):
the inner lateral side (inner lateral side of dam 910 facing opening 132) and a second portion of the outer lateral side of the dam (uppermost left side portion of 910, uppermost right side portion of 910 as shown in Annotated FIG. 12A below) are devoid of the encapsulant (128, Col. 21, lines 64-66; Annotated FIG. 12A below shows inner lateral side of dam 910, uppermost left side portion of 910, uppermost right side portion of 910 are devoid of 128).
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Annotated FIG. 12A from Peterson
Peterson further discloses in FIG. 12B (see Annotated FIG. 12B from Peterson below):
the inner lateral side (inner lateral side of dam 916 facing opening 132; 916 serves as a dam, Col. 22, lines 33-36) and a second portion of the outer lateral side of the dam (uppermost left side portion of 916, uppermost right side portion of 916) are devoid of the encapsulant (128; Annotated FIG. 12A below shows inner lateral side of dam 916, uppermost left side portion of 916, uppermost right side portion of 916 are devoid of 128).
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Annotated FIG. 12B from Peterson
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the uppermost left outer side portion and uppermost right outer side portion of Yun’s dam to be devoid of Yun’s encapsulant as taught by Peterson in order to prevent Yun’s encapsulant from flowing or permeating over Yun’s dam and interfering with Ushiyama’s light receiving part LRP and to conserve encapsulant material.
RE: Claim 12, Ushiyama in view of Yun Peterson discloses The electronic device of claim 10, wherein:
the lid comprises a transmissive material (Ushiyama discloses The cover member CVG is a glass plate that is transparent relative to visible light, such that the light-receiving part LRP (see FIG. 2) of the semiconductor chip CP (see FIG. 2) can be visible from the upper surface CVGt of the cover member CVG, [0066]; Accordingly, CVG consists essentially of a material configured to pass an optical signal); and
the lid is coupled to the substrate sidewall (FIG. 3 Ushiyama shows the lid CVG is coupled to the substrate sidewall FLP).
RE: Claim 15, Ushiyama in view of Yun, Peterson discloses The electronic device of claim 10, wherein:
the component first side comprises an outer edge adjacent to the component lateral side (From Ushiyama FIG. 3, the chip CP comprises outer edges adjacent to the left and right lateral sides); and
the dam comprises a structure that is continuous along the outer edge so that no portion of the component first side is exposed between the component terminals and the component lateral side (In Yun, see FIGs. 3, 8; FIG. 8 shows the dam 200 is shown being continuous along the outer edge of the chip C1 so that no portion of the component first side of C1 is exposed between the component terminals CP and the component lateral side of the chip C1; Accordingly, as modified, Yun’s dam would be continuous along the outer edge of Ushiyama’s chip CP so that no portion of the component first side CPt of CP is exposed between the component terminals PD and the component left and right lateral sides).
RE: Claim 21, Ushiyama in view of Yun, Peterson discloses The electronic device of claim 10, wherein:
the dam comprises a dam top side that resides on a first horizontal plane (In Ushiyama FIG. 3 the first horizontal plane is the plane defined by the top surface of the chip CP; As modified, Yun’s dam top side would reside on the top surface of Ushiyama’s chip CP);
the encapsulant comprises an encapsulant top side that resides on a second horizontal plane (second horizontal plane defined by top surface of SR1t in FIG. 3; As modified, Yun’s encapsulant would have a top side residing on the top surface of SR1t);
the component first side resides on a third horizontal plane (third horizontal plane defined by top surface of base member BSP in FIG. 3; the top side of the chip CP resides on the top surface of BSP in FIG. 3); and
the second horizontal plane is below the first horizontal plane and above the third horizontal plane (In FIG. 3, the top surface of SR1t is below the top surface of the chip CP and above the top surface of the base member BSP).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ushiyama in view of Sato, Yun, Peterson as applied to claim 10, further in view of US20100264532A1 (“Bolken”), further in view of Huang.
RE: Claim 11, Ushiyama in view of Yun, Peterson discloses The electronic device of claim 10, wherein:
the substrate sidewall comprises a polymer structure (Ushiyama discloses FLP is formed by impregnating glass fiber with resin, [0063]; The word resin is defined as “any of a large number of synthetic, usually organic, materials that have a polymeric structures,” see definition 2 from Dictionary.com at https://www.dictionary.com/browse/resin; Accordingly, since FLP has resin, it has a polymer structure);
the substrate sidewall comprises an interior surface (FIGs. 3, 8 Ushiyama shows FLP has interior surface);
the encapsulant is over at least a portion of the internal interconnects (In FIG. 2 Yun shows the encapsulant 400 over at least a portion of the internal interconnects BW; Accordingly, as modified, Yun’s encapsulant would be over at least a portion of Ushiyama’s internal interconnects BW).
Ushiyama in view of Yun, Peterson does not explicitly disclose:
the polymer structure is a molded polymer structure molded onto the substrate base;
the encapsulant is over at least a portion of the interior surface.
In the same field of endeavor, Bolken discloses in FIGs. 2A, 3:
a substrate sidewall (16) comprises a molded polymer structure molded onto the substrate base (substrate base 2; Mold cavity 30 b is then filled with a mold compound 34 in a liquid or otherwise molten state. Mold compound 34 is cured to an at least semisolid state, and interposer 2 is removed from molding tool 28, leaving the housing structure 16 illustrated in FIGS. 2A-2C, [0046]; Mold compound 34 may be a thermoplastic polymer or other suitable encapsulant material as known in the art. Further, a filler material such as fine silicon particles may be incorporated within the mold compound 34, [0048]).
Bolken further discloses the substrate sidewall 16 has a wider opening at the top than at the bottom, with sloped interior side surfaces.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mold the substrate sidewall FLP onto the wiring substrate WB so that FLP has sloped interior side surfaces as taught by Bolken in order form a stronger conformal connection between the substrate WB and the substrate sidewall FLP, and to widen the upper opening of the substrate sidewall to allow more light to be received by the light receiving region LRP.
In the same field of endeavor, Huang discloses in FIGs. 5-6:
an encapsulant 402 extending to and in direct contact with interior surfaces of a substrate sidewall 124.
Huang further shows the encapsulant 402 covering the entirety of the upper surface of the substrate 100.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make Yun’s encapsulant 400 extend to and be in direct contact with Ushiyama’s substrate sidewall FLP as taught by Huang in order to better seal the upper surface of Ushiyama’s wiring substrate WB and to better connect the substrate sidewall FLP to the chip CP. As a result, the encapsulant would be over at least a portion of the interior surface of the substrate sidewall FLP.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ushiyama in view of Sato, Yun, Peterson as applied to claim 10, further in view of Huang.
RE: Claim 22, Ushiyama in view of Yun, Peterson discloses The electronic device of claim 10, wherein:
a third portion of the internal interconnects is exposed from the dam (In Yun FIG. 2, a third portion of the internal interconnects BW is exposed from the dam 200; Accordingly, as modified, a third portion of BW would be exposed from Yun’s dam).
Ushiyama in view of Yun, Peterson does not explicitly disclose
wherein: the third portion of the internal interconnects is exposed from the encapsulant.
In the same field of endeavor, Huang discloses in FIGs. 5-6:
a third portion of internal interconnects (upper portion of interconnects 140) is exposed from the encapsulant (402).
FIG. 3D shows the upper portions of interconnects 140 completely exposed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the third portion of Ushiyama’s internal interconnects BW exposed from Yun’s encapsulant as taught by Huang in order to conserve encapsulant material while still offering protection to the chip CP.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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