DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/05/2025 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/11/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-10, 12-18, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Shimomura; US 2023/0069307 A1; 08/2021 in view of Lee et al.; US 7,622,778 B2; 05/2006 and Gwon et al.; US 2021/0287986 A1; 10/2020.
Claim 1: Shimomura discloses A semiconductor device (par [0089] The structure shown in Fig. 2 is provided after formation of semiconductor devices #720 on a substrate semiconductor layer #9), comprising:
a first semiconductor structure (par [0064] #132 first insulating layer,#146 first electrically conductive layer) including a first substrate (par [0065] First exemplary structure can include an optional semiconductor material layer #110. Semiconductor material layer #110 may be a substrate) and circuit devices (par [0068] first memory array region 100A. [0075] At least a portion of the first electrically conductive layers #146 and at least a portion of the second electrically conductive layers #246 continuously extend from the first memory array region #100A to the second memory array region #100B) on the first substrate (par [0065] First exemplary structure can include an optional semiconductor material layer #110. Semiconductor material layer #110 may be a substrate); and a second semiconductor structure (par [0064] #232 second insulating layer, #246 second electrically conductive layer) on the first semiconductor structure (par [0064] #132 first insulating layer,#146 first electrically conductive layer), wherein the second semiconductor structure (par [0064] #232 second insulating layer, #246 second electrically conductive layer) includes: a second substrate ( par [0076] located over the substrate) having a first region (par [0076] Combination of a first-tier alternating stack (#132 first insulating layer, #146 first electrically conductive layer) and an overlying second-tier alternating stack (#232, #246)) and a second region (par [0076] A structure that is adjacent to each combination of a first-tier alternating stack (#132, #146 and an overlying second-tier alternating stack(232,246) may be provided);
interlayer insulating layers (par [0112] Generally, at least one additional vertically alternating sequence of additional continuous insulating layers and additional continuous sacrificial material layers can be optionally formed over the first vertically alternating sequence (#132L, #142L) and the first-tier retro-stepped dielectric material portions #165) alternately stacked with the gate electrodes (#142L); channel structures ( par [0133] The memory stack structure #55 is a combination of a vertical semiconductor channel #60, a tunneling dielectric layer #56, a plurality of memory elements comprising portions of the memory material layer #54, and an optional blocking dielectric layer #52) penetrating through the gate electrodes ( par [0134] Each of the memory stack structures #55 comprises vertical NAND string including the respective vertical stack of memory elements, and a vertical semiconductor channel #60 that vertically extend through the continuous sacrificial material layers (#142L, #242L) adjacent to the respective vertical stack of memory elements.), extending in the first direction ( par [0134] vertically extend) , and respectively including a channel layer ( par [0128] A semiconductor channel material layer #60L); gate contact plugs ( par [0135] support pillar structures #20) penetrating through the pad region ( par [0135] The support pillar structures #20 include first support pillar structures #20 that vertically extend through the second vertically alternating sequence (#232L, #242L), a first-tier retro-stepped dielectric material portion #165, and a portion of the first vertically alternating sequence (#132L, #142L) that underlies the first-tier retro-stepped dielectric material portion #165) of each of the gate electrodes (#142L) and extending into the first semiconductor structure (#132L) in the first direction (vertically); and the second insulating layer ( #232 ) includes a first portion filling a region between the first insulating layer ( #132) and each of the gate electrodes ( #142L ) opposing the first insulating layer ( #132) and extending onto upper and lower surfaces of the first insulating layer ( par [0066] A second-tier alternating stack of second insulating layers #232 and second electrically conductive layers #246 overlies the first-tier alternating stack (132, 146), and overlies a horizontal plane including a planer top surface of the first-tier retro-stepped dielectric material portion #165 between each neighboring pair of trench fill structures #76).
Shimomura does not appear to disclose gate electrodes spaced apart from each other on the first region in a first direction, extending on the second region by different lengths in a second direction, and respectively including a pad region on the second region having an upper surface exposed upwardly; the insulating structure further includes a first insulating layer and a second insulating layer surrounding all of the first insulating layer and an insulating structure alternating between the interlayer insulating layers below a respective one of the pad regions, surrounding the gate contact plugs, and having a first sidewall abutting a second sidewall of the gate electrodes, and including a material different from any material of the first insulating layer.
However, Gwon teaches gate electrodes ( Fig. 4 #130 ) spaced apart from each other on the first region in a first direction ( as shown in Fig. 4 ), extending on the second region by different lengths in a second direction ( Fig. 4 #130 extends in the X direction at different lengths ), and respectively including a pad region on the second region having an upper surface exposed upwardly ( [0026] a second interconnection structure UI electrically connected to the gate electrodes #130 and the channel structures CH ); an insulating structure ( Fig. 4 #118 ) alternating between the interlayer insulating layers ( Fig. 4 #120 ) below a respective one of the pad regions ( Fig. 4 #184 ), surrounding the gate contact plugs (Fig. 4 #165 ), and having a first sidewall abutting a second sidewall of the gate electrodes ( Fig. 4 #165 ), and including a material different from any material of the first insulating layer ( [0049] The sacrificial insulating layers #118 may be formed of an insulating material different from an insulating material of the interlayer insulating layers #120 ).
Gwon does not appear to disclose the insulating structure further includes a first insulating layer and a second insulating layer surrounding all of the first insulating layer.
However, Lee discloses the insulating structure further includes a first insulating layer ( Fig. 2F oxide layer #132 ) and a second insulating layer ( Fig. 2F #134 ) surrounding all of the first insulating layer ( as shown in Fig. 2F ).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Lee with Shimomura and Gwon to implement the insulating structure further includes a first insulating layer and a second insulating layer surrounding all of the first insulating layer because the second insulating layer provides mechanical protection and an environmental barrier for the first insulating layer.
Claim 2: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 1 (as discussed above).
Shimomura discloses the first portion of the second insulating layer has a uniform thickness ( par [0111] Each of the second continuous insulating layers 232L is an insulating layer that continuously extends over the entire area of the substrate #8, and may have a uniform thickness throughout)
Claim 3: Shimomura, Gwon and Lee disclose the semiconductor device of claim 1 (as discussed above).
Shimomura discloses the second insulating layer further includes a second portion (#265, Fig. 14) between the first insulating layer (#132L, Fig. 14) and the gate contact plugs ( par [0154] A second-tier alternating stack of second insulating layers #232 and second electrically conductive layers #246 is formed between the neighboring pair of backside trenches #79), and the first portion and the second portion are integrally connected to each other ( par [0154] a second subset of the electrically conductive layers (146, 246) that is interlaced with the second insulating layers #246).
Claim 4: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 3 (as discussed above).
Shimomura discloses wherein a first thickness of the first portion is different from a second thickness of the second portion ( [0077] A vertical distance between the second stepped surfaces and the substrate increases along the first horizontal direction hd1, and a vertical distance between the additional second stepped surfaces and the substrate decreases along the first horizontal direction hd1).
Claim 5: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 3 (as discussed above).
Shimomura discloses wherein the second insulating layer (#232) has a protrusion extending in a direction from the second portion ( par [0066] A second-tier retro-stepped dielectric material portion #265 overlies, and contacts, second stepped surfaces of the second-tier alternating stack (#232, #246). Vertical steps S of the first stepped surfaces and the second stepped surfaces laterally extend along the second horizontal direction hd2 (e.g. bit line direction) toward an internal region of the first insulating layer (#132).
Claim 7: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 1 (as discussed above).
Shimomura discloses wherein a first thickness of the first portion ( par [0076] an additional second-tier retro-stepped dielectric material portion #265 overlying additional second stepped surfaces of the additional second-tier alternating stack (#232,#246), and a trench fill structure #76 laterally extending along the first horizontal direction hd1. [0115] The material of the second retro-stepped dielectric material portion #265 may be the same as the material of the first retro-stepped dielectric material portion #165) ranges from about 80 A to about 100 A ([0125] The memory material layer #54 may include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions (e.g. floating gates). The thickness of the memory material layer #54 may be in a range from 2 nm to 20 nm. 80 A is 8 nm and 100 A is 10 nm so the range is covered).
Claim 8: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 1 (as discussed above).
Shimomura discloses the first insulating layer (#132) defines a seam within the first insulating layer ( Fig 3A illustrates a seam in (#132L first continuous insulating layers) in region #163 (A first stepped cavity)).
Claim 9: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 1 (as discussed above).
Shimomura discloses the first insulating layer includes oxide ( par [0091] the first material of the first continuous insulating layers #132L may be a first silicon oxide material) , and the second insulating layer includes silicon oxynitride ([0091] Insulating materials include, but are not limited to silicon oxide, silicon nitride, silicon oxynitride).
Claim 10: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 1 (as described above).
Shimomura discloses each of the gate electrodes has a first gate thickness in a stack region ( [0191] each of the electrically conductive layers (146, 246) may be formed with a respective protrusion region #148 that includes a respective combination of a protrusion via portion 148V and a protrusion pad portion #148P other than the pad region), and has a second gate thickness greater than the first gate thickness in the pad region ( [0196] The protrusion pad portion 148P has a greater lateral extent than the protrusion via portion 148V).
Claim 12: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 1 (as discussed above).
Shimomura discloses the first semiconductor structure further includes pad layers in contact with the gate contact plugs ( par [0193] The respective protrusion regions #148 are not over etched through the entire thickness of the underlying electrically conductive layers (#146,#246)) on lower ends of the gate contact plugs (via cavities (#85A,#85B)).
Claim 13: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 1 (as discussed above).
Shimomura discloses the second semiconductor structure (par [0080]) includes: substrate insulating layers (#132) penetrating through the second substrate (par [0080] a substrate) and surrounding the gate contact plugs (#780), respectively ( par [0080] The lower-level metal interconnect structures #780 can be embedded in the lower-level dielectric material layers #760, which are located between the first-tier alternating stack (#132, #146) and a substrate); a horizontal insulating layer horizontally below the gate electrodes on a portion of the second substrate ( [0080] a tubular insulating spacer #484 that laterally surrounds the conductive via structure #486); and a horizontal conductive layer ( par [0081] Drain contact via structures can extend through the contact-level dielectric layer #280. Bit lines can laterally extend along the second horizontal direction hd2, and can contact top surfaces of a respective subset of the drain contact via structures) on the horizontal insulating layer(#484), wherein the gate contact plugs (#780) penetrate the horizontal insulating layer (#280) and the horizontal conductive layer (#280), and are spaced apart from the horizontal insulating layer (#484) and the horizontal conductive layer (#280) by the substrate insulating layers (#132).
Claim 14: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 1 (as discussed above).
Shimomura discloses wherein a distance of one side surface ( Fig. 10 #100A) of the insulating structure opposing each of the gate electrodes in the first direction is greater than a distance of another side surface (Fig. 10 #100B) opposing the gate contact plugs in the first direction.
Claim 15: Shimomura discloses a semiconductor device, comprising: a substrate having a first region ( [0089] The substrate semiconductor layer #9 may comprise a top portion of a substrate #8) and a second region (or a semiconductor layer located over a substrate), and a remaining stack region (#232L, #242L, FIG. 10), a gate contact plug (FIG 22B, #86A) penetrating through the pad region (#167) of a first gate electrode (Fig 24B, #148P, #148V), which is one of the gate electrodes, electrically connected to the first gate electrode (Fig 24B, #148P, 148V), penetrating through the remaining stack region (#232L, #242L), of a second gate electrode (Fig 25 #86A), which is another one of the gate electrodes and below the first gate electrode, the gate contact plug spaced apart from the second gate electrode ( #86B) ; and an insulating structure (#266 insulating liner) between the gate contact plug (#86B) and the second gate electrode (#248P, #248V), wherein the insulating structure includes a first insulating layer (#132) and a second insulating layer (#232)
Shimomura does not appear to disclose gate electrodes stacked and spaced apart from each other in a first direction on the first region, extending on the second region by different lengths in a second direction and respectively including a pad region on the second region having an upper surface exposed upwardly; having a first sidewall abutting a second sidewall of the second gate electrode and including a material different from any material of the first insulating layer and fully surrounding the first insulating layer.
However, Gwon discloses gate electrodes ( Fig. 4 #130 ) stacked and spaced apart from each other in a first direction on the first region ( as shown in Fig. 4 ), extending on the second region by different lengths in a second direction ( Fig. 4 #130 extends in the X direction at different lengths ), and respectively including a pad region on the second region having an upper surface exposed upwardly ( [0026] a second interconnection structure UI electrically connected to the gate electrodes #130 and the channel structures CH ); having a first sidewall abutting a second sidewall of the gate electrodes ( Fig. 4 #165 ) and including a material different from any material of the first insulating layer ( [0049] The sacrificial insulating layers #118 may be formed of an insulating material different from an insulating material of the interlayer insulating layers #120 ).
Gwon does not appear to disclose fully surrounding the first insulating layer.
However, Lee teaches fully surrounding the first insulating layer ( Fig. 2F #134 fully surrounds #132 )
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Lee with Shimomura and Gwon to implement fully surrounding the first insulating layer because this approach provides an environmental barrier for the first insulating layer.
Claim 16: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 15 (as discussed above).
Shimomura discloses the first insulating layer (#132) is spaced apart from the gate contact plug (#86B, Fig 25. Above the first insulating layer) and the second gate electrode (#248P, #248V, Fig 5. Above the first insulating layer).
Claim 17: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 15 (as discussed above).
Shimomura discloses the second insulating layer (#232) includes a first portion extending with a first thickness and a second portion (#265, Fig. 14) extending with a second thickness different from the first thickness ( [0077] A vertical distance between the second stepped surfaces and the substrate increases along the first horizontal direction hd1, and a vertical distance between the additional second stepped surfaces and the substrate decreases along the first horizontal direction hd1) , the first portion and the second portion are integrally connected to each other ( par [0154] a second subset of the electrically conductive layers (146, 246) that is interlaced with the second insulating layers #246), and the second portion (#265 Fig. 14) is in contact with the gate contact plug (Fig 24D, #265 is next to #86A).
Claim 18: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 15 (as discussed above).
Shimomura discloses the insulating structure ( [0115] The material and/or thickness of the second insulating liner #266 may be the same as the material and/or thickness of the first insulating liner #166) has a thickness decreasing ( Fig. 24D #166 is removed to form the electrode #148, same process for #266 and #248) from the second gate electrode (#248P, #248V) toward the gate contact plug (#86B).
Claim 22: Shimomura, Gwon, and Lee disclose the semiconductor device of claim 1 (as discussed above).
Shimomura discloses each of the gate contact plugs comprises a vertical extension portion extending in the first direction ( Fig. 13D #60) , and a horizontal extension portion extending horizontally from the vertical extension portion ( Fig. 13D #60 center piece extends horizontally ) and contacting the respective one of the pad region ( Fig. 13D top of the gate plug #63 connects to the pad region), the vertical extension portion ( Fig. 13D #60 ) penetrates the second substrate ( Fig. 13D substrate #110)
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Shimomura; US 2023/0069307 A1; 08/2021 in view of Lee et al.; US 7,622,778 B2; 05/2006 and Gwon et al.; US 2021/0287986 A1; 10/2020 as applied to claim 8 and further in view of Hinoue et al.; US 2022/0406720 A1; 06/2021.
Claim 21: Shimomura, Lee, and Gwon disclose the semiconductor device of claim 8 (as discussed above).
Neither Shimomura nor Lee nor Gwon appear to disclose the seam is an air seam.
However, Hinoue teaches the seam is an air seam ( Fig. 12 air gap #39)
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Hinoue with Shimomura and Gwon to implement the seam is an air seam because air can be used as a dielectric to reduce parasitic capacitance.
Response to Amendment/Arguments
Applicant’s arguments, see page 11 - 13 of the remarks, filed 12/05/2025, with respect to the rejection(s) of claims 1 and 15 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lee.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817