Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-5, 7, 9, 11-15, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. (U.S. Patent No. 9,076,795) in view of Shin et al. (U.S. Patent Publication No. 2021/0210346) and Lin et al. (U.S. Patent Publication No. 2018/0261537).
Referring to figures 1-5, Saito et al. teaches an interconnect structure comprising:
a first dielectric layer (11/13) including a trench (see figure 2a);
a conductive wire (12/21/22) filling an inside of the trench (see figure 2);
a first cap layer (23) on a top surface of the conductive wire, the first cap layer including a doped graphene, the doped graphene being graphene doped with a group V element (see figure 5, col. 5, lines 35-40); and
a second dielectric layer (25) on a top surface of first cap layer (see figure 5).
However, the reference does not clearly teach the doped graphene has a surface energy with a water contact angle of about 60 degrees or less, the second dielectric layer includes a first portion on the region of the first dielectric layer and a second portion over the trench of the first dielectric layer, and a thickness of the first portion is uniform with a thickness of the second portion (in claim 1, 15), a doping concentration of the doped graphene is about 0.1 % to about 30 % (in claims 3, 18).
Shin et al. teaches doped graphene has a surface energy with a water contact angle of 60 degrees or less (see paragraphs# 19, 27, 70, meeting claims 1, 15), a doping concentration of the doped graphene is about 0.1 % to about 30 % (see paragraph# 20, meeting claims 3, 18).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the invention was filed would form doped graphene has a surface energy with a water contact angle of 60 degrees or less, a doping concentration of the doped graphene is about 0.1 % to about 30 % in Saito et al. as taught by Shin et al. because it is known in the semiconductor to improve adhesion or resistance (see paragraph# 113).
And Lin et al. teaches the second dielectric layer (40) includes a first portion on the region of the first dielectric layer (12) and a second portion over the trench of the first dielectric layer, and a thickness of the first portion is uniform with a thickness of the second portion (see figure 4, paragraph# 33, meeting claims 1, 15).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the invention was filed would form the second dielectric layer includes a first portion on the region of the first dielectric layer and a second portion over the trench of the first dielectric layer, and a thickness of the first portion is uniform with a thickness of the second portion in Saito et al. as taught by Lin et al. because it is known in the semiconductor to improve reliability of the interconnect structure (see paragraph# 33).
Regarding to claim 2, wherein a doping material of the doped graphene comprises at least one of nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb) (see figure 5, col. 5, lines 35-40).
Regarding to claim 5, the doped graphene comprises intrinsic graphene or nanocrystalline graphene (see col. 2, lines 8-13).
Regarding to claim 7, the nanocrystalline graphene has a thickness of 3 nm or less (see col. 2, lines 13-20).
Regarding to claim 9, the first dielectric layer comprises a dielectric material having a dielectric constant of about 3.6 or less (11/13, see col. 4, lines 47-49).
Regarding to claims 11, 19, a second cap layer in the trench, wherein the second cap layer comprises the doped graphene (see col. 3, lines 6-15).
Regarding to claim 12, a barrier layer (21) in the trench (see figure 2b).
Regarding to claim 13, the barrier layer (21) covers a side surface of the conductive wire and a bottom surface of the conductive wire (22, see figure 2b).
Regarding to claim 14, an electronic device comprising: the interconnect structure of claim 1 (see figure 1-5).
Regarding to claim 15, an interconnect structure comprising:
a first dielectric layer (11/13) including a trench (12, 21, 22) and a region surrounding the trench of the first dielectric layer, the region of the first dielectric layer defining a sidewall of the trench and including a top surface higher than a bottom of the trench (see figure 2b);
a conductive wire (21/22) in the trench; and
a first cap layer (23) on a top surface of the conductive wire (21/22), the first cap layer including a doped graphene, the doped graphene including graphene doped with a group V element, the top surface of the conductive wire being opposite the bottom of the trench (see figure 5, col. 5, lines 35-40).
Regarding to claim 20, the doped graphene of the first cap layer (23) is directly on the top surface of the conductive wire (22, see figure 5).
Claims 6, 8, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. (U.S. Patent No. 9,076,795) in view of Shin et al. (U.S. Patent Publication No. 2021/0210346) and Lin et al. (U.S. Patent Publication No. 2018/0261537), as applied in claim(s) 1-5, 7, 9, 11-15, 18-20 above, and further in view of Byun et al. (U.S. Patent Publication No. 2020/0035611).
Referring to figures 1-5, Saito et al. teaches an interconnect structure comprising:
a first dielectric layer (11/13) including a trench (see figure 2a);
a conductive wire (12/21/22) filling an inside of the trench (see figure 2);
a first cap layer (23) on a top surface of the conductive wire, the first cap layer including a doped graphene, the doped graphene being graphene doped with a group V element (see figure 5, col. 5, lines 35-40); and
a second dielectric layer (25) on a top surface of first cap layer (see figure 5).
However, the reference does not clearly teach the nanocrystalline graphene comprises crystals having a size of about 0.5 nm to about 150 nm (in claim 6), the doped graphene comprises a bonding structure in which a ratio of carbon having sp2 bonding to total carbon is about 50 % to about 99 % (in claim 8).
Byun et al. teaches the nanocrystalline graphene comprises crystals having a size of about 0.5 nm to about 150 nm (see figure 9, paragraph# 7, meeting claim 6), the doped graphene comprises a bonding structure in which a ratio of carbon having sp2 bonding to total carbon is about 50 % to about 99 % (see figure 9, paragraph# 7, meeting claim 8).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the invention was filed would form a specific nanocrystalline graphene size and a specific a ratio of carbon having sp2 bonding to total carbon is about 50 % to about 99 % in Saito et al. as taught by Byun et al. because it is known in the semiconductor to improve electromigration resistance.
Claims 10, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. (U.S. Patent No. 9,076,795) in view of Shin et al. (U.S. Patent Publication No. 2021/0210346) and Lin et al. (U.S. Patent Publication No. 2018/0261537), as applied in claim(s) 1-5, 7, 9, 11-15, 18-20, and further in view of Li et al. (U.S. Patent Publication No. 2022/0157710).
Referring to figures 1-5, Saito et al. teaches an interconnect structure comprising:
a first dielectric layer (11/13) including a trench (see figure 2a);
a conductive wire (12/21/22) filling an inside of the trench (see figure 2);
a first cap layer (23) on a top surface of the conductive wire, the first cap layer including a doped graphene, the doped graphene being graphene doped with a group V element (see figure 5, col. 5, lines 35-40); and
a second dielectric layer (25) on a top surface of first cap layer (see figure 5).
However, the reference does not clearly teach the first dielectric layer includes silicon oxycarbide (SIOCH, see paragraph# 34), and the second dielectric layer includes silicon carbide or silicon carbon nitride (in claims 10, 17).
Li et al. teaches the second dielectric layer comprises silicon carbon nitride (SiCN, see paragraph# 67, meeting claim 10), the first dielectric layer includes silicon oxycarbide (SIOCH, see paragraph# 34), and the second dielectric layer includes silicon carbide (SiC, see paragraph# 67, meeting claim 17).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a specific material for the first dielectric and second dielectric in Saito et al. as taught by Li et al. because choosing an optimum material for a layer is known in the semiconductor art to form a layer to reduce resistivity and electromigration of the conductive structure (see paragraph# 13).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893