Prosecution Insights
Last updated: August 18, 2026
Application No. 17/959,892

SEMICONDUCTOR PACKAGE MANUFACTURING METHOD

Non-Final OA §103
Filed
Oct 04, 2022
Priority
Nov 08, 2021 — RE 10-2021-0152107
Examiner
CHOUDHRY, MOHAMMAD M
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
3 (Non-Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
576 granted / 703 resolved
+13.9% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
31 currently pending
Career history
737
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
75.6%
+35.6% vs TC avg
§102
10.9%
-29.1% vs TC avg
§112
4.1%
-35.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 703 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/12/2026 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 8-10, 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2010/0277850, hereinafter Chang) in view of Foulke (WO 0003829, hereinafter Foulke) and further in view of Yang (US 2018/0122680, hereinafter Yang). With respect to claim 1, Chang discloses a semiconductor package manufacturing method (Para 0005) which uses a semiconductor package manufacturing apparatus including: a chuck (200 of Fig. 2); and a scanning device (122 of Fig. 6) configured to provide information about a shape of the substrate to the chuck (Para 0016 & 0023), wherein the chuck comprises a first adsorbing portion (Para 0020 – center zone with independent control), a second adsorbing portion (Para 0020-0021– intermediate & outer zones), and a driver configured to drive the first adsorbing portion and each of the a plurality of divided regions of the second adsorbing portion (Para 0007; 0028; respective voltage sources/drivers provide the respective voltages V1-V3 to the zones 201-203 of the electrostatic chuck – a processor controls a metrology device to measure data indicating an amount of warpage of the wafer; determining at least two different voltages to be applied to respective portions of the wafer by an electrostatic chuck that is to hold the wafer, based on the amount of warpage – electrostatic chuck drives the wafer), wherein the first adsorbing portion and each of the plurality of divided regions of the second adsorbing portion are configured to adsorb the substrate (Para 0019-0021), the semiconductor package manufacturing method comprising: driving each of the plurality of divided regions to move along a vertical direction (Para 0069; 0118) to correspond to the shape of the substrate based on the information using the driver (Para 0019 – applying different voltages to different regions of the wafer to flatten the substrate – processor optimize voltage profile base on warpage). Chang does not explicitly disclose a solder device configured to attach solder balls to a substrate provided on the chuck. In an analogous art, Foulke discloses a solder device configured to attach solder balls to a substrate provided on the chuck (page 06; lines 16-35). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s method by having Foulke’s disclosure in order to connect different components of a semiconductor device. Chang/Foulke does not explicitly disclose controlling the scanning device to obtain the information about the shape of the substrate; rotating the second adsorbing portion based on the information about the shape of the substrate; and individually driving each of the plurality of divided regions. In an analogous art, Yang discloses controlling the scanning device to obtain the information about the shape of the substrate (para 0068 and 0074; 0081 – shape of the warpage of the wafer); rotating the second adsorbing portion based on the information about the shape of the substrate (para 0036; 0048; 0108; and 0117 – controlling the movement/rotation based on the received measurements from the sensor); and individually driving each of the plurality of divided regions (Para 0071 – individually controlling divided regions). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang/Foulke’s method by having Yang’s disclosure in order to improve processing quality by reducing unevenness on a wafer surface by controlling individual sections of the chuck. With respect to claim 8, Chang does not explicitly disclose wherein the semiconductor package manufacturing apparatus further comprising an inspection device configured to: identify whether the solder balls are attached to the substrate and a location corresponding to a missing solder ball; and provide a solder ball to the location corresponding to the missing solder ball. In an analogous art, Foulke discloses wherein the semiconductor package manufacturing apparatus further comprising an inspection device configured to: identify whether the solder balls are attached to the substrate and a location corresponding to a missing solder ball (Page 6; lines 18-27); and provide a solder ball to the location corresponding to the missing solder ball (Page 06; lines 1-17). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s method by having Foulke’s disclosure in order to connect different components of a semiconductor device. With respect to claim 9, A semiconductor package manufacturing method (Para 0005) comprising: a chuck (200 of Fig. 2) comprising a first adsorbing portion (Para 0020 – center zone with independent control) and a second adsorbing portion (Para 0020-0021– intermediate & outer zones), wherein the second adsorbing portion comprises a plurality of divided regions (Para 0020-0021-intermediate & outer zones); providing information about a warpage shape of the substrate to the chuck (Para 0016 & 0023); and controlling positions of each of the plurality of divided regions of the second adsorbing portion (Para 0007; 0028; respective voltage sources/drivers provide the respective voltages V1-V3 to the zones 201-203 of the electrostatic chuck – a processor controls a metrology device to measure data indicating an amount of warpage of the wafer; determining at least two different voltages to be applied to respective portions of the wafer by an electrostatic chuck that is to hold the wafer, based on the amount of warpage) along a vertical direction based on the information (para 0026 – moving in y direction based on the scanning results); Chang does not explicitly disclose attaching solder balls to a substrate provided on the chuck. In an analogous art, Foulke discloses attaching solder balls to a substrate provided on the chuck (page 06; lines 16-35). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s method by having Foulke’s disclosure in order to connect different components of a semiconductor device. Chang/Foulke does not explicitly disclose rotating the second adsorbing portion based on the information about the warpage shape of the substrate; and individually controlling positions of each of the plurality of divided regions. In an analogous art, Yang discloses rotating the second adsorbing portion based on the information about the warpage shape of the substrate (para 0068 and 0074; 0081 – shape of the warpage of the wafer; para 0036; 0048; 0108; and 0117 – controlling the movement/rotation based on the received measurements from the sensor); and individually controlling positions of each of the plurality of divided regions (Para 0071 – individually controlling divided regions). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang/Foulke’s method by having Yang’s disclosure in order to improve processing quality by reducing unevenness on a wafer surface by controlling individual sections of the chuck. With respect to claim 10, Chang discloses wherein the second adsorbing portion comprises the plurality of divided regions divided along a circumferential direction (Para 0020-0021-intermediate & outer zones). With respect to claim 12, Chang/Foulke does not explicitly disclose wherein the chuck further comprises a third adsorbing portion comprising a plurality of divided regions divided along a circumferential direction. In an analogous art, Yang discloses wherein the chuck further comprises a third adsorbing portion comprising a plurality of divided regions divided along a circumferential direction (Para 0069; 0085; and 0101; Fig. 5B – There are different portions to adsorb the wafer and each portion is divided into multiple regions). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang/Foulke’s method by having Yang’s disclosure in order to improve processing quality by reducing unevenness on a wafer surface by controlling individual sections of the chuck. With respect to claim 16, Chang does not explicitly disclose wherein the semiconductor package manufacturing apparatus further comprising: identifying the solder balls that are attached to the substrate; and providing a solder ball to a location corresponding to the missing solder ball. In an analogous art, Foulke discloses wherein the semiconductor package manufacturing apparatus further comprising identifying the solder balls that are attached to the substrate (Page 6; lines 18-27); and providing a solder ball to the location corresponding to the missing solder ball (Page 06; lines 1-17). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s method by having Foulke’s disclosure in order to connect different components of a semiconductor device. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chang/Foulke/Yang in view of LaBrie (US 2019/0341290, hereinafter LaBrie). With respect to claim 4, Chang/Foulke/Yang does not explicitly disclose wherein the driver is further configured to rotate the plurality of divided regions along a direction parallel to an upper surface of the substrate. In an analogous art, LaBrie discloses wherein the driver is further configured to rotate the plurality of divided regions along a direction parallel to an upper surface of the substrate (0049-0051). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang/Foulke/Yang’s method by having LaBrie’s disclosure in order to improve processing quality by reducing unevenness on a wafer surface by controlling individual sections of the chuck. Claims 2-3, 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang/Foulke/Yang in view of Kato. With respect to claim 2, Chang/Foulke/Yang discloses the semiconductor manufacturing method of claim 1. Chang/Foulke/Yang does not explicitly disclose wherein each of the plurality of divided regions of the second adsorbing portion is configured to adsorb the substrate at a position corresponding to the shape of the substrate. In an analogous art, Kato discloses wherein each of the plurality of divided regions of the second adsorbing portion is configured to adsorb the substrate at a position corresponding to the shape of the substrate (Para 0056 and 0109). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang/Foulke/Yang’s method by having Kato’s disclosure in order to reduce imperfections of a wafer by addressing each section individually. With respect to claim 3, Chang/Foulke/Yang discloses the semiconductor manufacturing method of claim 1. Chang/Foulke/Yang does not explicitly disclose wherein each of the plurality of divided regions of the adsorbing portion is configured to move each of the plurality of divided regions along the vertical direction. In an analogous art, Kato discloses wherein the driver is further configured to move each of the plurality of divided regions along the vertical direction (Para 0032). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang/Foulke/Yang’s method by having Kato’s disclosure in order to reduce imperfections of a wafer by addressing each section individually. With respect to claim 11, Chang/Foulke/Yang discloses the semiconductor manufacturing method of claim 9. Chang/Foulke/Yang does not explicitly disclose wherein the individually controlling the positions of each of the plurality of divided regions comprises moving the plurality of divided regions of the second adsorbing portion comprises moving the plurality of divided regions along a vertical direction to correspond to the warpage shape of the substrate. In an analogous art, Kato discloses wherein the individually controlling the positions of each of the plurality of divided regions comprises moving the plurality of divided regions of the second adsorbing portion comprises moving the plurality of divided regions along a vertical direction to correspond to the warpage shape of the substrate (Para 0032). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang/Foulke/Yang’s method by having Kato’s disclosure in order to reduce imperfections of a wafer by addressing each section individually. With respect to claim 15, Chang/Foulke/Yang discloses the semiconductor manufacturing method of claim 9. Chang/Foulke/Yang does not explicitly disclose wherein the plurality of divided regions of the second adsorbing portion are provided at an initial position when the substrate is attached to the chuck, and wherein the semiconductor package manufacturing method further comprises: relocating the plurality of divided regions to the initial position; and detaching the substrate from the chuck while the plurality of divided regions of the second adsorbing portioin are provided at the initial position. In an analogous art, Kato discloses wherein the plurality of divided regions of the second adsorbing portion are provided at an initial position when the substrate is attached to the chuck (para 0106), and wherein the semiconductor package manufacturing method further comprises: relocating the plurality of divided regions to the initial position (Para 0109 and 0114); and detaching the substrate from the chuck while the plurality of divided regions of the second adsorbing portioin are provided at the initial position (Para 0059). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang/Foulke/Yang’s method by having Kato’s disclosure in order to reduce imperfections of a wafer by addressing each section individually. Claims 5-6 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chang/Foulke/Yang in view of Kubo. With respect to claim 5, Chang discloses wherein the measuring device is configured to obtain the information about the shape of the substrate, and provide warpage information to the chuck about a warpage type of the substrate (Para 0026 and 0028), movement of each of the plurality of divided regions (Para 0033-0035), and a movement distance (Para 0016). Chang/Foulke/Yang does not explicitly disclose that the measuring device is the scanning device and comprises of a sensor. In an analogous art, Kubo discloses that the measuring device is the scanning device and comprises of a sensor (Page 15, last Para -Page 16 first Para; Page 17, last para). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Chang/Foulke/Yang’s method by having Kubo’s disclosure in order to reduce error rate in semiconductor manufacturing process. With respect to claim 6, Chang discloses measuring a distance between each of the plurality of divided regions and the substrate (0016 and 0026), and wherein the driver is further configured to drive each of the plurality of divided regions based on the distance (Para 0017-0018 and 0028). Chang/Foulke/Yang does not explicitly disclose that the chuck comprises of a sensor configured to perform the measuring step. In an analogous art, Kubo discloses that the chuck comprises of a sensor configured to perform the measuring step (Page 15, last Para -Page 16 first Para; Page 17, last para). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Chang/Foulke/Yang’s method by having Kubo’s disclosure in order to reduce error rate in semiconductor manufacturing process. With respect to claim 13, Chang discloses obtaining the information about the warpage shape of the substrate; and transmitting the information about the warpage shape of the substrate (Para 0026 and 0028), movement of each of the plurality of divided regions of the second adsorbing portion (Para 0033-0035), and a movement distance to the chuck (Para 0016). Chang/Foulke/Yang does not explicitly disclose controlling a sensor to obtain the information. In an analogous art, Kubo discloses controlling a sensor to obtain the information (Page 15, last Para -Page 16 first Para; Page 17, last para). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Chang/Foulke/Yang’s device by having Kubo’s disclosure in order to reduce error rate in semiconductor manufacturing process. With respect to claim 14, Chang discloses obtaining a distance between each of the plurality of divided regions of the second adsorbing portion and the substrate (0016 and 0026), and adjusting heights of the plurality of divided regions of the second adsorbing portion based on the distance (Para 0016; 0023 and 0026). Chang/Foulke/Yang does not explicitly disclose controlling a sensor to obtain the distance. In an analogous art, Kubo discloses controlling a sensor to obtain the distance (Page 15, last Para -Page 16 first Para; Page 17, last para). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Chang/Foulke/Yang’s device by having Kubo’s disclosure in order to reduce error rate in semiconductor manufacturing process. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chang/Foulke/Yang/ Kubo and further in view of Kitaoka (US 2004/0217765, hereinafter Kitaoka). With respect to claim 7, Chang/Foulke/Yang/ Kubo discloses the semiconductor manufacturing method of claim 1. Chang/Foulke/Yang/ Kubo does not explicitly disclose wherein the sensor extends into the chuck. In an analogous art, Kitaoka discloses wherein the sensor extends into the chuck (Para 0007). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Chang/Foulke/Yang/ Kubo’s device by having Kitaoka’s disclosure in order to improve the accuracy of the measurements. Allowable Subject Matter Claim 17. Claims 18-20 are allowed by virtue of dependency on claims 17. The following is an examiner’s statement of reasons for allowance: Regarding claim 17, prior art of record does not disclose or render obvious the “… a driver configured to drive each of the plurality of divided regions, the scanning device includes a first sensor, the chuck includes a second sensor, the semiconductor package manufacturing method comprising: providing the substrate on the chuck; obtaining information indicating a warpage shape of the substrate using the first sensor; identifying a movement distance for each of the plurality of divided regions according to the information; measuring a distance between each of the plurality of divided regions and the substrate using the second sensor; moving each of the plurality of divided regions to an initial position based on the movement distance using the driver; adsorbing the substrate to the chuck based on each of the plurality of divided regions reaching an adsorption distance at which vacuum adsorption is enabled; moving each of the plurality of divided regions back to the initial position; and detaching the substrate from the plurality of divided regions while positioned at the initial position.” when considered as a whole along with all other limitations of claim 17. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Based on new ground of rejection, applicant's arguments filed on 06/12/2026 are moot. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Show 3 earlier events
Oct 08, 2025
Examiner Interview Summary
Nov 25, 2025
Response Filed
Mar 13, 2026
Final Rejection mailed — §103
Apr 24, 2026
Examiner Interview Summary
Apr 24, 2026
Applicant Interview (Telephonic)
Jun 12, 2026
Request for Continued Examination
Jun 17, 2026
Response after Non-Final Action
Jun 25, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
94%
With Interview (+11.9%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 703 resolved cases by this examiner. Grant probability derived from career allowance rate.

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