DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 02/02/2026. Claims 1-20 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 10/04/2022 is acceptable.
Election/Restrictions
Applicant elects Group I, claims 1-12, without traverse, and without prejudice to the presentation of the claims of Groups II and 13-20 “Response to Election / Restriction Filed” filed on 02/02/2026 is acknowledged. In response to the species restriction, Applicant elects Species M.IV: a configurable capacitance chip, as described in Fig. 4 and Applicant respectfully asserts that pending claims 1-12 are each generic.
This office action considers claims 1-20 pending for prosecution, wherein claims 13-20 are withdrawn from further consideration, and 1-12 are presented for examination.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 5-8 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran et al (US 2020/0176427 A1; hereafter Ramachandran) in view of SHEN et al (US 2016/0293534 A1; hereafter SHEN).
PNG
media_image1.png
275
600
media_image1.png
Greyscale
Regarding claim 1. Ramachandran discloses an electronic device (comprising:
a semiconductor substrate (Fig 13, substrate 150, such as silicon substrate, Para [ 0043]) including a first integrally formed capacitor ( Fig 13, left capacitor banks 102, Para [ 0032]) having first and second terminals (Fig 13, left terminals 110 , Para [ 0032]) formed at a bottom surface of the semiconductor substrate (Fig 13, substrate 150, such as silicon substrate, Para [ 0043]), the semiconductor substrate (Fig 13, substrate 150, such as silicon substrate, Para [ 0043]) including a second integrally formed capacitor (Fig 13, right capacitor banks 102 , Para [ 0032]) having third and fourth terminals ( Fig 13, right terminals 110 , Para [ 0032]) formed at the bottom surface of the semiconductor substrate (Fig 13, substrate 150, such as silicon substrate, Para [ 0043]); and
a package substrate (Fig 13, package die 200, Para [ 0039]) attached to the semiconductor substrate (Fig 13, substrate 150, such as silicon substrate, Para [ 0043]) and including:
a first plurality of electrical interconnects (Fig 13, pads 250, Para [ 0045]) formed at a first surface including first, second, third and fourth electrical interconnects (Fig 13, plurality pads 250 , Para [ 0045]) wherein the first electrical interconnect is electrically connected to the first terminal (Fig 13, left terminals 110 , Para [ 0032]), the second electrical interconnect is electrically connected to the second terminal (Fig 13, left terminals 110 , Para [ 0032]), the third electrical interconnect is electrically connected to the third terminal (Fig 13, right terminals 110 , Para [ 0032]) and the fourth electrical interconnect is electrically connected to the fourth terminal (Fig 13, right terminals 110 , Para [ 0032]).
But Ramachandran does not disclose explicitly a second plurality of electrical interconnects formed at a second surface opposite the first surface; and a plurality of electrical conductors coupling the first, second, third and fourth electrical interconnects to two electrical interconnects of the second plurality of electrical interconnects.
PNG
media_image2.png
303
776
media_image2.png
Greyscale
In a similar field of endeavor, SHEN discloses a second plurality of electrical interconnects (Fig. [14], connections 140′, Para [ 0050]) formed at a second surface opposite the first surface (Fig. [14], connections 140′, Para [ 0050]); and a plurality of electrical conductors (Fig. [14], interconnect [1510, 120I.T], Para [ 0057]) coupling the first, second, third and fourth electrical interconnects ( circuit modules 804 includes electrical connection, Para [ 0085]) to two electrical interconnects of the second plurality of electrical interconnects (connections 140′, Para [ 0050]).
Since Ramachandran and SHEN are both from the similar field of endeavor, and SHEN discloses number of ICs and discrete circuits attached to a printed circuit board (PCB). Therefore, the purpose disclosed by SHEN would have been recognized in the pertinent art of Ramachandran.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Ramachandran in light of SHEN teaching “a second plurality of electrical interconnects (Fig. [14], connections 140′, Para [ 0050]) formed at a second surface opposite the first surface (Fig. [14], connections 140′, Para [ 0050]); and a plurality of electrical conductors (Fig. [14], interconnect [1510, 120I.T], Para [ 0057]) coupling the first, second, third and fourth electrical interconnects ( circuit modules 804 includes electrical connection, Para [ 0085]) to two electrical interconnects of the second plurality of electrical interconnects (connections 140′, Para [ 0050])” for further advantage such as improve device performance with reliable interconnect structure.
Regarding claim 5. Ramachandran and SHEN the electronic device of claim 1, SHEN further discloses wherein the second plurality of electrical interconnects (Fig. [14], connections 140′, Para [ 0050]) comprise spherical interconnects arranged to be soldered (Fig. [14], connections 140′, Para [ 0050]) to a separate electronic device (Fig. [14], circuit modules 804 Para [ 0042, 0085]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Ramachandran in light of SHEN teaching “wherein the second plurality of electrical interconnects (Fig. [14], connections 140′, Para [ 0050]) comprise spherical interconnects arranged to be soldered (Fig. [14], connections 140′, Para [ 0050]) to a separate electronic device (Fig. [14], circuit modules 804 Para [ 0042, 0085])” for further advantage such as improve device performance with reliable interconnect structure.
Regarding claim 6. Ramachandran and SHEN the electronic device of claim 1, Ramachandran further discloses wherein the first electrical interconnect (Fig 13, pads 250) is electrically connected to the first terminal ( Fig 13, left terminals 110, Para [ 0032]), the second electrical interconnect (Fig 13, pads 250) is electrically connected to the second terminal (Fig 13, left terminals 110, Para [ 0032]), the third electrical interconnect (Fig 13, pads 250) is electrically connected to the third terminal ( Fig 13, right terminals 110, Para [ 0032]) and the fourth electrical interconnect (Fig 13, pads 250) is electrically connected to the fourth terminal (Fig 13, right terminals 110, Para [ 0032]) via soldered interfaces (Fig 13, solder 162, Para [ 0032]).
Regarding claim 7. Ramachandran discloses an electronic device comprising:
a substrate (Fig 13, substrate 150, such as silicon substrate, Para [ 0043]) including a plurality of integrally formed capacitors (Fig 13, capacitor banks 102, Para [ 0032]), each capacitor having respective electrical terminals (Fig 13, terminals 110, Para [ 0032]) formed at a bottom surface of the substrate (Fig 13, substrate 150, such as silicon substrate, Para [ 0043]); and
a package substrate (Fig 13, package die 200, Para [ 0039]) attached to the substrate (Fig 13, substrate 150, such as silicon substrate, Para [ 0043]) and including:
a plurality of first electrical interconnects (Fig 13, pads 250) formed at a first surface and electrically coupled to the electrical terminals (terminals 110, Para [ 0032]) and a plurality of electrical conductors (Fig 13, IPD routing 120, Para [ 0034]) coupling at least two of the integrally formed capacitors (Fig 13, capacitor banks 102, Para [ 0032]) together.
But Ramachandran does not disclose explicitly a plurality of second electrical interconnects formed at a second surface opposite the first surface.
In a similar field of endeavor, SHEN discloses a plurality of second electrical interconnects (connections 140′, Para [ 0050]) formed at a second surface opposite the first surface (Fig. [14], connections 140′, Para [ 0050]).
Since Ramachandran and SHEN are both from the similar field of endeavor, and SHEN discloses number of ICs and discrete circuits attached to a printed circuit board (PCB). Therefore, the purpose disclosed by SHEN would have been recognized in the pertinent art of Ramachandran. Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ramachandran in light of SHEN teaching “a plurality of second electrical interconnects (connections 140′, Para [ 0050]) formed at a second surface opposite the first surface (Fig. [14], connections 140′, Para [ 0050])” for further advantage such as improve device performance with reliable interconnect structure.
Regarding claim 8. Ramachandran and SHEN the electronic device of claim 7, Ramachandran further discloses wherein the plurality of electrical conductors couple the at least two integrally formed capacitors together in parallel (Fig 13, Para [ 0005-0007]).
Regarding claim 11. Ramachandran and SHEN the electronic device of claim 7, SHEN further discloses wherein the plurality of second electrical interconnects (connections 140′, Para [ 0050]) comprise spherical interconnects arranged to be soldered (connections 140′, Para [ 0050]) to a separate electronic device (circuit modules 804 Para [ 0042, 0085]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ramachandran in light of SHEN teaching “wherein the plurality of second electrical interconnects (connections 140′, Para [ 0050]) comprise spherical interconnects arranged to be soldered (connections 140′, Para [ 0050]) to a separate electronic device (circuit modules 804 Para [ 0042, 0085])” for further advantage such as improve device performance with reliable interconnect structure.
Regarding claim 12. Ramachandran and SHEN the electronic device of claim 7, Ramachandran further discloses wherein the plurality of first electrical interconnects (Fig 13, pads 250) are electrically coupled to the electrical terminals (terminals 110) via soldered interfaces (Fig 13, solder 162, Para [ 0032]).
Claims 2-3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran et al (US 2020/0176427 A1; hereafter Ramachandran) in view of SHEN et al (US 2016/0293534 A1; hereafter SHEN) as applied claims above and further in view of de Rochemont (US 2018/0358295 A1; hereafter Rochemont).
Regarding claim 2. Ramachandran and SHEN the electronic device of claim 1, But Ramachandran and SHEN do not disclose explicitly wherein the plurality of electrical conductors couple the first capacitor in parallel with the second capacitor.
In a similar field of endeavor, Rochemont discloses wherein the plurality of electrical conductors couple the first capacitor in parallel with the second capacitor (Para [ 0063]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ramachandran and SHEN in light of Rochemont teaching “wherein the plurality of electrical conductors couple the first capacitor in parallel with the second capacitor (Para [ 0063])” for further advantage such as improve electrical connectivity of embedded capacitors within a chip stack.
Regarding claim 3. Ramachandran and SHEN the electronic device of claim 1, But Ramachandran and SHEN do not disclose explicitly wherein the plurality of electrical conductors couple the first capacitor in series with the second capacitor.
In a similar field of endeavor, Rochemont discloses wherein the plurality of electrical conductors couple the first capacitor in series with the second capacitor (Para [ 0063]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ramachandran and SHEN in light of Rochemont teaching “wherein the plurality of electrical conductors couple the first capacitor in series with the second capacitor (Para [ 0063])” for further advantage such as improve electrical connectivity of embedded capacitors within a chip stack.
Regarding claim 9. Ramachandran and SHEN the electronic device of claim 7, But Ramachandran and SHEN do not disclose explicitly wherein the plurality of electrical conductors couple the at least two integrally formed capacitors together in series.
In a similar field of endeavor, Rochemont discloses wherein the plurality of electrical conductors couple the first capacitor in series with the second capacitor (Para [ 0063]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ramachandran and SHEN in light of Rochemont teaching “wherein the plurality of electrical conductors couple the first capacitor in series with the second capacitor (Para [ 0063])” for further advantage such as improve electrical connectivity of embedded capacitors within a chip stack.
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran et al (US 2020/0176427 A1; hereafter Ramachandran) in view of SHEN et al (US 2016/0293534 A1; hereafter SHEN) as applied claims above and further in view of Nelson (US 2020/0083186 A1; hereafter Nelson).
Regarding claim 4. Ramachandran and SHEN the electronic device of claim 1, But Ramachandran and SHEN do not disclose explicitly wherein the package substrate comprises a printed circuit board.
In a similar field of endeavor, Nelson discloses wherein the package substrate comprises a printed circuit board (Para [ 0017]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ramachandran and SHEN in light of Nelson teaching “wherein the package substrate comprises a printed circuit board (Para [ 0017])” for further advantage such as improve electrical connection within a chip package.
Regarding claim 10. Ramachandran and SHEN the electronic device of claim 7, But Ramachandran and SHEN do not disclose explicitly wherein the package substrate comprises a printed circuit board.
In a similar field of endeavor, Nelson discloses wherein the package substrate comprises a printed circuit board (Para [ 0017]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ramachandran and SHEN in light of Nelson teaching “herein the package substrate comprises a printed circuit board (Para [ 0017])” for further advantage such as improve electrical connection within a chip package.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
Prosecution Insights