DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the communication filed on 05/13/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 05/13/2026 in reply to the final rejection mailed on 03/18/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered.
Claims 1-7, 12, & 15-20 will be examined in this Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 19 & 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 19, the limitations “at least one interconnection layer disposed on the planarization layer” & “the connection pads are electrically connected to the light emitting device pads through the interconnection layer” in lines 2-3 & 8-9, respectively, raise new matter issues in view of the amended limitation of Claim 18, “wherein the planarization layer covers an entirety of a side surface of at least one of the connection pads,” in lines 18-19.
Claim 19 establishes “at least one interconnection layer disposed on the planarization layer” wherein “the connection pads are electrically connected to the light emitting device pads through the interconnection layer.” The interconnection layers L1 & L2 are discussed (see e.g., Applicant’s Drawings, figs. 29a-c, Applicant’s Specification, para.0231-0234) wherein L1 & L2 are incorporated into the device, but the limitation of Claim 19 requires “the connection pads are electrically connected to the light emitting device pads through the interconnection layer.” Figs. 29a-c show the interconnection layers to be on the side of the light emitting device pads 20pd, 30pd, 40pd, & 50pd in order to connect each of the light emitting device pads together. The incorporation of the interconnection layers L1 & L2 do not foster the connection between the connection pads and the light emitting device pads 20pd, 30pd, 40pd, & 50pd as required by Claim 19. Additionally the at least one interconnection layer L1 & L2 is shown in figures 5 & 7 of the Applicant’s drawings, but the interconnection layers L1 & L2 are physically in between the planarization layer 60/160 and the connection pads 50g1 & 50r2. In these figures, the newly amended limitation “wherein the planarization layer covers an entirety of a side surface of at least one of the connection pads,” would no longer be shown because of the physical separation caused by the interconnection layers.
Regarding Claim 20, the limitations “a first intermediate layer disposed on the planarization layer, and a second intermediate layer disposed on the first intermediate layer” in lines 3-4 raise new matter issues in view of the amended limitation of Claim 18, “wherein the planarization layer covers an entirety of a side surface of at least one of the connection pads,” in lines 18-19.
The first intermediate layer 120 and the second intermediate layer 130 are discussed (see e.g., Applicant’s Drawings, figs. 5 & 7, Applicant’s Specification, para.0102-0103, para.0115) and shown to be incorporated into the device. However, the first and second intermediate layers 120 & 130 are physically in between the planarization layer 60/160 and the connection pads 50g1 & 50r2. In these figures, the newly amended limitation “wherein the planarization layer covers an entirety of a side surface of at least one of the connection pads,” would no longer be shown because of the physical separation caused by the presence of the first and second intermediate layers.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-7, 12, & 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, the limitations “a first light emitter, a second light emitter, and a third light emitter disposed at a position above the circuit board…” and “a planarization layer covering side surfaces and an upper surface of at least a region of the first, second, and third light emitter…” are inconsistent with the device shown in figure 27 of Applicant’s specification. Figure 27 shows the circuit board 1001 incorporated into the display apparatus. Once incorporated, the light emitting devices 100a are flipped upside down and the first limitation “a first light emitter, a second light emitter, and a third light emitter disposed at a position above the circuit board…” is taught. The planarization layer is shown to cover upper surfaces of at least a region of the first, second, and third light emitters of the light emitting devices in figures that do not incorporate the circuit board into the display apparatus, such as in figures 3, 5, 7, 12b, 12c 25b, 26a, 26b, & 28. However, since the light emitting devices are flipped, the planarization layer no longer covers upper surfaces of at least a region of the first, second, and third light emitters of the light emitting devices, rather lower surfaces of said regions. Therefore, Claim 1 is rejected as being indefinite for failing to point out the proper relative position of the circuit board and the coverage of the surfaces by the planarization layer.
Claims 2-7, 12, & 15-17 are rejected as being dependent on Claim 1.
Regarding Claim 12, the limitation “wherein a number of the connection pads is (3n+m) or more and 2 x n x m or less” is unclear as the current claim language does not point out and distinctly claim what the values n & m are. Therefore, Claim 12 is rejected as being indefinite for failing to point out and claim the values of n & m.
Regarding Claim 15, the limitation “at least one of the light emitting device pads disposed on the inner surface of the planarization layer at a first angle,” is unclear as figures 26a-b only shows connection pads 20ce & 30ce disposed on the inner inclined surfaces of the planarization layer. Therefore, Claim 15 is rejected as being indefinite for failing to distinctly claim the position of the at least one of the light emitting device pads.
PNG
media_image1.png
472
1174
media_image1.png
Greyscale
Regarding Claim 16, the limitation “wherein at least one of the connection pads” in lines 1-2 establishes another antecedent basis for the limitation “at least one of the connection pads” established in lines 2-3 of Claim 15, on which Claim 16 depends. It is unclear whether the intention is to refer to another one of the connection pads or the at least one of the connection pads of Claim 15.
Regarding Claim 17, the limitation “wherein a distance between the connection pads formed on the inner surface of the planarization layer” is inconsistent with the figures of the application. The current claim language of Claims 15 & 17 establish a singular inner surface of the planarization layer, not two inclined surfaces as shown in figures 26a-b. Figures 26a-b at most one connection pad formed on one inclined surface of the planarization layer. Therefore, there can be no distance between a plurality of connection pads on the inner surface of the planarization layer because is only one connection pad (20ce or 30ce) formed on the inner surface of the planarization layer 60.
PNG
media_image2.png
472
1109
media_image2.png
Greyscale
Regarding Claim 18, the limitations “a first light emitter, a second light emitter, and a third light emitter disposed at a position above the circuit board…” and “a planarization layer covering side surfaces and an upper surface of the light emitting source…” are inconsistent with the device shown in figure 27 of Applicant’s specification. Figure 27 shows the circuit board 1001 incorporated into the display apparatus. Once incorporated, the light emitting devices 100a are flipped upside down and the first limitation “a first light emitter, a second light emitter, and a third light emitter disposed at a position above the circuit board…” is taught. The planarization layer is shown to cover an upper surface of the light emitting source of the light emitting devices in figures that do not incorporate the circuit board into the display apparatus, such as in figures 3, 5, 7, 12b, 12c 25b, 26a, 26b, & 28. However, since the light emitting devices are flipped, the planarization layer no longer covers an upper surface of the light emitting source of the light emitting devices, rather a lower surface. Therefore, Claim 18 is rejected as being indefinite for failing to point out the proper relative position of the circuit board and the coverage of the surfaces by the planarization layer.
Regarding Claim 19, the limitation “the planarization layer covers side surfaces and upper surfaces of the plurality of light emitting regions” is inconsistent with the device shown in figure 27 of Applicant’s specification. Figure 27 shows the circuit board 1001 incorporated into the display apparatus as required by Claim 18, on which Claim 19 depends. Once incorporated, the light emitting devices 100a comprising the plurality of light emitting regions are flipped upside down. The planarization layer is shown to cover an upper surface of the light emitting regions of the light emitting devices in figures that do not incorporate the circuit board into the display apparatus, such as in figures 3, 5, 7, 12b, 12c 25b, 26a, 26b, & 28. However, since the light emitting devices are flipped, the planarization layer no longer covers an upper surface of the light emitting source of the light emitting devices, rather lower surfaces. Therefore, Claim 19 is rejected as being indefinite for failing to point out the proper coverage of the surfaces by the planarization layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Jang T (US 20230069883).
Regarding Claim 1, Jang T (see, e.g., fig. 63) shows a display apparatus, comprising:
a light emitting device AA, BB, & CC (see, e.g., fig. 63, para.0223):
and a bump pad 92Ac, 93Ac, 93Bc, & 93Cc (see, e.g., para.0223) electrically connected to the light emitting device:
wherein the light emitting device AA, BB, & CC (see, e.g., fig. 63) includes:
a first light emitter AA,
a second light emitter CC,
and a third light emitter BB
disposed at a position between the first light emitter and the second light emitter (BB horizontally in between AA & CC, see, e.g., fig. 63):
a planarization layer 76 (see, e.g., para.0225) covering side surfaces and an upper surface of at least a region of the first, second and third light emitter such that the planarization layer completely surrounds at least a portion of each of the first, second, and third light emitter (see, e.g., annotated figure 1);
and light emitting device pads 92Aa & 92Ca including
a first pad 92Aa (see, e.g., para.0225) electrically connected with the first light emitter AA,
and a second pad 92Ca (see, e.g., para.0225) electrically connected to the second light emitter CC;
and connection pads 92Ab & 92Cb, disposed on the planarization layer;
wherein the planarization layer 76 covers an entirety of a side surface of at least one of the connection pads 92Ab & 92Cb (see, e.g., annotated figure 2),
and wherein the connection pads are electrically connected to the light emitting device pads through the planarization layer (connection happens in the openings of the planarization layer where there is direct contact between the elements to form an electrical connection, see, e.g., fig. 63, para.0223),
and wherein at least a region of each of the connection pads 92Ab & 92Cb extends from an upper region of the light emitting device to an inner surface of the planarization layer formed between the planarization layer and the light emitting device (see, e.g., annotated figure 3)
PNG
media_image3.png
346
503
media_image3.png
Greyscale
PNG
media_image4.png
346
568
media_image4.png
Greyscale
PNG
media_image5.png
457
887
media_image5.png
Greyscale
Jang T in the first embodiment of fig. 63, however, fails to show
a circuit board:
the light emitting device disposed on the circuit board
and the bump pad electrically connected to the circuit board
the first light emitter, the second light emitter, and the third light emitter, disposed at a position above the circuit board
Jang T (see, e.g., fig. 27, para.0130) in a second embodiment of fig. 27 similar to the first embodiment of fig. 63, teaches that a circuit board 98 incorporated into the display apparatus would be advantageous in the case of the display apparatus’ failure as the inspection and replacement would be first performed package level rather than repairing individual elements, such as the light emitters of the light-emitting device. Fig. 27 of Jang T does not show the circuit board 98 incorporated in the device but states “with this configuration, a plurality of light emitting device chips can be combined into one package and connected to the external power supply 98 (e.g., the submount, the interposer, the wiring board, the display pixel, or the like) as shown in Fig. 25.”
The circuit board 98 is incorporated into the device of Jang T, first embodiment of fig. 63.
The combination of Jang T’s first embodiment of fig. 63 and the circuit board 98 of the second embodiment of fig. 27 shows the following limitations in annotated figure 4,
the light emitting device AA, BB, & CC disposed on the circuit board 98
and the bump pad 92Ac, 93Ac, 93Bc, & 93Cc electrically connected to the circuit board 98
the first light emitter AA, the second light emitter CC, and the third light emitter BB, disposed at a position above the circuit board 98
PNG
media_image6.png
839
1987
media_image6.png
Greyscale
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the circuit board 98 of the second embodiment of fig. 27 in the first embodiment of fig. 63 of Jang T in the case of the display apparatus’ failure as the inspection and replacement process would be performed first on the package level rather than repairing individual elements, such as the light emitters of the light emitting device.
Regarding Claim 2, Jang T (see, e.g., fig. 63, para.0223) shows the display apparatus of claim 1,
wherein: the planarization layer 76 has an opening (see, e.g., annotated figure 5) exposing the light emitting device pads 92Aa & 92Ca;
and the connection pads 92Ab & 92Cb are electrically connected to the light emitting device pads 92Aa & 92Ca through the opening (see, e.g., annotated figure 5).
PNG
media_image7.png
414
877
media_image7.png
Greyscale
Regarding Claim 3, Jang T (see, e.g., fig. 63, para.0225) shows the display apparatus of claim 2,
further comprising a protection layer 99 (encapsulant, see, e.g., para.0225) covering the opening.
Regarding Claim 4, Jang T (see, e.g., fig. 63, para.0225) shows the display apparatus of claim 3,
wherein the protection layer 99 covers the connection pads 92Ab & 92Cb,
and has openings exposing the connection pads (near the base of 92Ac, 93Ac, 93Bc, & 93Cc, see, e.g., annotated figure 6).
PNG
media_image8.png
414
877
media_image8.png
Greyscale
Regarding Claim 5, Jang T (see, e.g., fig. 63, para.0224) shows the display apparatus of claim 1,
further comprising: a transparent substrate 80 (see, e.g., para.0224);
and an adhesive layer 81 (see, e.g., para.0224) disposed between the transparent substrate and the light emitting device (see, e.g., fig. 63).
Regarding Claim 6, Jang T (see, e.g., fig. 63, para.0223) shows the display apparatus of claim 5,
further comprising a light blocking layer BM disposed on the transparent substrate to define a light emitting region (see, e.g., annotated figure 7),
wherein the light emitting device AA, BB, & CC is disposed on the light emitting region (see, e.g., annotated figure 7).
PNG
media_image9.png
452
877
media_image9.png
Greyscale
Claims 7, & 15 are rejected under 35 U.S.C. 103 as being unpatentable over by Jang T (US 20230069883) in view of Jang (US 20200365568).
Regarding Claim 7, Jang T (see, e.g., fig. 63) shows the display apparatus of claim 1,
Jang T, however, fails to show
wherein the light emitting device AA, BB, & CC is formed in plural.
Jang (see, e.g., fig. 13, para.0113), in a similar device to Jang T, shows
wherein the light emitting device 100 is formed in plural
Jang teaches a configuration of a plurality of light emitting devices 100 formed over a circuit board 11p similar to the device of Jang T (see, e.g., annotated figure 4) which shows a light emitting device AA, BB, & CC, formed over a circuit board 98. The plurality of the light emitting devices of Jang is incorporated into the device of Jang T.
It would have been obvious to one of ordinary skill in the art to incorporate the plurality of light emitting devise of Jang, in the device of Jang T, to form a plurality of light emitting devices in a display apparatus because the combination is a simple substitution to obtain predictable results – a simple substitution of display apparatus with one light emitting device for a display apparatus with a plurality of light emitting devices.
Regarding Claim 15, Jang T (see, e.g., fig. 63) shows the display apparatus of claim 2,
Jang T, however, fails to show
wherein an inner surface of the planarization layer defining the opening includes an inclined surface,
and at least one of the connection pads disposed on an upper surface of the planarization layer is connected to at least one of the light emitting device pads disposed on the inner surface of the planarization layer at a first angle.
Jang (see, e.g., fig. 1c, para.0083), in a similar device to Jang T, teaches a configuration wherein
wherein a surface of the planarization layer 90 (see, e.g., para.0083) defining the opening 40ct & 40CH (see, e.g., para.0073) includes an inclined surface (inclined by angle G, see, e.g., para.0104),
and at least one of the connection pads 40ce & 40C (see, e.g., para.0075-0077) disposed on an upper surface of the planarization layer is connected to at least one of the light emitting device pads disposed on the surface of the planarization layer 90 at a first angle G (see, e.g., para.0104).
Jang (see, e.g., para.0079) teaches the inclined angle and inclined surface of the planarization layer, its openings, and configuration with the connection pads would improve adhesion of the overall device to the circuit board. The inclined surface and the first angle of the device of Jang is incorporated into the device of Jang T.
The combination of Jang and Jang T teaches,
wherein an inner surface (left surface of the opening) of the planarization layer 76 defining the opening includes an inclined surface (inclined by angle G),
and at least one of the connection pads 92Cb disposed on an upper surface (top surface) of the planarization layer 76 is connected to at least one of the light emitting device pads 92Ca disposed on the inner surface of the planarization layer at a first angle G.
PNG
media_image10.png
800
1058
media_image10.png
Greyscale
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Jang, of the inclined angle and inclined surface of a planarization layer, in the device of Jang T to improve adhesion of the overall device to the circuit board.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20230069883).
Regarding Claim 18, Jang T shows a display apparatus, comprising:
and a light emitting device (the entire device of the embodiment shown in fig. 63, see, e.g., fig. 63, para.0223),
wherein the light emitting device comprises:
a light emitting source AA, BB, & CC;
a planarization layer 76 (see, e.g., para.0225) covering side surfaces and an upper surface of the light emitting source AA, BB, & CC;
and connection pads 92Ab, 92Bb, & 92Cb disposed on the planarization layer;
wherein the light emitting source comprises:
a first light emitter AA,
a second light emitter CC,
and a third light emitter BB
disposed at a position above the circuit board between the first light emitter and second light emitter (BB horizontally in between AA & CC, see, e.g., fig. 63),
wherein the planarization layer 76 completely surrounds at least a portion of each of the first, second, and third light emitter AA, BB & CC (see, e.g., annotated figure 9);
and light emitting device pads 92Aa, 92Ca, & 92Ba electrically connected to the first, second, and third light emitter,
wherein the connection pads are electrically connected to the light emitting device pads through the planarization layer (through openings of the planarization layer 76),
wherein the planarization layer 76 covers an entirety of a side surface of at least one of the connection pads 92Ab, 92Bb, & 92Cb (see, e.g., annotated figure 9),
PNG
media_image11.png
545
933
media_image11.png
Greyscale
and wherein at least a portion of each of the connection pads is disposed on the planarization layer outside of an upper region of the light emitting source (each pad is disposed above of the light emitting source, see, e.g., fig. 63),
Jang T in the first embodiment of fig. 63, however, fails to show
a circuit board;
and the light emitting device disposed on the circuit board
and wherein the connection pads are bonded to the circuit board.
Jang T (see, e.g., fig. 27, para.0130) in a second embodiment of fig. 27 similar to the first embodiment of fig. 63, teaches that a circuit board 98 incorporated into the display apparatus would be advantageous in the case of the display apparatus’ failure as the inspection and replacement would be first performed package level rather than repairing individual elements, such as the light emitters of the light-emitting device. Fig. 27 of Jang T does not show the circuit board 98 incorporated in the device but states “with this configuration, a plurality of light emitting device chips can be combined into one package and connected to the external power supply 98 (e.g., the submount, the interposer, the wiring board, the display pixel, or the like) as shown in Fig. 25.”
The circuit board 98 is incorporated into the device of Jang T, first embodiment of fig. 63.
The combination of Jang T’s first embodiment of fig. 63 and the circuit board 98 of the second embodiment of fig. 27 shows the following limitations in annotated figure 10,
a circuit board 98;
and the light emitting device (the entire device of the embodiment shown in fig. 63) disposed on the circuit board 98
and wherein the connection pads 92Ab, 92Bb, & 92Cb are bonded to the circuit board 98 (connection pads are indirectly bonded to the circuit board through elements 92Ac, 93Ac, 93Bc, & 93Cc).
PNG
media_image12.png
839
1987
media_image12.png
Greyscale
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the circuit board 98 of the second embodiment of fig. 27 in the first embodiment of fig. 63 of Jang T in the case of the display apparatus’ failure as the inspection and replacement process would be performed first on the package level rather than repairing individual elements, such as the light emitters of the light emitting device.
Response to Arguments
Applicant’s arguments, see page 7, filed 05/13/2026, with respect to the objections to claim 12 have been fully considered and are persuasive. The objections to claim 12 have been withdrawn.
Applicant's arguments with respect to the claim rejections under 35 U.S.C. 102 & 103 have been fully considered but they are not persuasive. The prior art of record (Jang T) overcome the amendments of Claims 1 & 18 as shown in paragraphs 23-53 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights