DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Applicant's response to the Office Non-Final Action filed on 3/5/2026 is acknowledged. Applicant amended claims 1, 2, 11, 15, 16, and 20. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 and 4-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2018/0315667) (hereafter Kwon), in view of Chiang et al. (US 20200294863) (hereafter Chiang). Regarding claim 1 , Kwon discloses a semiconductor device, comprising: a first active pattern (101 of PFET in Fig. 9, paragraph 0029) and a second active pattern (101 of NFET in Fig. 9, paragraph 0029) respectively on a first region (region where PFET is formed in Fig. 9) and a second region (region where NFET is formed in Fig. 9) of a substrate 100 (Fig. 9, paragraph 0029); a first channel pattern (102 of PFET in Fig. 9, paragraph 0030) on the first active pattern (101 of PFET in Fig. 9), the first channel pattern (102 of PFET in Fig. 9) including first semiconductor patterns (102 of PFET in Fig. 9) stacked to be spaced apart from each other; a second channel pattern (102 of NFET in Fig. 9, paragraph 0030) on the second active pattern (101 of NFET in Fig. 9), the second channel pattern (102 of NFET in Fig. 9) including second semiconductor patterns (102 of NFET in Fig. 9) stacked to be spaced apart from each other; and a gate electrode (501-503 in Fig. 9) on the first channel pattern (102 of PFET in Fig. 9) and the second channel pattern (102 of NFET in Fig. 9), the gate electrode extending in a first direction (Y direction in Fig. 9), wherein the gate electrode (501-503 in Fig. 9) includes a first outer gate electrode (501-503 of PFET in Fig. 9) and a second outer gate electrode (502-503 of NFET in Fig. 9) on a top surface of an uppermost one of the first semiconductor patterns (102 of PFET in Fig. 9) and a top surface of an uppermost one of the second semiconductor patterns (102 of NFET in Fig. 9), respectively, each of the first outer gate electrode (501-503 of PFET in Fig. 9) and the second outer gate electrode (502-503 of NFET in Fig. 9) including a first metal pattern (lower “TiN” of 502 in Fig. 9; and see paragraph 0053, wherein “second WFM 502 may include TiN/TiAlC/TiN”), a second metal pattern (“TiAlC” of 502 in Fig. 9; and see paragraph 0053, wherein “second WFM 502 may include TiN/TiAlC/TiN”) on the first metal pattern (lower “TiN” of 502 in Fig. 9), and a filling metal pattern 503 (Fig. 9, paragraph 0055) on the second metal pattern (“TiAlC” of 502 in Fig. 9), wherein the first outer gate electrode (501-503 of PFET in Fig. 9) further includes a third metal pattern (501 of PFET in Fig. 9, paragraph 0037) between the first metal pattern (lower “TiN” of 502 in Fig. 9) and the first semiconductor patterns (101 of PFET in Fig. 9), the third metal pattern (501 of PFET in Fig. 9, paragraph 0037, wherein “p-type WFM”) including a p-type work function metal, wherein the second metal pattern (“TiAlC” of 502 in Fig. 9; and see paragraph 0053, wherein “The second WFM 502 may be n-type WFM (NWFM), and may include, for example…titanium aluminum carbide (TiAlC)”) includes an n-type work function metal, a thickness of the first metal pattern (lower “TiN” of 502 in Fig. 9; and see paragraph 0053, wherein “second WFM 502 may include TiN/TiAlC/TiN”) being smaller (see paragraph 0053, wherein “second WFM 502 may include a thin layer which includes a material of the first WFM 501, and a relatively thicker layer which includes a material of the n-type WFM on top of the thin layer”) than a thickness of the second metal pattern (“TiAlC” of 502 in Fig. 9), and wherein a topmost surface of the first metal pattern (lower “TiN” of 502 in Fig. 9) of the second outer gate electrode (502-503 of NFET in Fig. 9) is coplanar with a topmost surface of the second metal pattern (“TiAlC” of 502 in Fig. 9) of the second outer gate electrode (502-503 of NFET in Fig. 9). Kwon does not disclose a lower surface of the filling metal pattern in a region that vertically overlaps the first channel pattern is at a lower level than a topmost surface of the third metal pattern in the region that vertically overlaps the first channel pattern. Chiang disclose s a lower surface of the filling metal pattern 148 (Fig. 2R-2, paragraph 0060) in a region that vertically overlaps the first channel pattern 122 (Fig. 2R-2, paragraph 0061) is at a lower level than a topmost surface of the third metal pattern 144 (Fig. 2R-2, paragraph 0062) in the region that vertically overlaps the first channel pattern 122 (Fig. 2R-2) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon to form a lower surface of the filling metal pattern in a region that vertically overlaps the first channel pattern is at a lower level than a topmost surface of the third metal pattern in the region that vertically overlaps the first channel pattern, as taught by Chiang, since a gate structure (Chiang, paragraph 0002) is formed over and along the sides of the fin (e.g., wrapping) utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices. Regarding claim 4 , Kwon further discloses the semiconductor device as claimed in claim 1, wherein a lowermost level of a top surface of the first outer gate electrode (501-503 of PFET in Fig. 9) is at a substantially same level (see Fig. 9, wherein the lowermost top surface of 501 of PFET below the lowest 102 and the lowermost top surface of 502 of NFET below the lowest 102 are at same level) as a lowermost level of a top surface of the second outer gate electrode (502-503 of NFET in Fig. 9). Regarding claim 5 , Kwon further discloses the semiconductor device as claimed in claim 1, wherein the second outer gate electrode (502-503 of NFET in Fig. 9) has a flat top surface. Regarding claim 6 , Kwon further discloses the semiconductor device as claimed in claim 1, wherein the first metal pattern (lower “TiN” of 502 in Fig. 9) includes titanium nitride, and a thickness of the first metal pattern (lower “TiN” of 502 in Fig. 9) is smaller (see Fig. 9, wherein horizontal length of a portion of 502 of PFET formed between 501 is smaller than horizontal length of 501 of PFET) than a thickness of the third metal pattern (501 of PFET in Fig. 9). Regarding claim 7 , Kwon further discloses the semiconductor device as claimed in claim 6, wherein: the second metal pattern (“TiAlC” of 502 in Fig. 9) includes at least one of aluminum-doped titanium carbide, aluminum-doped tantalum carbide, aluminum-doped vanadium carbide, silicon-doped titanium carbide, and silicon-doped tantalum carbide, and the third metal pattern (501 of PFET in Fig. 9, paragraph 0053, wherein “TiN”) includes at least one of titanium nitride, tantalum nitride, titanium oxynitride, titanium silicon nitride, titanium aluminum nitride, tungsten carbon nitride, and molybdenum nitride. Regarding claim 8 , Kwon further discloses the semiconductor device as claimed in claim 1, wherein the third metal pattern (501 of PFET in Fig. 9) has a recessed topmost surface (see Fig. 9, wherein lower top surface of 501 contacting 502), the recessed topmost surface (see Fig. 9, wherein lower top surface of 501 contacting 502) being at a level lower than a topmost surface of the first outer gate electrode (501-503 of PFET in Fig. 9), and the first metal pattern (lower “TiN” of 502 in Fig. 9) covering the recessed topmost surface (see Fig. 9, wherein lower top surface of 501 contacting 502). Regarding claim 9 , Kwon further discloses the semiconductor device as claimed in claim 1, wherein a thickness of each of the first metal pattern (lower “TiN” of 502 in Fig. 9) and the second metal pattern (“TiAlC” of 502 in Fig. 9) of the first outer gate electrode (501-503 of PFET in Fig. 9) is substantially equal to a thickness of each of the first metal pattern (lower “TiN” of 502 in Fig. 9) and the second metal pattern (“TiAlC” of 502 in Fig. 9) of the second outer gate electrode (502-503 of NFET in Fig. 9). Regarding claim 10 , Kwon further discloses the semiconductor device as claimed in claim 1, wherein: the gate electrode (501-503 in Fig. 9) further includes first inner gate electrodes (501 formed between 102 of PFET in Fig. 9, paragraph 0053) in spaces between the first semiconductor patterns (102 of PFET in Fig. 9), and second inner gate electrodes (502 formed between 102 of NFET in Fig. 9) in spaces between the second semiconductor patterns (102 of NFET in Fig. 9), each of the first inner gate electrodes includes the third metal pattern (501 of PFET in Fig. 9), and each of the second inner gate electrodes (502 formed between 102 of NFET in Fig. 9) includes the first metal pattern (lower “TiN” of 502 in Fig. 9) and the second metal pattern (“TiAlC” of 502 in Fig. 9). Regarding claim 11 , Kwon discloses a semiconductor device, comprising: a substrate 100 (Fig. 9, paragraph 0032) including a first region (PFET in Fig. 9) and a second region (NFET in Fig. 9) adjacent to each other in a first direction (Y direction in Fig. 9); a first active pattern (101 of PFET in Fig. 9, paragraph 0029) on the first region (PFET in Fig. 9) and a second active pattern (101 of NFET in Fig. 9, paragraph 0029) on the second region (NFET in Fig. 9); a first channel pattern (102 of PFET in Fig. 9, paragraph 0030) on the first active pattern (101 of PFET in Fig. 9) and a second channel pattern (102 of NFET in Fig. 9, paragraph 0030) on the second active pattern (101 of NFET in Fig. 9), the first channel pattern (102 of PFET in Fig. 9) including first semiconductor patterns (102 of PFET in Fig. 9), which are stacked to be spaced apart from each other, and the second channel pattern (102 of NFET in Fig. 9) including second semiconductor patterns (102 of NFET in Fig. 9), which are stacked to be spaced apart from each other; a gate electrode (501-503 in Fig. 9) crossing the first channel pattern (102 of PFET in Fig. 9) and the second channel pattern (102 of NFET in Fig. 9), the gate electrode extending in the first direction (Y direction in Fig. 9), and the gate electrode (501-503 in Fig. 9) including a first gate portion (501-503 of PFET in Fig. 9) on the first region (PFET in Fig. 9) and a second gate portion (502-503 of NFET in Fig. 9) on the second region (NFET in Fig. 9); and a gate insulating layer 301 (Fig. 9, paragraph 0034) between the gate electrode (501-503 in Fig. 9) and each of the first channel pattern (102 of PFET in Fig. 9) and the second channel pattern (102 of NFET in Fig. 9), wherein each of the first gate portion (501-503 of PFET in Fig. 9) and the second gate portion (502-503 of NFET in Fig. 9) includes a first metal pattern (lower “TiN” of 502 in Fig. 9; and see paragraph 0053, wherein “second WFM 502 may include TiN/TiAlC/TiN”), a second metal pattern (“TiAlC” of 502 in Fig. 9; and see paragraph 0053, wherein “second WFM 502 may include TiN/TiAlC/TiN”) on the first metal pattern (lower “TiN” of 502 in Fig. 9), and a filling metal pattern 503 (Fig. 9, paragraph 0055) on the second metal pattern (“TiAlC” of 502 in Fig. 9), wherein the first gate portion (501-503 of PFET in Fig. 9) further includes a third metal pattern (501 of PFET in Fig. 9, paragraph 0037) between the first metal pattern (lower “TiN” of 502 in Fig. 9) and the first channel pattern (102 of PFET in Fig. 9), the third metal pattern (501 of PFET in Fig. 9, paragraph 0037, wherein “p-type WFM”) including a p-type work function metal, wherein the second metal pattern (“TiAlC” of 502 in Fig. 9; and see paragraph 0053, wherein “The second WFM 502 may be n-type WFM (NWFM), and may include, for example…titanium aluminum carbide (TiAlC)”) includes an n-type work function metal, the second metal pattern (“TiAlC” of 502 in Fig. 9) being spaced apart from an inner side surface of the gate insulating layer 301 (Fig. 9) by the first metal pattern (lower “TiN” of 502 in Fig. 9), wherein a thickness of the first metal pattern (lower “TiN” of 502 in Fig. 9) is smaller than (see Fig. 9, wherein horizontal length of a portion of 502 of PFET formed between 501 is smaller than horizontal length of 501 of PFET and horizontal length of a portion of 502 of PFET formed above the topmost surface of 501) a thickness of each of the second metal pattern (“TiAlC” of 502 in Fig. 9) and the third metal pattern (501 of PFET in Fig. 9) and wherein a topmost surface of the first metal pattern (lower “TiN” of 502 in Fig. 9) is flat. Kwon does not disclose a lower surface of the filling metal pattern in a region that vertically overlaps the first channel pattern is at a lower level than a topmost surface of the third metal pattern in the region that vertically overlaps the first channel pattern. Chiang discloses a lower surface of the filling metal pattern 148 (Fig. 2R-2, paragraph 0060) in a region that vertically overlaps the first channel pattern 122 (Fig. 2R-2, paragraph 0061) is at a lower level than a topmost surface of the third metal pattern 144 (Fig. 2R-2, paragraph 0062) in the region that vertically overlaps the first channel pattern 122 (Fig. 2R-2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon to form a lower surface of the filling metal pattern in a region that vertically overlaps the first channel pattern is at a lower level than a topmost surface of the third metal pattern in the region that vertically overlaps the first channel pattern, as taught by Chiang, since a gate structure (Chiang, paragraph 0002) is formed over and along the sides of the fin (e.g., wrapping) utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices. Regarding claim 12 , Kwon further discloses the semiconductor device as claimed in claim 11, wherein the third metal pattern (501 of PFET in Fig. 9) is between the first semiconductor patterns (102 of PFET in Fig. 9), and the first metal pattern (lower “TiN” of 502 in Fig. 9) and the second metal pattern (“TiAlC” of 502 in Fig. 9) are between the second semiconductor patterns (102 of NFET in Fig. 9). Regarding claim 13 , Kwon further discloses the semiconductor device as claimed in claim 11, wherein the topmost surface of the first metal pattern (lower “TiN” of 502 in Fig. 9) is at a level higher than a topmost surface of the third metal pattern (501 of PFET in Fig. 9). Regarding claim 14 , Kwon further discloses the semiconductor device as claimed in claim 11, wherein the first region (PFET in Fig. 9) is a PMOSFET region, and the second region (NFET in Fig. 9) is an NMOSFET region. Regarding claim 15 , Kwon further discloses the semiconductor device as claimed in claim 11, wherein the topmost surface of the first metal pattern (lower “TiN” of 502 in Fig. 9) is coplanar with a topmost surface of the second metal pattern (“TiAlC” of 502 in Fig. 9) , and wherein the gate insulating layer 301 (Fig. 9) directly contacts (see I-I’ cross sectional view of Fig. 9, bottom 301 contacts 501 and 502) a side surface of the third metal pattern 501 (Fig. 9) and a side surface of the first metal pattern (lower “TiN” of 502 in Fig. 9). Kwon does not disclose the topmost surface of the first metal pattern is coplanar with a topmost surface of the gate insulating layer. Chiang discloses the topmost surface of the first metal pattern 146 (Fig. 2R-2, paragraph 0057) is coplanar with a topmost surface of the gate insulating layer 142 (Fig. 2R-2, paragraph 0038). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon to form the topmost surface of the first metal pattern is coplanar with a topmost surface of the gate insulating layer, as taught by Chiang, since a gate structure (Chiang, paragraph 0002) is formed over and along the sides of the fin (e.g., wrapping) utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices. Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Chiang as applied to claim 1 above, and further in view of Lee et al. (US 2017/0110542) (hereafter Lee542). Regarding claim 2 , Kwon further discloses the semiconductor device as claimed in claim 1, further comprising a gate insulating layer 301 (Fig. 9, paragraph 0034) between the gate electrode (501-503 in Fig. 9) and the first semiconductor patterns (102 of PFET in Fig. 9) and the second semiconductor patterns (102 of NFET in Fig. 9), wherein the gate insulating layer 301 (Fig. 9) includes an interface layer (“a silicon oxide layer” of 301 in Fig. 9; and see paragraph 0035, wherein “The dielectric layer 301 may include, for example, a silicon oxide layer, a high-k dielectric layer, or a combination thereof”) and a high-k dielectric layer (“high-k dielectric layer” of 301 in Fig. 9), the gate insulating layer 301 (Fig. 9) enclosing the first semiconductor patterns (102 of PFET in Fig. 9) and the second semiconductor patterns (102 of NFET in Fig. 9 ) , and wherein the high-k dielectric layer 301 (Fig. 9) directly contacts (see I-I’ cross sectional view of Fig. 9, bottom 301 contacts 501 and 502) a side surface of the third metal pattern 501 (Fig. 9) and a side surface of the first metal pattern (lower “TiN” of 502 in Fig. 9; and see paragraph 0053, wherein “second WFM 502 may include TiN/TiAlC/TiN”) . Kwon and Chiang do not disclose a topmost surface of the high-k dielectric layer is coplanar with the topmost surface of the first metal pattern. Lee542 discloses a topmost surface of the high-k dielectric layer 82 (Fig. 1, paragraph 0069) is coplanar (see paragraph 0019, wherein “Upper ends of the gate dielectric layer, the work function layer, and the low resistance layer may be substantially the same plane”) with the topmost surface of the first metal pattern 85 (Fig. 1, paragraph 0070). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon in view of Chiang to form a topmost surface of the high-k dielectric layer is coplanar with the topmost surface of the first metal pattern, as taught by Lee542, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose , 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff , 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Regarding claim 3 , Kwon further discloses the semiconductor device as claimed in claim 2, wherein the second metal pattern (“TiAlC” of 502 in Fig. 9; and see paragraph 0053, wherein “second WFM 502 may include TiN/TiAlC/TiN”) is spaced apart from an inner side surface of the high-k dielectric layer (“high-k dielectric layer” of 301 in Fig. 9; and see paragraph 0035, wherein “The dielectric layer 301 may include, for example, a silicon oxide layer, a high-k dielectric layer, or a combination thereof”) by the first metal pattern (lower “TiN” of 502 in Fig. 9). Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2018/0315667) (hereafter Kwon), in view of Lee et al. (US 2021/0043730) (hereafter Lee730) , in further view of Chiang et al. (US 20200294863) (hereafter Chiang) . Regarding claim 16 , Kwon discloses a semiconductor device, comprising: a first active pattern (101 of PFET in Fig. 9, paragraph 0029) and a second active pattern (101 of NFET in Fig. 9, paragraph 0029) on a first region and a second region (region where NFET is formed in Fig. 9) of a substrate (101 of PFET in Fig. 9, paragraph 0029), respectively, the first region (region where PFET is formed in Fig. 9) and the second region (region where NFET is formed in Fig. 9) being PMOSFET and NMOSFET regions, respectively; a device isolation layer 201 (Fig. 9, paragraph 0033) filling a trench (region between 100 in Fig. 9) between the first active pattern (101 of NFET in Fig. 9) and the second active pattern (101 of PFET in Fig. 9); a first channel pattern (102 of PFET in Fig. 9, paragraph 0030) on the first active pattern (101 of PFET in Fig. 9) and a second channel pattern (102 of NFET in Fig. 9, paragraph 0030) on the second active pattern (101 of NFET in Fig. 9), the first channel pattern (102 of PFET in Fig. 9) including first semiconductor patterns (102 of PFET in Fig. 9), which are stacked to be spaced apart from each other, and the second channel pattern (102 of NFET in Fig. 9) including second semiconductor patterns (102 of NFET in Fig. 9), which are stacked to be spaced apart from each other; a gate electrode (501-503 in Fig. 9) crossing the first channel pattern (102 of PFET in Fig. 9) and the second channel pattern (102 of NFET in Fig. 9), the gate electrode (501-503 in Fig. 9) extending in a first direction (Y direction in Fig. 9) and including: first inner gate electrodes (501 formed between 102 of PFET in Fig. 9, paragraph 0053) between the first semiconductor patterns (102 of PFET in Fig. 9), second inner gate electrodes (502 formed between 102 of NFET in Fig. 9) between the second semiconductor patterns (102 of NFET in Fig. 9), a first outer gate electrode (501-503 of PFET in Fig. 9) on a top surface of an uppermost one of the first semiconductor patterns (102 of PFET in Fig. 9), and a second outer gate electrode (502-503 of NFET in Fig. 9) on a top surface of an uppermost one of the second semiconductor patterns (102 of NFET in Fig. 9); a gate insulating layer 301 (Fig. 9, paragraph 0034) between the gate electrode (501-503 in Fig. 9) and each of the first channel pattern (102 of PFET in Fig. 9) and the second channel pattern (102 of NFET in Fig. 9), the gate insulating layer 301 (Fig. 9) including an interface layer (“a silicon oxide layer” of 301 in Fig. 9; and see paragraph 0035, wherein “The dielectric layer 301 may include, for example, a silicon oxide layer, a high-k dielectric layer, or a combination thereof”) enclosing the first (102 of PFET in Fig. 9) and second semiconductor patterns (102 of NFET in Fig. 9) and a high-k dielectric layer (“high-k dielectric layer” of 301 in Fig. 9; and see paragraph 0035, wherein “The dielectric layer 301 may include, for example, a silicon oxide layer, a high-k dielectric layer, or a combination thereof”) on the interface layer (“a silicon oxide layer” of 301 in Fig. 9); wherein each of the first outer gate electrode (501-503 of PFET in Fig. 9) and the second outer gate electrode (502-503 of NFET in Fig. 9) includes a first metal pattern (lower “TiN” of 502 in Fig. 9; and see paragraph 0053, wherein “second WFM 502 may include TiN/TiAlC/TiN”), a second metal pattern (“TiAlC” of 502 in Fig. 9; and see paragraph 0053, wherein “second WFM 502 may include TiN/TiAlC/TiN”) on the first metal pattern (lower “TiN” of 502 in Fig. 9), and a filling metal pattern 503 (Fig. 9, paragraph 0055) on the second metal pattern (“TiAlC” of 502 in Fig. 9), wherein the first outer gate electrode (501-503 of PFET in Fig. 9) further includes a third metal pattern (501 of PFET in Fig. 9, paragraph 0037) between the first metal pattern (lower “TiN” of 502 in Fig. 9) and the first semiconductor patterns (102 of PFET in Fig. 9), the third metal pattern (501 of PFET in Fig. 9, paragraph 0037, wherein “p-type WFM”) including a p-type work function metal, wherein the second metal pattern (“TiAlC” of 502 in Fig. 9; and see paragraph 0053, wherein “The second WFM 502 may be n-type WFM (NWFM) includes an n-type work function metal, wherein a thickness of the first metal pattern (lower “TiN” of 502 in Fig. 9) is smaller than (see Fig. 9, wherein horizontal length of a portion of 502 of PFET formed between 501 is smaller than horizontal length of 501 of PFET and horizontal length of a portion of 502 of PFET formed above the topmost surface of 501) a thickness of each of the second metal pattern (“TiAlC” of 502 in Fig. 9) and the third metal pattern (501 of PFET in Fig. 9), and wherein a topmost surface of the first metal pattern (lower “TiN” of 502 in Fig. 9) of the second outer gate electrode (502-503 of NFET in Fig. 9) is coplanar with a topmost surface of the second metal pattern (“TiAlC” of 502 in Fig. 9) of the second outer gate electrode (502-503 of NFET in Fig. 9). Kwon does not disclose a gate capping pattern on a top surface of the gate electrode; a first interlayer insulating layer on the gate capping pattern; a gate contact penetrating the first interlayer insulating layer and coupled to the gate electrode; a second interlayer insulating layer on the first interlayer insulating layer; a first metal layer in the second interlayer insulating layer; a third interlayer insulating layer on the second interlayer insulating layer; and a second metal layer in the third interlayer insulating layer. Lee730 discloses a gate capping pattern (GP in Fig. 14D, paragraph 0032) on a top surface of the gate electrode (GE in Fig. 14D, paragraph 0032 ) ; a first interlayer insulating layer 120 (Fig. 14D, paragraph 0032) on the gate capping pattern (GP in Fig. 14D); a gate contact (GC in Fig. 14D, paragraph 0046) penetrating the first interlayer insulating layer 120 (Fig. 14D) and coupled to the gate electrode (GE in Fig. 14D); a second interlayer insulating layer (lower portion of 130 in Fig. 14D, paragraph 0041) on the first interlayer insulating layer 120 (Fig. 14D); a first metal layer (VI in Fig. 14D, paragraph 0047) in the second interlayer insulating layer (lower portion of 130 in Fig. 14D); a third interlayer insulating layer (upper portion of 130 in Fig. 14D, paragraph 0041) on the second interlayer insulating layer (lower portion of 130 in Fig. 14D); and a second metal layer (IL in Fig. 14D, paragraph 0047) in the third interlayer insulating layer (upper portion of 130 in Fig. 14D). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon to form a gate capping pattern on a top surface of the gate electrode; a first interlayer insulating layer on the gate capping pattern; a gate contact penetrating the first interlayer insulating layer and coupled to the gate electrode; a second interlayer insulating layer on the first interlayer insulating layer; a first metal layer in the second interlayer insulating layer; a third interlayer insulating layer on the second interlayer insulating layer; and a second metal layer in the third interlayer insulating layer, as taught by Lee730, since the first wiring layer (Lee730, paragraph 0049) may be provided with a plurality of stacked wiring layers such that logic cells may be connected to each other through the connection lines IL (Lee730, Fig. 14D, paragraph 0049) and via VI (Lee730, Fig. 14D, paragraph 0049), thereby constituting a logic circuit. Kwon and Lee730 do not disclose a lower surface of the filling metal pattern in a region that vertically overlaps the first channel pattern is at a lower level than a topmost surface of the third metal pattern in the region that vertically overlaps the first channel pattern. Chiang discloses a lower surface of the filling metal pattern 148 (Fig. 2R-2, paragraph 0060) in a region that vertically overlaps the first channel pattern 122 (Fig. 2R-2, paragraph 0061) is at a lower level than a topmost surface of the third metal pattern 144 (Fig. 2R-2, paragraph 0062) in the region that vertically overlaps the first channel pattern 122 (Fig. 2R-2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon to form a lower surface of the filling metal pattern in a region that vertically overlaps the first channel pattern is at a lower level than a topmost surface of the third metal pattern in the region that vertically overlaps the first channel pattern, as taught by Chiang, since a gate structure (Chiang, paragraph 0002) is formed over and along the sides of the fin (e.g., wrapping) utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices. Regarding claim 17 , Kwon further discloses the semiconductor device as claimed in claim 16, wherein the first metal pattern (lower “TiN” of 502 in Fig. 9) includes titanium nitride, the second metal pattern (“TiAlC” of 502 in Fig. 9) includes aluminum-doped titanium carbide, and the third metal pattern 501 (Fig. 9, paragraph 0037, wherein “titanium aluminum nitride (TiAlN)”) includes titanium aluminum nitride. Regarding claim 18 , Kwon further discloses the semiconductor device as claimed in claim 16, wherein the second metal pattern (“TiAlC” of 502 in Fig. 9) is spaced apart from an inner side surface of the high-k dielectric layer (“high-k dielectric layer” of 301 in Fig. 9) by the first metal pattern (lower “TiN” of 502 in Fig. 9). Regarding claim 19 , Kwon further discloses the semiconductor device as claimed in claim 16, wherein the third metal pattern 501 (Fig. 9, paragraph 0037) has a recessed topmost surface (see Fig. 9, wherein lower top surface of 501 contacting 502), the recessed topmost surface (see Fig. 9, wherein lower top surface of 501 contacting 502) being at a level lower than a topmost surface of the first outer gate electrode (501-503 of PFET in Fig. 9), and the first metal pattern (lower “TiN” of 502 in Fig. 9) covering the recessed topmost surface (see Fig. 9, wherein lower top surface of 501 contacting 502). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Lee730 and Chiang as applied to claim 16 above, and further in view of Lee et al. (US 2017/0110542) (hereafter Lee542). Regarding claim 20 , Kwon further discloses the semiconductor device as claimed in claim 16, wherein the high-k dielectric layer 301 (Fig. 9) directly contacts (see I-I’ cross sectional view of Fig. 9, bottom 301 contacts 501 and 502) a side surface of the third metal pattern 501 (Fig. 9) and a side surface of the first metal pattern (lower “TiN” of 502). Kwon in view of Lee730 and Chiang discloses the semiconductor device as claimed in claim 16, however Kwon and Lee730 do not disclose a topmost surface of the high-k dielectric layer is coplanar with the topmost surface of the first metal pattern and the topmost surface of the second metal pattern. Lee542 discloses a topmost surface of the high-k dielectric layer 82 (Fig. 1, paragraph 0069) is coplanar (see paragraph 0019, wherein “Upper ends of the gate dielectric layer, the work function layer, and the low resistance layer may be substantially the same plane”) with the topmost surface of the first metal pattern 85 (Fig. 1, paragraph 0070) and the topmost surface of the second metal pattern 86 (Fig. 1, paragraph 0126). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon in view of Lee730 and Chiang to form a topmost surface of the high-k dielectric layer is coplanar with the topmost surface of the first metal pattern, as taught by Lee542, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose , 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff , 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Response to Arguments 1. Applicant's arguments filed 3 / 5 /202 6 have been fully considered. 2. The applicant argues (REMARKS, third paragraph in page 1 3 ) that “ By virtue of their dependence from amended independent claim 1, claims 2 and 3 call for combinations including the above-quoted recitation of amended independent claim 1. However, as discussed above, Kwon fails to teach or suggest at least these recitations of amended independent claim 1. To overcome the deficiencies of Kwon, the Office Action cites Lee '542 as disclosing "a topmost surface of the high-k dielectric layer 82 . . . is coplanar . .. with the topmost surface of the first metal pattern." Office Action, p. 9. Even assuming the Office Action's characterizations, which Applicant does not concede, neither Lee '542 also fails to teach or suggests, inter alia, "wherein a lower surface of the filling metal pattern in a region that vertically overlaps the first channel pattern is at a lower level than a topmost surface of the third metal pattern in the region that vertically overlaps the first channel pattern," as recited in amended independent claim 1. ” However, Kwon et al. (US 2018/0315667) disclose the high-k dielectric layer 301 (Fig. 9) directly contacts (see I-I’ cross sectional view of Fig. 9, bottom 301 contacts 501 and 502) a side surface of the third metal pattern 501 (Fig. 9) and a side surface of the first metal pattern (lower “TiN” of 502 in Fig. 9; and see paragraph 0053, wherein “second WFM 502 may include TiN/TiAlC/TiN”). Applicant's arguments with respect to claims 1 -20 have been considered but are moot in view of the new ground(s) of rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. 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