Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. l12(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1, 11 recites “the predefined function comprising one or more operations of the electronic circuit not involving the one or more memory cells”, where scope related to said limitation is deemed indefinite. Because, the claim limitation clearly indicates that the predefined function comprising one or more operations of the electronic circuit where the electronic circuit comprising one or more memory cells. So, if the predefined function comprising one or more operations of the electronic circuit, it is automatically involved with one or more memory cells and the limitation “not involving the one or more memory cells” is very unclear and indefinite.
Also, as per claim 6 and 16, the limitation recites the predefined function comprises “accessing a memory portion” i.e. the predefined function is involved in memory portion or memory cells.
So, overall scope of the claim limitations is indefinite.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. l12(a), as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in sucha way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the timethe application was filed, had possession of the claimed invention.
Particularly, claim 1, 11 recites “the predefined function comprising one or more operations of the electronic circuit not involving the one or more memory cells” where written description totally not clear how predefined function is involved with operation of electronic circuit but not involving the one or more memory cells where electronic circuit comprising one or more memory cells.
For the purpose of examination, the limitation would be interpreted where operation of electronic circuit is involved with memory portion as the electronic circuit comprising one or more memory cells (see claim limitation 1, 5, 6, 11, 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hosono et al. (US Pub # 2010/0208510).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Hosono et al. teach an electronic circuit, comprising: one or more memory cells; and a control circuit configured to: determine a formation state for each of at least one of the one or more memory cells (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134-0146 where unit 160 is control circuitry and cell array includes memory cell MC and forming operation done before programming operation if the cell is determined as unformed state); and set a predefined function to a predefined state of executability based on the determined formation state(s) (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134 where defined status of memory cell (formed or unformed state) before executing writing / programming operation is predefined function), the predefined function comprising one or more operations of the electronic circuit not involving the one or more memory cells, (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134 where control circuitry 160 along with status circuit 180 defined status of memory cell (formed or unformed state) before executing writing / programming operation for memory cells).
wherein the formation state for each of the at least one of the one or more memory cells is either unformed or formed, and the formed state is a state into which an initially unformed memory cell is transformable and in which the formed memory cell is repeatedly switchable between a state of low electrical resistivity and a state of high electrical resistivity (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134-0146 where after forming operation is done, the control circuitry execute programming operation where variable resistor VR changes to low / high due to switching for set / reset operation, unformed cell is at always high state i.e. no switching).
Even though Hosono et al. teach unformed state but silent exclusively about wherein the unformed state is an electrically isolated state. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Hosono et al. where unformed state is actually constant high resistance state (see paragraph 0130) which would be called as single isolated state in order to have predefined state and apply appropriate voltage condition to have variable resistive state with function memory element (see paragraph 0005, 0008).
Regarding claim 2, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hosono et al. further teach wherein the control circuit is configured to set the predefined function to the predefined state of executability based on the determined formation state for a single one of the one or more memory cells (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126).
Regarding claim 3, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hosono et al. further teach wherein the control circuit is configured to determine the formation state for each of two or more memory cells and to set the predefined function to the predefined state of executability in response to determining that the determined formation states match a predefined formation state pattern (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110, the cell status pattern is formed / unformed pattern).
Regarding claim 4, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hosono et al. further teach wherein the control circuit is configured to determine the formation state for each of two or more memory cells and to set the predefined function to the predefined state of executability in response to determining that a minimum number or fraction of the two or more memory cells have a predefined one of the formed and unformed states (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134, control circuit determined cell status as formed / unformed for multiple cells).
Regarding claim 5, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hosono et al. further teach wherein the predefined state of executability is either enabled or disabled (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134-0140 where control circuitry enabled programming or set / reset operation only if cell status is formed but disable operation for unformed cell).
Regarding claim 6, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hosono et al. further teach, wherein the predefined function comprises at least one of a group of functions, the group comprising: executing a predefined software; accessing a predefined circuit portion; accessing a memory portion; assigning a permission; disabling an interface; disabling an interrupt; disabling a change of data (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064), disabling a change of configuration settings; requesting an authentication; running a supervising process; executing a key generator; enabling an interface; enabling an interrupt; enabling a change of data, enabling a change of configuration settings; assigning a life cycle state; locking a predefined feature or a higher-level system that the electronic circuit is part of; defining access rights; defining a value or a key; recording a level;setting a processing speed; and identifying a state (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134-0146 where cell status act as predefined function and if the cell status is “formed”, then only control circuit enable programming operation or set/reset operation for that cell i.e. change of data-high, low resistive state).
Regarding claim 7, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hosono et al. further teach further comprising: a write circuit controlled by the control circuit and configured to attempt to set each of the at least one of the one or more memory cells to the low resistivity state or to the high resistivity state for determining the formation state of respective memory cell (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134-0141).
Regarding claim 8, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Hosono et al. further teach further comprising: a read circuit controlled by the control circuit and configured to read each of the at least one of the one or more memory cells (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078).
Regarding claim 9, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 8 on which this claim depends.
Hosono et al. further teach wherein the control circuit is configured to, for each of the at least one of the one or more memory cells, first read the respective memory cell and to subsequently determine the formation state of the respective memory cell (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126).
Regarding claim 10, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Hosono et al. further teach wherein the control circuit is configured to issue an alarm if at least one memory cell is read to be in the high resistivity state and the respective determined formation state is the formed state (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134).
Regarding independent claim 11, Hosono et al. teach a method of operating an electronic circuit comprising one or more memory cells, the method comprising: determining a formation state for each of at least one of the one or more memory cells (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134-0146 where cell array includes memory cell MC, unit 160 control circuitry determine formed / unformed state of memory cell); and setting a predefined function to a predefined state of executability based on the determined formation state(s) (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134 where defined status of memory cell (formed or unformed state) before executing writing / programming operation is predefined function),
the predefined function comprising one or more operations of the electronic circuit not involving the one or more memory cells where control circuitry 160 along with status circuit 180 defined status of memory cell (formed or unformed state) before executing writing / programming operation for memory cells),
wherein the formation state for each of the at least one of the one or more memory cells is either unformed or formed and the formed state is a state into which an initially unformed memory cell is transformable (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126) and in which the formed memory cell is repeatedly switchable between a state of low electrical resistivity and a state of high electrical resistivity (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134-0146 where after forming operation is done, the control circuitry execute programming operation where variable resistor VR changes to low / high due to switching for set / reset operation, unformed cell is at always at high state i.e. no switching).
Even though Hosono et al. teach unformed state but silent exclusively about wherein the unformed state is an electrically isolated state. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Hosono et al. where unformed state is actually constant high resistance state (see paragraph 0130) which would be called as single isolated state in order to have predefined state and apply appropriate voltage condition to have variable resistive state with function memory element (see paragraph 0005, 0008).
Regarding claim 12, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Hosono et al. further teach wherein the method comprises setting the predefined function to the predefined state of executability based on the determined formation state for a single one of the one or more memory cells (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126).
Regarding claim 13, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Hosono et al. further teach wherein the method comprises determining the formation state for each of two or more memory cells and setting the predefined function to the predefined state of executability in response to determining that the determined formation states match a predefined formation state pattern (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0125).
Regarding claim 14, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Hosono et al. further teach wherein the method comprises determining the formation state for each of two or more memory cells and setting the predefined function to the predefined state of executability in response to determining that a minimum number or fraction of the two or more memory cells have a predefined one of the formed and unformed states (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134-0143).
Regarding claim 15, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Hosono et al. further teach wherein the predefined state of executability is either enabled or disabled (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126).
Regarding claim 16, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Hosono et al. further teach wherein the predefined function comprises at least one of a group of functions, the group comprising: executing a predefined software; accessing a predefined circuit portion; accessing a memory portion; assigning a permission; disabling an interface; disabling an interrupt disabling a change of data, disabling a change of configuration settings; requesting an authentication; running a supervising process (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064); executing a key generator; enabling an interface; enabling an interrupt; enabling a change of data, enabling a change of configuration settings; assigning a life cycle state; locking a predefined feature or a higher-level system that the electronic circuit is part of; defining access rights; defining a value or a key; recording a level; setting a processing speed; and identifying a state (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134-0146).
Regarding claim 17, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Hosono et al. further teach further comprising: attempting to set each of the at least one of the one or more memory cells to the low resistivity state or the high resistivity state for determining the formation state of the respective memory cell (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0121).
Regarding claim 18, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Hosono et al. further teach further comprising: reading each of the at least one of the one or more memory cells (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110).
Regarding claim 19, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Hosono et al. further teach wherein, for each of the at least one of the one or more memory cells, the determining the formation state of the respective memory cell is performed after the reading of the respective memory cell (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126).
Regarding claim 20, Hosono et al. teach all claimed subject matter as applied in prior rejection of claim 19 on which this claim depends.
Hosono et al. further teach further comprising issuing an alarm at least one memory cell is read to be in the high resistivity state and the respective determined formation state is the formed state (see Fig. 3-5, 9-15 and paragraph 0005-0014, 0037-0041, 0047-0064, 0074-0078, 0110-0126, 0134-0143).
Response to Arguments
Applicant's arguments filed 03/25/2026 have been fully considered but they are not persuasive.
Applicant argues (see page 11 of remarks) that Hosono does not disclose or suggest “the predefined function comprising one or more operations of the electronic circuit not involving the one or more memory cells”.
Examiner respectfully disagrees with this statement.
Because, as explained above under 112 rejections, the claim limitation totally contradicts applicant’s other limitation where claim 6, 16 clearly recite the predefined function comprising “accessing a memory portion” i.e. predefined function is also involved with memory portion / cells.
As also explained in the rejection, the defined status of memory cell (formed or unformed, see at least paragraph 0141) by the control circuitry 160 along with status circuit 180 is predefined function and determined the executability of memory cell i.e. if the cell status is formed, then the control circuitry can execute the writing / programming / set-reset operation where memory cells act as switch i.e. high / low resistive state (set or reset status) but if the cell status is unformed, the cell is at always high state i.e. unable to execute for programming operation (see Fig.12-15, paragraph 0011, 0055-0059, 0122-0136, 0141) i.e memory cells cannot act as a switch.
Regarding claim 3 and 13, applicant argues (see page 11 of remarks) that Hosono does not disclose or suggest “wherein the control circuit is configured to determine the formation state for each of two or more memory cells and to set the predefined function to the predefined state of executability in response to determining that the determined formation states match a predefined formation state pattern”.
Examiner respectfully disagrees with this statement.
First, the limitation “formation state pattern” would be interpreted broadly as the limitation didn’t define the pattern i.e. the cell formation state would be “formed” or “unformed” pattern.
Second, the limitation “determine the formation state for each of two or more memory cells” clearly indicate that control circuitry can determine for more than two memory cells. In Fig.12-15, paragraph 0011-0013, claim 9, 0055-0059, 0122-0136, 0141, Hosono et al. teach forming operation for the memory cells i.e two or more than two cells. If the cells are formed, the control circuits 160 along with status circuits 180 defined the cell status pattern as “formed”, otherwise it will be defined as “unformed” pattern.
Regarding claim 4 and 14, applicant argues (see page 14 of remarks) that Hosono does not disclose or suggest “wherein the control circuit is configured to determine the formation state for each of two or more memory cells and to set the predefined function to the predefined state of executability in response to determining that a minimum number or fraction of the two or more memory cells have a predefined one of the formed and unformed states”.
Examiner respectfully disagrees with this statement.
In Fig.12-15, paragraph 0011-0013, 0055-0059, 0122-0136, 0141, Hosono et al. teach the control circuit 160 along with status circuit 180 determines the status (unformed / formed) for multiple memory cells i.e more than two cells where at least one cell (fraction of two) or more cells are “formed” status before executing programming or set / reset operation for those cell / cells. No operation to execute for the unformed cell / cells.
Regarding claim 5 and 15, applicant argues (see page 14 of remarks) that Hosono does not disclose or suggest “the predefined state of executability is either enabled or disabled”.
Examiner respectfully disagrees with this statement.
In paragraph 0055, Hosono et al. teach that the "memory cell does not exhibit the behavior of transition of resistance state (change between the set state and the reset state) unless it undergoes the forming operation".
In paragraph 0057, Hosono et al. teach, "prior to executing the forming operation on the memory cells, all normal memory cells are still in the constant high-resistance state where the resistance state does not change"
As explained above, the determined cell status is predefined function and when the controller 160 along with status circuit 180 defined the cell status as “formed”, then only it can enable programming operation / set /reset operation. If the cell status or predefined function determined to be “unformed” status, then it will disable / no programming or set / reset operation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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