DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. Applicant’s amendment to the claims, filed on May 4, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
3. Applicant’s arguments/remarks, see pgs. 8-12, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
Pertaining to the Applicant’s arguments/remarks, pgs. 8-12:
The arguments state that the sacrificial layer 152 of Son is merely a liner disposed along the surface profile of the sacrificial spacers 150, and is not formed on an upper surface of the sacrificial spacers 150 so as to recess the upper surface of the sacrificial spacers 150.
The Examiner notes that the element 152 of Son is corresponded to the claimed first protective pattern in the claims. The recessing of an upper surface of the insulating fence which is element 150 of Son occurs in Fig. 11A.
The arguments further discuss final structure and/or elements in the Applicant’s figures without providing distinguishing limitations in the claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Currently, the claims require elements associated during method steps but do not claim distinguishing limitations pertaining to a final structure.
The Examiner further notes that discussion over the phone may help discussions in advancing prosecution and welcomes the Applicant’s Representative to schedule an interview.
Note by the Examiner
4. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-3, 6-8, 13, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2014/0077333 A1), hereinafter as S1, in view of Choi et al. (US 2013/0292847 A1), hereinafter as C1
6. Regarding Claim 1, S1 discloses a method of fabricating a semiconductor device (see Figs. 1-22E and [0026] “semiconductor device 100”), comprising:
forming interconnection structures (see in particular Figs. 3A-B elements 140, see [0057] “bit line stack structure 140”) on a lower structure (elements below 140);
forming an insulating layer (see in particular Figs. 4A-B element 148, see [0063] “insulating liner 148”) between the interconnection structures;
forming an insulating fence (element 150, see [0064] “sacrificial spacers 150”) between the insulating layer (see Fig. 5A-B);
forming a first protective pattern (see Figs. 6A-B element 152, see [0065] “sacrificial layer 152”) on the insulating fence (see Figs. 6A-B) and configured to recess an upper surface of the insulating fence (see Fig. 11A element 172 is a recess formed in an upper surface of the insulating fence element 150 and see [0082]);
etching the insulating layer after the forming of the first protective pattern to form contact holes (see Figs. 9A-B and [0075] “The second sacrificial layer 152, the insulating liner 148, the interlayer insulating pattern 130, and a portion of the substrate 110, which are exposed through the plurality of contact holes 154H, may be sequentially etched”); and
forming contact plugs (elements 160, see [0078] “contact plugs 160”) in the contact holes (see Fig. 10A-B and [0078]).
S1 does not explicitly disclose patterning the insulating layer to form insulating patterns; the insulating fence between the insulating patterns.
C1 discloses patterning the insulating layer to form insulating patterns (see in particular Figs. 9A-10C the insulating layer element 143 is patterned to form insulating patterns, see [0130] “after the line patterns 140 are formed, a first protecting spacer layer 143 may be conformally formed on the substrate 100 and then a second filling layer may be formed on the first protecting spacer layer 143. The second filling layer may fill spaces between the line patterns 140. The second filling layer may be planarized to form second filling line patterns”); the insulating fence between the insulating patterns (see Fig. 11B element 152 between the elements 143, see [0135] “sacrificial spacer 152”).
The patterning of the insulating layer at the step taught by C1 is incorporated as patterning of the insulating layer at the step of S1 (see S1 Fig. 9A the insulating layer element 148 is patterned in the same manner as C1 in a later step and the combination performs the patterning at an earlier step).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C1 with S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known stage of patterning a similar element of a similar device in a similar device for another to obtain predictable results (see C1 Figs. 9A-C).
7. Regarding Claim 2, S1, C1 disclose the method of claim 1, further comprising:
forming second protective patterns (see S1 in particular Figs. 7A-B, element 154, see [0067] “insulating lines 154”) on the interconnection structures (see Figs. 7A-B [0068]) and configured to recess upper surfaces of the interconnection structures (see Fig. 11A element 172 recesses upper surfaces of the interconnect structures elements 140),
wherein the second protective patterns and the first protective pattern are simultaneously formed (see S1 Figs. 7A-B [0068], simultaneously formed in the same manner as the Applicant’s invention in that they are etched back together subsequently considered simultaneously formed).
8. Regarding Claim 3, S1, C1 disclose the method of claim 1, further comprising removing the first protective pattern during the forming of the contact plugs (see S1 Figs. 9A-B at least a bottom portion is removed).
9. Regarding Claim 6, S1, C1 disclose the method of claim 1, wherein at least a portion of the first protective pattern remains after the forming of the contact plugs (see S1 Figs. 9A-B side portions remain).
10. Regarding Claim 7, S1, C1 disclose the method of claim 6, wherein the first protective pattern comprises an insulating material (see S1 [0066] “the second sacrificial layer 152 may include an oxide layer, a nitride layer, or a silicon oxynitride layer”)
11. Regarding Claim 8, S1, C1 disclose the method of claim 6, wherein the forming of the contact plugs comprises:
forming at least one conductive material layer that at least fills the contact holes (see S1 Figs. 9A-10B and [0078-0080] “Thereafter, a first conductive layer may be formed on the barrier layer 162 to such a sufficient thickness as to fill the inside of each of the plurality of contact holes 154H. After that, the first conductive layer may be etched back or polished until the barrier layer 162 is exposed, thereby forming the plurality of conductive plugs 164 within the plurality of contact holes 154H”); and
planarizing the at least one conductive material layer (see [0080]), wherein at least a portion of the first protective pattern remains after the planarizing (see Figs. 9A-10B and [0080]).
12. Regarding Claim 13, S1, C1 disclose the method of claim 1, wherein the forming of the first protective pattern on the insulating fence comprises partially etching the insulating fence to form a recess region (see [0064] “a first sacrificial layer may be deposited on the resultant structure having the insulating liner 148 and etched back using the insulating liner 148 as an etch stop layer, so that a plurality of sacrificial spacers 150 can be formed on both sidewalls of the plurality of bit line stack structures 140 to cover the insulating, liner 148”), and filling the recess region with the first protective pattern (see Figs. 6A-B the element 152 is formed after element 150 is recessed to be on sidewalls of element 148).
13. Regarding Claim 15, S1 discloses a method of fabricating a semiconductor device (see Figs. 1-22E and [0026] “semiconductor device 100”), comprising:
forming a lower structure (elements below 140) including first regions (first region of elements 132 under a first plurality of elements 140 of the array, see [0056] “direct contacts 132”) and second regions (second region of elements 158, see [0076] “metal silicide layer 158”);
forming interconnection structures (see in particular Figs. 3A-B elements 140, see [0057] “bit line stack structure 140”) on the lower structure (see Figs. 3A-B), the interconnection structures are electrically connected to the first regions (see Figs. 3A-B);
forming an insulating layer (see in particular Figs. 4A-B element 148, see [0063] “insulating liner 148”) between the interconnection structures (see Figs. 6A-B);
forming an insulating fence (element 150, see [0064] “sacrificial spacers 150”) between the insulating layer (see Figs. 6A-B);
simultaneously forming a first protective pattern (see Figs. 6A-B element 152, see [0065] “sacrificial layer 152”) on the insulating fence (see Figs. 6A-B) and configured to recess an upper surface of the insulating fence (see Fig. 11A element 172 is a recess formed in an upper surface of the insulating fence element 150 and see [0082]) and second protective patterns (element 154, see [0067] “insulating lines 154”) on the interconnection structures (see [0068]) and configured to recess upper surfaces of the interconnection structures (see Fig. 11A element 172 recesses upper surfaces of the interconnect structures elements 140);
etching the patterns after the forming of the first and second protective patterns to form contact holes (see Figs. 9A-B and [0075] “The second sacrificial layer 152, the insulating liner 148, the interlayer insulating pattern 130, and a portion of the substrate 110, which are exposed through the plurality of contact holes 154H, may be sequentially etched”); and
forming contact plugs (elements 160, see [0078] “contact plugs 160”) in the contact holes, the contact plugs are electrically connected to the second regions (see [0078-0080]).
S1 does not explicitly disclose the insulating layer are patterns; the insulating fence between the patterns.
C1 discloses the insulating layer are patterns (see in particular Figs. 9A-10C the insulating layer element 143 is patterned to form insulating patterns, see [0130] “after the line patterns 140 are formed, a first protecting spacer layer 143 may be conformally formed on the substrate 100 and then a second filling layer may be formed on the first protecting spacer layer 143. The second filling layer may fill spaces between the line patterns 140. The second filling layer may be planarized to form second filling line patterns”); the insulating fence between the insulating patterns (see Fig. 11B element 152 between the elements 143, see [0135] “sacrificial spacer 152”).
The patterning of the insulating layer at the step taught by C1 and shape of the insulating fence is incorporated as patterning of the insulating layer at the step of S1 (see S1 Fig. 9A the insulating layer element 148 is patterned in the same manner as C1 in a later step and the combination performs the patterning at an earlier step) and shape of the insulating fence of S1 (the bottom end of at least the insulating fence extends inwards towards and contacting the contact plugs).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C1 with S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known stage of patterning a similar element of a similar device and simple substitution of one known shape of an element in a similar device for another to obtain predictable results (see C1 Figs. 9A-C).
14. Regarding Claim 16, S1, C1 disclose the method of claim 15, further comprising removing the first and second protective patterns during the forming of the contact plugs (see S1 Figs. 8A-9B and [0078-0080]).
15. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2014/0077333 A1), hereinafter as S1, in view of Choi et al. (US 2013/0292847 A1), hereinafter as C1, in view of Tsai (US 2021/0351140 A1), hereinafter as T1
16. Regarding Claim 4, S1, C1 disclose the method of claim 3.
S1, C1 do not disclose the first protective pattern comprises a metal nitride.
T1 discloses the first protective pattern comprises a metal nitride (see Fig. 19 liner layer element 509 which contacts sidewalls of a bit contact line can be selected to be made of a metal nitride, see [0091] “The liner layer 509 may be formed of, for example, titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or a combination thereof”)
The material of the first protective pattern as taught by T1 is incorporated as a material of the first protective pattern of S1, C1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of T1 with S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known material for a protective pattern on sidewalls of at least a conductive bit line contact structure for another in a similar device for which the options are provided as alternative selections to obtain predictable results (see T1 [0091]).
17. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2014/0077333 A1), hereinafter as S1, in view of Sandhu et al. (US 10,777,562 B1), hereinafter as S2, in view of Choi et al. (US 2013/0292847 A1), hereinafter as C1
18. Regarding Claim 18, S1 discloses a method of fabricating a semiconductor device (see Figs. 1-22E and [0026] “semiconductor device 100”), comprising:
forming an isolation layer (elements 130,112, see [0044] “isolation trenches 112” and [0054] “interlayer insulating pattern 130”) defining active regions (regions of element 116, see [0044] “active trenches 116”) on a substrate (element 110, see [0044] “semiconductor substrate 110”);
forming cell transistors (see [0049-0052] each of the source, drain, gate channels of the cells which are not shown) including gate structures (portion of the word line element 122 insulated and separated from the active channel region element 116 by the gate dielectric layer element 120) and first and second impurity regions (see [0049-0052] source and drain regions), wherein the gate structures cross the active regions (see at least Figs. 3A-B), and wherein the first and second impurity regions are formed in the active regions (see [0049-0052]):
forming bit line structures (see in particular Figs. 3A-B elements 140, see [0057] “bit line stack structure 140”) disposed on the cell transistors, the active regions, and the isolation layer, the bit line structures extending parallel to each other (see Fig. 9A-B);
forming insulating an insulating layer (see in particular Figs. 4A-B element 148, see [0063] “insulating liner 148”) between the bit line structures (see Figs. 4A-B);
forming an insulating fence (see Figs. 5A-B element 150, see [0064] “sacrificial spacers 150”) between the insulating layer (see Figs. 5A-B);
simultaneously forming a first protective pattern (see Figs. 6A-B element 152, see [0065] “sacrificial layer 152”) on the insulating fence and configured to recess an upper surface of the insulating fence (see Fig. 11A element 172 is a recess formed in an upper surface of the insulating fence element 150 and see [0082]) and second protective patterns (see Figs. 7A-B, element 154, see [0067] “insulating lines 154”) on the bit line structures (see Figs. 7A-B [0068], simultaneously formed in the same manner as the Applicant’s invention in that they are etched back together subsequently considered simultaneously formed) and configured to recess upper surfaces of the interconnection structures (see Fig. 11A element 172 recesses upper surfaces of the interconnect structures elements 140);
etching the insulating patterns after the forming of the first and second protective patterns to form contact holes (see Figs. 9A-B and [0075] “The second sacrificial layer 152, the insulating liner 148, the interlayer insulating pattern 130, and a portion of the substrate 110, which are exposed through the plurality of contact holes 154H, may be sequentially etched”); and
forming contact plugs (elements 160, see [0078] “contact plugs 160”) in the contact holes (see Fig. 10A-B and [0078]).
S1 does not explicitly disclose the gate structures extend into the isolation layer; the insulating layer is insulating patterns.
S2 discloses the gate structures extend into the isolation layer (see Fig. 7 gate structures elements 22 extend into the isolation layer element 14, see Column 3 lines 62-66 “conductive gate material 22” see Column 3 line 40 “trench isolation regions 14”).
The gate structures extending into the isolation layer as taught by S2 is incorporated as the gate structures extending into the isolation layer of S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S2 with S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gate alignment location with respect to the isolation layer of a similar device for another to obtain predictable results (see S2 Fig. 7).
S1, S2 do not disclose the insulating layer is insulating patterns.
C1 discloses the insulating layer is insulating patterns (see in particular Figs. 9A-10C the insulating layer element 143 is patterned to form insulating patterns, see [0130] “after the line patterns 140 are formed, a first protecting spacer layer 143 may be conformally formed on the substrate 100 and then a second filling layer may be formed on the first protecting spacer layer 143. The second filling layer may fill spaces between the line patterns 140. The second filling layer may be planarized to form second filling line patterns”).
The patterning of the insulating layer at the step taught by C1 and shape of the insulating fence is incorporated as patterning of the insulating layer at the step of S1 (see S1 Fig. 9A the insulating layer element 148 is patterned in the same manner as C1 in a later step and the combination performs the patterning at an earlier step) and shape of the insulating fence of S1 (the bottom end of at least the insulating fence extends inwards towards and contacting the contact plugs).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C1 with S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known stage of patterning a similar element of a similar device and simple substitution of one known shape of an element in a similar device for another to obtain predictable results (see C1 Figs. 9A-C).
19. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2014/0077333 A1), hereinafter as S1, in view of Sandhu et al. (US 10,777,562 B1), hereinafter as S2, in view of Choi et al. (US 2013/0292847 A1), hereinafter as C1, in view of Wang et al. (US 2018/0350817 A1), hereinafter as W1
20. Regarding Claim 19, S1, S2, C1 disclose the method of claim 18, wherein:
each of the bit line structures comprises a bit line (each of the individual elements 142, see [0057] “bit lines 142”) including plug portions (elements 132, see [0057] “A plurality of bit line stack structures 140 may be formed on the interlayer insulating pattern 130 and the plurality of direct contacts 132 and extend parallel to one another. The plurality of bit line stack structures 140 may include a plurality of bit lines 142 and a plurality of insulating capping lines 144 covering top surfaces of the plurality of bit lines 142.”) electrically connected to the first and second impurity regions (see [0056] “The plurality of direct contacts 132 may be electrically connected to the source regions 1165 of the active regions 116”), respectively, an insulating capping layer (element 144, see [0057] “insulating capping lines 144”) disposed on the bit line;
the second protective patterns are formed on the insulating capping layers of the bit line structures (see S1 in particular Figs. 7A-B); and
the first and second protective patterns are removed during the forming of the contact plugs (see S1 Figs. 8A-9B and [0078-0080]).
S1, S2, and C1 do not disclose insulating spacers disposed on a lateral side surface of the bit line and a lateral side surface of the insulating capping layer.
W1 discloses insulating spacers disposed on a lateral side surface of the bit line and a lateral side surface of the insulating capping layer (see Fig. 2 bit line of element BL and see [0026] “Additionally, one or more spacers may be formed on sidewalls of each of the bit line structures BL. The spacers formed on the sidewalls of each of the bit line structures BL”, and see [0025] “bit line structures BL … cap layer 44A”).
The insulating spacers as taught by W1 is incorporated as insulating spacers of S1, S2, and C1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of W1 with S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known presence/absence of spacers of a similar device for another for which a number of spacers is selectable to obtain predictable results (see W1 Fig. 2 and [0026]).
Allowable Subject Matter
21. Claims 5 and 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
22. Claim 5, “forming at least one conductive material layer that at least fills the contact holes; and planarizing the at least one conductive material layer until the first protective pattern is removed and the insulating fence is exposed” – as instantly claimed and in combination with the additionally claimed limitations.
23. Claim 9, “forming an upper recess region by performing a first partial etching of the insulating fence; forming a first protective layer covering a sidewall of the upper recess region and exposing a lower surface of the upper recess region; forming a lower recess region by performing a second partial etching of the insulating fence below the lower surface of the upper recess region exposed by the first protective layer; and forming a second protective layer filling the lower recess region and the upper recess region, wherein the first protective layer and the second protective layer constitute the first protective pattern” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on the current claim incorporate the same allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMUEL PARK/Examiner, Art Unit 2818
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