DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05 March 2026 has been entered.
Response to Arguments
Applicant's arguments filed 05 March 2026 have been fully considered and the responses are set forth below.
The claims have been amended to further define some features of the disclosure in the independent claims 1, 21, and 27. These amendments overcome the prior art of record as previously applied in the last Office action.
However, features relating to the overall configuration of the package and the spatial relationships between the various packaged features have not been defined with sufficient specificity to overcome the prior art of record and newly referenced art (listed in the updated rejections below). Applicant elected Invention I Species 1 (represented by Figs. 1A, 1B, and 4-12, device 100) in the response filed 05/28/2025. Specifically, the independent claims have not included limitations relating to the overall structure and configuration of the package represented by this election, including (from bottom to top of Fig. 1A) a package substrate, first contact layer, first interconnect, first IC die with related dual-sided features, second interconnect, second contact layer, RDL, and second IC die. The rejections have been updated below according to the newly presented amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Vidhya Ramachandran et al. (US 20160095221 A1; hereinafter Ramachandran) in view of Min-Feng Kao et al. (US 20200411636 A1; hereinafter Kao) and Jonghae Kim et al. (US 20220223585 A1; hereinafter Kim).
Regarding Claim 1, Ramachandran discloses a structure (Fig. 1 and Fig. 3), comprising:
a package substrate (308);
a first integrated circuit (IC) die (100; ¶0028), disposed on a first side (top) of the package substrate (308), comprising:
a substrate (104; ¶0028) comprising a first surface (active side) and a second surface (backside) opposite to the first surface,
a first active device (110a; ¶0028) disposed on the first surface (active side) of the substrate (104),
a passive device (114; ¶0029) disposed on the second surface (backside) of the substrate (104), wherein the passive device comprises:
a plurality of trenches (plurality of trench caps 114’s in trenches) disposed in the substrate (104) and through the second surface of the substrate (as shown in Fig. 1),
a through-via (112; ¶0029) disposed in the substrate and adjacent to the first active device (110a) and the passive device (114) (as shown in Fig. 1), wherein the through-via (112) extends over a top surface of the first active device (top of 110a) and over a top surface of the passive device (top of 114) (as shown in Fig. 1);
a second IC die (302) comprising a second active device (¶0032) disposed on the first IC die (100) (as shown in Fig. 3).
Ramachandran is silent regarding wherein the trench capacitor comprises first and second conductive layers disposed in the plurality of trenches and on the second surface of the substrate, and a first dielectric layer disposed between the first and second conductive layers.
In the same field of endeavor, Kao discloses a similar package (Fig. 3 and Fig. 2) comprising a passive device (capacitor in trench 317; ¶0026; hereinafter cap) disposed on a second surface (bottom) of a substrate (302; ¶0026) opposite a first active device (110; ¶0014) disposed on the first surface (top) of the substrate (302), wherein the passive device (cap) comprises:
a trench (317; ¶0025) disposed in the substrate (302) and through the second surface (bottom) of the substrate (302),
first (114) and second (117) conductive layers (¶0023) disposed in trench (317) and on the second surface (bottom) of the substrate (302), and
a first dielectric layer (116b; ¶0023) disposed between the first (114) and second (117) conductive layers (wherein Kao discloses in ¶0026 that the capacitor of Fig. 1 or Fig. 2 can be inserted into the trench 317).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the features of Kao’s trench capacitor for that of Ramachandran in order to provide a capacitor with relatively high capacitance in a small footprint (Kao; ¶0012) and/or for their art recognized equivalence for the same purpose of providing a trench capacitor opposite the side of the substrate from an active device in a semiconductor package (MPEP 2144.06).
Ramachandran is silent regarding wherein first and second bonding structures disposed on a second side of the package substrate that faces away from the first IC die; and
a trench capacitor disposed on the second side of the package substrate and between the first and second bonding structures.
In the same field of endeavor, Kim teaches a similar package (Fig. 7) comprising multiple semiconductor dies (712; ¶0050) disposed above (top of) a package substrate (702; ¶0050), wherein first and second bonding structures (704/704; ¶0050) disposed on a second side (bottom) of the package substrate (702) that faces away from the first IC die (712); and a trench capacitor (710 which comprises trench capacitors of Fig. 6; ¶0050) disposed on the second side (bottom) of the package substrate (702) and between the first and second bonding structures (704/704) (as shown in Fig. 7).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the above features of Kim in the package of Ramachandran in order to provide high capacitance close to the desired circuit (Kim; ¶0003) or to provide a decoupling capacitor (¶0024; ¶0050) for the package.
Regarding Claim 2, modified Ramachandran teaches the structure of claim 1, wherein the passive device is electrically connected to the first active device through the conductive through-vias (as described in Ramachandran ¶0029).
Regarding Claim 3, modified Ramachandran teaches the structure of claim 1, further comprising a redistribution layer (Fig. 3; metal lines and via on 102 side between 104 and 302 comprising elements 110; ¶0028) disposed between the first and second IC dies.
Ramachandran does not expressly disclose wherein the first IC die (of 100) is bonded to the redistribution layer with the second surface of the substrate (backside of 104) facing the second IC die (302).
However, Ramachandran teaches another embodiment in Fig. 2 showing either orientation (backside facing second die as in Fig. 2 or active side facing second die as in Fig. 3). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have either orientation as shown in Fig. 2 and Fig. 3 of Ramchandran because they are shown to be art recognized equivalents/alternatives for the purpose of packaging semiconductor components (MPEP 2144.04 MPEP 2144.06).
Regarding Claim 4, modified Ramachandran teaches the structure of claim 1, wherein a back-side of the passive device (114) is separated from a back-side of the first active device (110) by a portion of the substrate (104) (as shown in Ramachandran Fig. 1).
Regarding Claim 5, modified Ramachandran teaches the structure of claim 1, wherein the passive device (114) and the first active device (labeled 110a) are non-overlapping with each other (as shown in Fig. 1).
Regarding Claim 6, modified Ramachandran teaches the structure of claim 1, wherein the first IC die further comprises a first contact layer (on side of 106) disposed on the passive device (114),
wherein the first contact layer comprises a first dual-layered passivation layer (layer surrounding metal lines 108 which has a layer surrounding the pads of the TFTs, plate cap, and TF diodes devices, and a layer surrounding the wide pads closer to the package substrate) and first dual-layered metal pads (108 which includes contact pads of the devices and wider pads closer to the package substrate) disposed in the first dual-layered passivation layer,
wherein the second IC die (302) comprises a second contact layer disposed on the second active device, wherein the second contact layer comprises a second dual-layered passivation layer and second dual-layered metal pads disposed in the second dual-layered passivation layer (die 302 may include the exemplary aspects of the disclosure and therefore contains the same features as the first die thereby satisfying these limitations, as described in ¶0032; and/or it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have die 302 incorporate the same features as die 100 to exploit additional surface area on the semiconductor die, as described in ¶0026), and wherein the first and second contact layers are electrically bonded to each other (they are electrically coupled via 304; ¶0034 in view of Fig. 3).
Ramachandran does not explicitly disclose that the material surrounding the metals lines is a passivation layer (which requires it to be a material that can electrically insulate metal lines, commensurate in scope with ¶0033 of the instant specification). However, Ramachandra discloses in ¶0038 that forming conductive features on a side of the substrate may include depositing an interlayer dielectric then patterning and filling with the conductive material.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the interlayer dielectric material (¶0038) as a passivation layer surround the conductive metal lines in the embodiment of Fig. 3 in order to support the formation of the metal lines while preventing respective connected devices from electrical shorts.
Regarding Claim 7, modified Ramachandran teaches the structure of claim 1, wherein the passive device further comprises: a doped region in the substrate (as modified by Kao Fig. 2; 136; ¶0019) and surrounding the plurality of trenches (plurality of 114’s of Ramachandran); and a second dielectric layer (116c; ¶0023) disposed in the plurality of trenches and between the doped region (136) and the first conductive layer (114).
Regarding Claim 8, modified Ramachandran teaches the structure of claim 1, wherein the first IC die (100) comprises a logic die (¶0026) or a memory die.
Regarding Claim 9, modified Ramachandran teaches the structure of claim 1, wherein the second IC die (302) comprises a system-on-chip (SoC) die (¶0032; ¶0005).
These limitations are implicitly satisfied by the structure of claim 1 because it is the intended use of the structure, and the filed-specification does not define additional structural details required by a “system-on chip” die or “logic die”. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. See In re Swinehart, 169 USPQ 226 (C.C.P.A. 1971), MPEP 2114 I.
Alternatively, Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Vidhya Ramachandran et al. (US 20160095221 A1; hereinafter Ramachandran) in view of Min-Feng Kao et al. (US 20200411636 A1; hereinafter Kao), Jonghae Kim et al. (US 20220223585 A1; hereinafter Kim), and Hsiang-Wei Liu et al. (US 20160005691 A1; hereinafter Liu).
Regarding Claim 6, modified Ramachandran teaches the structure of claim 1, wherein the first IC die further comprises a first contact layer (on side of 106) disposed on the passive device (114),
wherein the first contact layer comprises a first passivation layer (layer surrounding metal lines and features of 108 and devices) and first dual-layered metal pads (108 which includes contact pads of the devices/ thin portions of 108 and wider pads closer to the package substrate) disposed in the first passivation layer,
wherein the second IC die (302) comprises a second contact layer disposed on the second active device, wherein the second contact layer comprises a second passivation layer and second dual-layered metal pads disposed in the second passivation layer (die 302 may include the exemplary aspects of the disclosure and therefore contains the same features as the first die thereby satisfying these limitations, as described in ¶0032; and/or it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have die 302 incorporate the same features as die 100 to exploit additional surface area on the semiconductor die, as described in ¶0026), and wherein the first and second contact layers are electrically bonded to each other (they are electrically coupled via 304; ¶0034 in view of Fig. 3).
Ramachandran does not explicitly disclose that the material surrounding the metals lines are a first and second dual-layer passivation layer.
In the same field of endeavor, Liu teaches a contact layer (Fig. 1) including wide pads (114) and narrow pads (112) having different metals from each other (¶0016), and first (116) and second (108) dielectric layers (dual layered passivation) with dielectric materials different from each other (¶0013) to support formation of vias (110) for connection to underlying semiconductor-related components (¶0013).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the above dual layered passivation layers of Liu in the contact layers of modified Ramachandran order to properly fill the variously sized/layered pads to improve reliability (Liu; ¶0011) while utilizing the multiple dielectric materials to protect underlying components while forming the narrow portions.
Claims 21 and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Chen-Hua Yu et al. (US 20220262778 A1; hereinafter Yu) in view of Min-Feng Kao et al. (US 20200411636 A1; hereinafter Kao) and Hsiang-Wei Liu et al. (US 20160005691 A1; hereinafter Liu).
Regarding Claim 21, Yu discloses a structure (Fig. 20), comprising:
a first integrated circuit (IC) die (42; ¶0023), comprising:
a substrate (44; ¶0023),
first and second trench capacitors (49 left and 49 right; ¶0023) disposed on the substrate (44),
a first interconnect structure (in view of Fig. 2; 51/53; ¶0023) disposed on the first and second trench capacitors (49/49) and comprising a dielectric layer (51; ¶0023) and metal lines (53; ¶0023) disposed in the dielectric layer (as shown in Fig. 2);
a contact layer (50/52) disposed on the first interconnect structure (48) and comprising a first passivation layer (52; ¶0025) and metal pads (50; which comprise wide pads and narrow pads with vias; ¶0025) disposed in the first passivation layer (50 is disposed in 52, wherein 52 is a dielectric passivation layer providing coplanar surfaces for 50/52);
and
a through-via (46 middle; ¶0023) disposed in the substrate (44) and between the first and second trench capacitors (as shown in Fig. 20);
a redistribution layer (plurality of features comprising 73/75; ¶0051) disposed on and in physical contact with the contact layer (50/52) (as shown in Fig. 20); and
a second IC die (die of substrate 20) comprising a second semiconductor device (22; ¶0015) disposed on the redistribution layer (73/75) (as shown in Fig. 20).
Yu does not expressly disclose a first semiconductor device disposed on the substrate (44).
In the same field of endeavor, Kao teaches a similar structure (Fig. 9), comprising a first IC die (Fig. 9) comprising a substrate (102; ¶0014), a trench capacitor (in trench 112; ¶0018) disposed on the substrate (102), a first semiconductor device (110 on the right; ¶0014) disposed on the substrate with a through via (186; ¶0037).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosures and integrate a semiconductor device on the substrate of the first IC die with the trench capacitors in the manner of Kao in the device of Yu. One of ordinary skill in the art would have motivation to do so in order to reduce size, cost, and increase functionality of the IC device (Kao; ¶0002).
Modified Yu is silent regarding wherein the first passivation layer (52) comprises first and second dielectric layers having dielectric materials different from each other, and wherein the metal pads (50) comprise first (wide) and second metal pads (narrow) having metals different from each other.
In the same field of endeavor, Liu teaches a contact layer (Fig. 1) including wide pads (114) and narrow pads (112) having different metals from each other (¶0016), and first (116) and second (108) dielectric layers with dielectric materials different from each other (¶0013) to support formation of vias (110) for connection to underlying semiconductor-related components (¶0013).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the above features of Liu in the contact layer of Yu in order to properly fill the wide and narrow pads to improve reliability (Liu; ¶0011) while utilizing the multiple dielectric materials to protect underlying components while forming the vias.
Regarding Claim 23, modified Yu teaches the structure of claim 21, wherein the first trench capacitor (49) is separated from the first semiconductor device (Kao; 110) by a portion of the substrate (as modified by Kao Fig. 9, which shows trench capacitor is separated from semiconductor device 110 by a portion of the substrate between the two).
Regarding Claim 24, modified Yu teaches the structure of claim 21, wherein the first trench capacitor (49 left) and the first semiconductor device (Kao; 110) overlap with each other (as modified by Kao Fig. 9; trench capacitor and semiconductor device 110 overlap in a vertical direction); and wherein the second trench capacitor (49 right) and the first semiconductor device (Kao; 110) non-overlap with each other (as modified, the semiconductor device 110 overlapping with the first trench capacitor {49 left} in the vertical direction would not overlap the second trench capacitor {49 right} in the vertical direction).
Regarding Claim 25, modified Yu teaches the structure of claim 21, wherein the first IC die (42) further comprises: a second passivation layer (82; ¶0039) disposed on the first semiconductor device (as modified by Kao; Fig. 9; wherein the semiconductor device 110 is opposite the trench capacitor, this would put the semiconductor device 110 on the top of 44 in Yu Fig. 20; and passivation layer 82 would be disposed on 110 in Fig. 20 of Yu as modified by Kao).
Regarding Claim 26, modified Yu teaches the structure of claim 21, further comprising a conductive through-via (26; ¶0050) adjacent to the first IC die (42) (26 and 42 are adjacent) and in contact with the redistribution layer (73/75) (as shown in Yu Fig. 20; 26 is in physical and electrical contact with the plurality of features of 73/75).
Claims 27 and 29-33 are rejected under 35 U.S.C. 103 as being unpatentable over Vidhya Ramachandran et al. (US 20160095221 A1; hereinafter Ramachandran) in view of Min-Feng Kao et al. (US 20200411636 A1; hereinafter Kao) and Thomas W. Dyer (US 20090250738 A1; hereinafter Dyer).
Regarding Claim 27, Ramachandran discloses a structure (Fig. 1/Fig. 3), comprising:
a first integrated circuit (IC) die (100; ¶0028), comprising:
a substrate (104; ¶0028),
a first semiconductor device (110a; ¶0028) disposed on the substrate (104), and
a trench capacitor (114; ¶0029) disposed on the first semiconductor device, wherein the trench capacitor (114) comprises:
a trench disposed in the substrate (as shown in Fig. 1; ¶0037), and
a second IC die (302; ¶0030-¶0032) comprising a second semiconductor device disposed on the first IC die (100) (as shown in Fig. 3).
Ramachandran is silent regarding the details of the trench capacitor, wherein it comprises a doped conductive region, surrounding the trench, first and second conductive layers disposed in the trench, and a high-k dielectric layer disposed between the first and second conductive layers.
In the same field of endeavor, Kao teaches a similar device with a trench capacitor integrated into a semiconductor package (Fig. 1 and Fig. 3) comprising: a trench (317; ¶0026) disposed in the substrate (302), a doped conductive region (136; ¶0019), surrounding the trench (as shown in Fig. 1), first (314) and second (318) conductive layers (¶0026) disposed in the trench (317), and a high-k dielectric layer (316; ¶0034) disposed between the first and second conductive layers (as shown in Fig. 3).
Absent any evidence of criticality, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the features of Kao’s capacitor in the device of Ramachandran in order to increase capacitance (Kao; ¶0034) in a small area (Kao; ¶0020).
Ramachandran modified by Kao is silent regarding the details of the doped conductive region comprising: dopants of conductivity different from a conductivity of the substrate, wherein a concentration of the dopants in the doped conductive region is about 1 to about 2 orders higher than a concentration of dopants in the substrate.
In the same field of endeavor, Dyer teaches a trench capacitor (Fig. 12; ¶0073) comprising a doped conductive region (12) surrounding the trench (11) (¶0055) comprising dopants of conductivity different (12 has a second conductivity type; ¶0055) from a conductivity of the substrate (6) (first conductivity type; ¶0049), wherein a concentration of the dopants in the doped conductive region (second conductivity type 12) is about 1 to about 2 orders higher (¶0055) than a concentration of dopants in the substrate (first conductivity type of 6; ¶0049).
Absent any evidence of criticality, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the dopant configuration of Dyer for that of the trench capacitor of modified Ramchandran in order to provide a deep trench capacitor (Dyer; ¶0073) with good capacitance, and/or for its art recognized equivalence for the same purpose of providing a deep trench capacitor in a semiconductor device (MPEP 2144.06).
Regarding Claim 29, modified Ramachandran teaches the structure of claim 27, wherein the first IC die (100) further comprises a conductive through-via (112) disposed in the substrate (104) and electrically connected to the trench capacitor (114) (as described in ¶0029 wherein TSV 112 electrically couples 108d connected to 114 as shown in Fig. 3), and wherein the conductive through-via (112) extends over a top surface of the first semiconductor device (110a) and over a top surface of the trench capacitor (114) (as shown in Ramachandran Fig. 3).
Regarding Claim 30, modified Ramachandran teaches the structure of claim 27, wherein the first IC die comprises a logic die (¶0026) or a memory die, and wherein the second IC die comprises a system-on-chip (SoC) die (¶0032; ¶0005).
These limitations are implicitly satisfied by the structure of claim 27 because it is the intended use of the structure, and the filed-specification does not define additional structural details required by a “system-on chip” die. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. See In re Swinehart, 169 USPQ 226 (C.C.P.A. 1971), MPEP 2114 I.
Regarding Claim 31, modified Ramachandran teaches wherein the first IC die further comprises:
a first interconnect structure (interconnect on side 106) disposed on the trench capacitor (114) and comprising a first dielectric layer (surrounding material of side 106) and a first metal line (108d; ¶0028) disposed in the first dielectric layer;
a second interconnect structure (interconnect on side 102) disposed on the first semiconductor device (110a) and comprising a second dielectric layer (surrounding material of side 102) and a second metal line (110b; ¶0028) disposed in the second dielectric layer; and
a conductive through-via (TSV 112; ¶0029) extending through the substrate and into the first and second dielectric layers and in physical contact with the first (108d) and second metal lines (110b) (as shown in Ramachandran Fig. 3).
Ramachandran does not explicitly disclose that the material surrounding the metals lines (first 108d and second 110b) is a dielectric. However, Ramachandran discloses in ¶0038 that forming conductive features on a side of the substrate may include depositing an interlayer dielectric then patterning and filling with the conductive material.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the interlayer dielectric material (¶0038) surround the conductive metal lines in the embodiment of Fig. 3 in order to support the formation of the metal lines while preventing respective connected devices from electrical shorts.
Regarding Claim 32, modified Ramachandran teaches the structure of claim 27, wherein the first IC die further comprises a first contact layer (on side of 106) disposed on the trench capacitor (114) and comprising a first dual-layered passivation layer (layer surrounding metal lines 108 which has a layer surrounding the pads of the TFTs, plate cap, and TF diodes devices, and a layer surrounding the wide pads closer to the package substrate) and first dual-layered metal pads (108 which includes contact pads of the devices and wider pads closer to the package substrate) disposed in the first dual-layered passivation layer; and
wherein the second IC die (302) further comprises a second contact layer disposed on the second semiconductor device and comprising a second dual-layered passivation layer and second dual- layered metal pads disposed in the second dual-layered passivation layer (die 302 may include the exemplary aspects of the disclosure and therefore contains the same features as the first die thereby satisfying these limitations, as described in ¶0032; and/or it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have die 302 incorporate the same features as die 100 to exploit additional surface area on the semiconductor die, as described in ¶0026).
Ramachandran does not explicitly disclose that the material surrounding the metals lines (first 108d and second 110b) is a passivation layer (which requires it to be a material that can electrically insulate metal lines, commensurate in scope with ¶0033 of the instant specification). However, Ramachandra discloses in ¶0038 that forming conductive features on a side of the substrate may include depositing an interlayer dielectric then patterning and filling with the conductive material.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the interlayer dielectric material (¶0038) as a passivation layer surround the conductive metal lines in the embodiment of Fig. 3 in order to support the formation of the metal lines while preventing respective connected devices from electrical shorts.
Regarding Claim 33, modified Ramachandran teaches the structure of claim 32, further comprising: a redistribution layer (layer comprising 306 which redistributes electrical signals to the package substrate; ¶0034) disposed on and in contact with the first dual-layered metal pads (layer 306 is in contact with the dual layered metal pads 108); and inter-IC die bonding structures (304) disposed between the first (100) and second (302) IC dies and in contact with the redistribution layer (304 is in electrical contact with interconnects 110 which is in electrical contact with 108; ¶0034 and Fig. 3) and the second dual-layered metal pads.
Alternatively, Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Vidhya Ramachandran et al. (US 20160095221 A1; hereinafter Ramachandran) in view of Min-Feng Kao et al. (US 20200411636 A1; hereinafter Kao), Thomas W. Dyer (US 20090250738 A1; hereinafter Dyer), and Hsiang-Wei Liu et al. (US 20160005691 A1; hereinafter Liu).
Regarding Claim 32, modified Ramachandran teaches the structure of claim 27, wherein the first IC die further comprises a first contact layer (on side of 106) disposed on the trench capacitor (114) and comprising a first passivation layer (layer surrounding metal lines 108) and first dual-layered metal pads (108 which includes contact pads of the devices/ thin portions of 108 and wider pads closer to the package substrate) disposed in the first passivation layer; and
wherein the second IC die (302) further comprises a second contact layer disposed on the second semiconductor device and comprising a second passivation layer and second dual- layered metal pads disposed in the second passivation layer (die 302 may include the exemplary aspects of the disclosure and therefore contains the same features as the first die thereby satisfying these limitations, as described in ¶0032; and/or it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have die 302 incorporate the same features as die 100 to exploit additional surface area on the semiconductor die, as described in ¶0026).
Ramachandran does not explicitly disclose that the material surrounding the metals lines are a first and second dual-layer passivation layer.
In the same field of endeavor, Liu teaches a contact layer (Fig. 1) including wide pads (114) and narrow pads (112) having different metals from each other (¶0016), and first (116) and second (108) dielectric layers (dual layered passivation) with dielectric materials different from each other (¶0013) to support formation of vias (110) for connection to underlying semiconductor-related components (¶0013).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the above dual layered passivation layers of Liu in the contact layers of modified Ramachandran order to properly fill the variously sized/layered pads to improve reliability (Liu; ¶0011) while utilizing the multiple dielectric materials of the dual layer passivation layers to protect underlying components while forming the narrow portions.
Claims 27 and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Min-Feng Kao et al. (US 20200411636 A1; hereinafter Kao) in view of Jyun-Ying Lin et al. (US 20210104598 A1; hereinafter Lin) and Thomas W. Dyer (US 20090250738 A1; hereinafter Dyer).
Regarding Claim 27, Kao teaches a structure (Fig. 3 in view of Fig. 1, wherein the capacitor from Fig. 1 can be insert into the trench of Fig. 3; ¶0026), comprising:
a first integrated circuit (IC) die (Kao Fig. 3; 302+306+top half of 322; hereinafter IC1), comprising:
a substrate (302; ¶0026),
a first semiconductor device (110; ¶0014) disposed on the substrate (302), and
a trench capacitor (capacitor in trench 317) disposed on the first semiconductor device (110), wherein the trench capacitor comprises:
a trench (317; ¶0026) disposed in the substrate (302),
a doped conductive region (136; ¶0019), surrounding the trench (as shown in Fig. 1),
first (314) and second (318) conductive layers (¶0026) disposed in the trench (317), and
a high-k dielectric layer (316; ¶0034) disposed between the first and second conductive layers (as shown in Fig. 3); and
a second IC die (die of substrate 320) comprising a second semiconductor device (110 of 320) disposed on the first IC die (as shown in Fig. 3).
Kao is silent regarding wherein the doped conductive region (136) comprises dopants of conductivity different from a conductivity of the substrate (this limitation is being interpreted in light of the instant specification at ¶0040, wherein the dopants surrounding the trench are n-type or p-type and the substrate is doped with the opposite n-type or p-type dopant). However, this is a well-known feature in the art.
One such example is provided from the same field of endeavor by Lin (Fig. 2B). Lin teaches a substantially same trench capacitor comprising first (108; ¶0032) and second (112; ¶0033) conductive layers with a dielectric (110; ¶0033) between them, disposed in a trench (102A/102B; ¶0027), wherein the trench is surrounded by a doped conductive region (104; ¶0027) that comprises a conductivity type (n-type; ¶0029) different from a conductivity type of the substrate (100A; p-type silicon; ¶0028 and claim 16).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosures to incorporate Lin’s teachings into the device of Kao in order to obtain a high-density trench capacitor (Lin; ¶0026) applicable for integration into numerous types of semiconductor devices (Lin; ¶0020).
Modified Kao is silent regarding wherein a concentration of the dopants in the doped conductive region is about 1 to about 2 orders higher than a concentration of dopants in the substrate.
In the same field of endeavor, Dyer teaches a trench capacitor (Fig. 12; ¶0073) comprising a doped conductive region (12) surrounding the trench (11) (¶0055) comprising dopants of conductivity different (12 has a second conductivity type; ¶0055) from a conductivity of the substrate (6) (first conductivity type; ¶0049), wherein a concentration of the dopants in the doped conductive region (second conductivity type 12) is about 1 to about 2 orders higher (¶0055) than a concentration of dopants in the substrate (first conductivity type of 6; ¶0049).
Absent any evidence of criticality, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the dopant configuration of Dyer for that of the trench capacitor of modified Kao in order to provide a deep trench capacitor (Dyer; ¶0073) with good capacitance, and/or for its art recognized equivalence for the same purpose of providing a deep trench capacitor in a semiconductor device (MPEP 2144.06).
Regarding Claim 30, modified Kao teaches the structure of claim 27, wherein the first IC die comprises a logic die (comprises FinFETs {¶0014} which are used in logic devices) or a memory die, and wherein the second IC die comprises a system-on-chip (SoC) die (second die of 320 comprises passive and active components).
This limitation of “the second IC die comprises a system-on-chip die” is implicitly satisfied by the structure of claim 27 because it is the intended use of the structure, and the filed-specification does not define additional structural details required by a “system-on chip” die. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. See In re Swinehart, 169 USPQ 226 (C.C.P.A. 1971), MPEP 2114 I.
Regarding Claim 31, modified Kao teaches the structure of claim 27, wherein the first IC die (IC1) further comprises:
a first interconnect structure (top half of 322) disposed on the trench capacitor (of trench 317) and comprising a first dielectric layer (shaded area) and a first metal line (metal lines; ¶0027) disposed in the first dielectric layer (as shown in Fig. 3);
a second interconnect structure (306; ¶0026) disposed on the first semiconductor device (110) and comprising a second dielectric layer (shaded area) and a second metal line (¶0026) disposed in the second dielectric layer (as shown in Fig. 3); and
a conductive through-via (through via comprising vias 340 and vias directly above/below and contacting 340; ¶0031; hereinafter TSV) extending through the substrate (302) and into the first and second dielectric layers and in physical contact with the first and second metal lines (TSV is in physical contact with the laterally extending metal lines in the top-half of 322 and 306 respectively).
Kao is silent regarding explicitly disclosing the shaded areas of 306 and top half of 322 in Fig. 3 are dielectric layers. However, Kao shows more detail in Fig. 1 and Fig. 9, wherein a first interconnect structure (120) disposed on the trench capacitor (capacitor in trench 112) comprises first metal lines (¶0022) and first dielectric layers (shaded layers 142a/142b; ¶0021), a second interconnect structure (104; ¶0015) disposed on the first semiconductor device (110) comprises second metal lines (¶0016) and second dielectric layers (shaded layers 106a/106b/106c; ¶0016); wherein a conductive through via (Fig. 9; 186+vias directly contacting above and below 186; ¶0037) extends into the first and second dielectric layers to physically contact the metal line (laterally extending portion of metal lines).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the detailed features of Fig. 1/Fig. 9 of Kao for the non-detailed features shown in Fig. 3 of Kao because they are art recognized equivalent features serving the same purposes in the respective figures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights