Prosecution Insights
Last updated: July 17, 2026
Application No. 17/962,634

OXIDE FIELD TRENCH POWER MOSFET WITH A MULTI EPITAXIAL LAYER SUBSTRATE CONFIGURATION

Non-Final OA §102
Filed
Oct 10, 2022
Priority
Oct 31, 2021 — provisional 63/273,975
Examiner
ISAAC, STANETTA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics N.V.
OA Round
2 (Non-Final)
86%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
48%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
824 granted / 963 resolved
+17.6% vs TC avg
Minimal -37% lift
Without
With
+-37.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
47 currently pending
Career history
1022
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.7%
+22.7% vs TC avg
§102
35.6%
-4.4% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 963 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to the amendment filed on 01/29/26. Claims 12-27 are pending. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. The rejection of claim(s) 1-27 under 35 U.S.C. 102(a)(1) as being anticipated by Yedinak et al. (US PGPub 2014/0273374, hereinafter referred to as “Yedinak”, IDS reference) has been maintained for reasons of record. Yedinak discloses the semiconductor method as claimed. See figures 1-17 and corresponding text, where Yedinak teaches, in claim 12, a method of fabricating a semiconductor substrate (105) including a base substrate layer surmounted by at least three epitaxial layers (110), comprising: in an epitaxial tool: controlling a dopant setting at a constant level ([0027], the dopant are constant and formed in-situ); and with the constant level for the dopant setting, performing three consecutive epitaxial growth processes (figure 13; [0028-0033]), wherein a different dilute level (examiner view that with each concentration of where the lower dopant concentration of the upper portion of the epitaxial layer and higher concentration in the bottom portion of the epitaxial layer is defined as being diluted levels) is set for each epitaxial growth process, to: form a first epitaxial layer (figure 14; [0025]) on the base substrate layer (105), said first epitaxial layer having a first resistivity controlled by a corresponding first dilute level (the examiner views that the resistivity is controlled by the level of dopant concentrations within the each of the epitaxial layers, where the epitaxial layer with a higher or highest concentration will have a lower resistivity verses an epitaxial layer having a lower of lowest concentration of dopants); form a second epitaxial layer (figure 14; [0025]) on the first epitaxial layer, said second epitaxial layer having a second resistivity controlled by a corresponding second dilute level (the examiner views that the resistivity is controlled by the level of dopant concentrations within the each of the epitaxial layers, where the epitaxial layer with a higher or highest concentration will have a lower resistivity verses an epitaxial layer having a lower of lowest concentration of dopants); and form a third epitaxial layer (figure 14; [0025]) on the second epitaxial layer, said third epitaxial layer having a third resistivity controlled by a corresponding third dilute level (the examiner views that the resistivity is controlled by the level of dopant concentrations within the each of the epitaxial layers, where the epitaxial layer with a higher or highest concentration will have a lower resistivity verses an epitaxial layer having a lower of lowest concentration of dopants) (figure 13; [0028-0033]). Yedinak teaches, in claim 13, wherein third resistivity is higher than the second resistivity, and wherein the second resistivity is higher than the first resistivity (figure 14; [0045-0052]) (the examiner views that the resistivity is controlled by the level of dopant concentrations within the each of the epitaxial layers, where the epitaxial layer with a higher or highest concentration will have a lower resistivity verses an epitaxial layer having a lower of lowest concentration of dopants). Yedinak teaches, in claim 14, wherein the second epitaxial layer has a second dopant concentration, wherein the third epitaxial layer has a third dopant concentration, and wherein the second dopant concentration is greater than the third dopant concentration (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 15, wherein the third dopant concentration has a gradient increasing as a function of depth in the third epitaxial layer (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 16, wherein the second dopant concentration is substantially constant as a function of depth in the second epitaxial layer (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 17, wherein the first epitaxial layer has a first dopant concentration, wherein the second epitaxial layer has a second dopant concentration, and wherein the third dopant concentration is greater than the second dopant concentration (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 18, wherein the first dopant concentration has a gradient increasing as a function of depth in the first epitaxial layer (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 19, wherein the second dopant concentration is substantially constant as a function of depth in the second epitaxial layer (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 20, a method of fabricating a semiconductor substrate including a base semiconductor substrate region (105) covered by a stack of three epitaxial semiconductor regions (110), comprising: in an epitaxial tool: (figures 13 and 14; [0028-0033], [0045-0052]) controlling a dopant setting at a constant level ; and with the constant level for the dopant setting, performing three consecutive epitaxial growth processes, wherein a different dilute level is set for each epitaxial growth process, to: form a first epitaxial semiconductor region covering the base semiconductor substrate region, said first epitaxial semiconductor region having a first resistivity controlled by a corresponding first dilute level (examiner view that with each concentration of where the lower dopant concentration of the upper portion of the epitaxial layer and higher concentration in the bottom portion of the epitaxial layer is defined as being diluted levels); form a second epitaxial semiconductor region covering the first epitaxial semiconductor region, said second epitaxial semiconductor region having a second resistivity controlled by a corresponding second dilute level (examiner view that with each concentration of where the lower dopant concentration of the upper portion of the epitaxial layer and higher concentration in the bottom portion of the epitaxial layer is defined as being diluted levels); and form a third epitaxial semiconductor region covering the second epitaxial semiconductor region, said third epitaxial semiconductor region having a third resistivity controlled by a corresponding third dilute level (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 21, wherein third resistivity is higher than the second resistivity, and wherein the second resistivity is higher than the first resistivity (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 22, wherein the second epitaxial semiconductor region has a second dopant concentration, wherein the third epitaxial semiconductor region has a third dopant concentration, and wherein the second dopant concentration is greater than the third dopant concentration (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 23, wherein the third dopant concentration has a gradient increasing as a function of depth in the third epitaxial semiconductor region (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 24, wherein the second dopant concentration is substantially constant as a function of depth in the second epitaxial semiconductor region (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 25, wherein the first epitaxial semiconductor region has a first dopant concentration, wherein the second epitaxial semiconductor region has a second dopant concentration, and wherein the third dopant concentration is greater than the second dopant concentration (figures 13 and 14; [0028-0033], [0045-0052]). Yedinak teaches, in claim 26, wherein the first dopant concentration has a gradient increasing as a function of depth in the first epitaxial semiconductor region (figure 14; [0045-0052]). Yedinak teaches, in claim 27, wherein the second dopant concentration is substantially constant as a function of depth in the second epitaxial semiconductor region (figure 14; [0045-0052]). Response to Arguments Applicant’s arguments with respect to claim(s) 12-27 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner would like to note that although there are no new grounds for rejection a new office action has be submitted to further explain the examiner’s view regarding the prior art of record and to further clarify position. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/Examiner, Art Unit 2898 May 29, 2026
Read full office action

Prosecution Timeline

Oct 10, 2022
Application Filed
Oct 31, 2025
Non-Final Rejection mailed — §102
Jan 29, 2026
Response Filed
Jun 03, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
86%
Grant Probability
48%
With Interview (-37.1%)
2y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 963 resolved cases by this examiner. Grant probability derived from career allowance rate.

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