DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 09/17/2025. Claims 1-19 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 11/06/2022.
Oath/Declaration
The oath or declaration filed on 10/10/2022 is acceptable.
Election/Restrictions
Applicant’s election, without traverse species I (claims 1-19), in the “Response to Election / Restriction Filed” filed on 09/17/2025 is acknowledged. This office action considers claims 1-19 are thus pending for prosecution.
Claim Objections
Claim 9 is objected to because of the following informalities:
Claim 9 recites the limitation “wherein a width of a top surface of the contact plug is greater than a width of a top surface of the dummy contact.” in line 1-2, lacks proper antecedent basis. It appears claim should be “wherein a width of a top surface of each of the contact plugs is greater than a width of a top surface of the dummy contact”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 8-12 and 14-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE (US 2018/0247953 A1; hereafter LEE).
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Regarding claim 1. LEE discloses a semiconductor memory device, comprising:
a lower insulating layer (Fig. [4], insulating layer 147, Para [ 0075]);
a dummy stack (dummy buffer stack structure DM, Para [ 0043]) on the lower insulating layer (Fig. [4], insulating layer 147, Para [ 0075]);
a source structure (Fig. [4], source stack structure SR, Para [ 0121-0126]) arranged at a same level as the lower insulating layer (Fig. [4], insulating layer 147, Para [ 0075]);
a cell stack (cell stack structures CS, Para [ 0043]) on the source structure (Fig. [4], source stack structure SR, Para [ 0121-0126]);
a plurality of contact plugs (contact plugs 193B, Para [ 0046]) passing through the dummy stack (dummy buffer stack structure DM, Para [ 0043]); and
a dummy contact (dummy conductive rings 171DR1, Para [ 0067-0069] and also shown figure [9c,9d]) passing through a portion of the dummy stack (dummy buffer stack structure DM, Para [ 0043]) and arranged between the plurality of contact plugs (contact plugs 193B, Para [ 0046]),
wherein each of the dummy (dummy buffer stack structure DM, Para [ 0043]) and cell stacks (cell stack structures CS, Para [ 0043]) includes a plurality of first material layers (Fig. [4], lower stack 151/153 and lower stack 151/171G) separated from each other, the first material layers stacked on top of each other (Fig. [4], lower stack 151/153 and lower stack 151/171G),
wherein the dummy stack (dummy buffer stack structure DM, Para [ 0043]) further includes a plurality of second material layers (Fig. [4], upper stack 151/153) arranged alternately with the plurality of first material layers (Fig. [4], lower stack 151/153) on the lower insulating layer (Fig. [4], insulating layer 147, Para [ 0075]), and
wherein the cell stack (Fig. [4], cell stack structures CS, Para [ 0043]) further includes a plurality of third material layers (upper stack 151/171G) arranged alternately with the plurality of first material layers (lower stack 151/171G) on the source structure (Fig. [4], source stack structure SR, Para [ 0121-0126]).
Regarding claim 2. LEE discloses the semiconductor memory device of claim 1, LEE further discloses further comprising a plurality of cell plugs (Cell pillars CPL, Para [ 0143]) passing through the cell stack (Fig. [4], cell stack structures CS, Para [ 0043]), wherein each of the plurality of cell plugs (Cell pillars CPL, Para [ 0143]) include a channel layer ( channel 167, Para [ 0059]) and a memory layer surrounding a sidewall of the channel layer (first and second memory patterns ML1 and ML2 surrounding the channel layer 167”, Para [ 0059-0061]).
Regarding claim 3. LEE discloses the semiconductor memory device of claim 2, LEE further discloses wherein the source structure (Fig. [4], source stack structure SR, Para [ 0121-0126]) includes a first source layer and a second source layer (Fig. [4], a first source conductive layer 141 and a second source conductive layer 185, Para [ 0055]), the second source layer arranged on the first source layer (Fig. [4], a first source conductive layer 141 and a second source conductive layer 185, Para [ 0055]).
Regarding claim 5. LEE discloses the semiconductor memory device of claim 1, LEE further discloses wherein a height of the dummy contact (dummy conductive rings 171DR1, Para [ 0067-0069]) is smaller than a height of each of the contact plugs (contact plugs 193B, Para [ 0046]).
Regarding claim 8. LEE discloses the semiconductor memory device of claim 1, LEE further discloses further comprising:
a vertical barrier (step shape region, Para [ 0063-0066]) arranged between the dummy stack (dummy buffer stack structure DM, Para [ 0043]) and the cell stack (cell stack structures CS, Para [ 0043]); and a support pillar passing (contact holes PH region, Para [ 0071]) through the dummy stack (dummy buffer stack structure DM, Para [ 0043]).
Regarding claim 9. LEE discloses the semiconductor memory device of claim 1, LEE further discloses wherein a width of a top surface of the contact plug (contact plugs 193B, Para [ 0046]) is greater than a width of a top surface of the dummy contact (dummy conductive rings 171DR1, Para [ 0067-0069]).
Regarding claim 10. LEE discloses a semiconductor memory device, comprising:
a substrate (Fig. [4], substrate 101, Para [ 0050]) on which a cell array region (cell stack structures CS, region I, Para [ 0043]) and a connection region (Fig. [4], region III) are defined;
a peripheral circuit structure (Fig. [4], ST1 structure includes peripheral circuit, Para [ 0050]) on the substrate (Fig. [4], substrate 101, Para [ 0050]);
a dummy stack (dummy buffer stack structure DM, Para [ 0043]) arranged on the connection region (Fig. [4], region III);
a cell stack (cell stack structures CS, Para [ 0043]) arranged on the cell array region (cell stack structures CS, region I, Para [ 0043]);
a plurality of contact plugs (contact plugs 193B, Para [ 0046]) passing through the dummy stack (dummy buffer stack structure DM, Para [ 0043]);
cell plugs (Cell pillars CPL, Para [ 0143]) passing through the cell stack (cell stack structures CS, Para [ 0043]); and
a dummy contact (dummy conductive rings 171DR1, Para [ 0067-0069] and also shown figure [9c,9d]) passing through a portion of the dummy stack (dummy buffer stack structure DM, Para [ 0043]).
Regarding claim 11. LEE discloses the semiconductor memory device of claim 10, LEE further discloses wherein the dummy (dummy buffer stack structure DM, Para [ 0043]) stack includes dummy insulating layers and sacrificial insulating layers (insulating layers 151 and sacrificial insulating layers 153, Para [ 0067]) stacked alternately with each other, and wherein the cell stack (cell stack structures CS, region I, Para [ 0043]) includes interlayer insulating layers and conductive patterns stacked alternately with each other (conductive patterns 171G and interlayer insulating layers 151, Para [ 0066]).
Regarding claim 12. LEE discloses the semiconductor memory device of claim 10, LEE further discloses further comprising a plurality of lower contacts (resistor conductive layer 119 and connecting structures LS, Para [ 0081]) coupling the peripheral circuit structure (Fig. [4], ST1 structure includes peripheral circuit, Para [ 0050]) to the plurality of contact plugs (contact plugs 193B, Para [ 0046]).
Regarding claim 14. LEE discloses the semiconductor memory device of claim 10, LEE further discloses further comprising a vertical barrier (slit insulating layer 187, Para [ 0127]) surrounding the dummy stack (dummy buffer stack structure DM, Para [ 0043]).
Regarding claim 15. LEE discloses the semiconductor memory device of claim 10, LEE further discloses wherein each of the cell plugs (cell pillars CPL, Para [ 059-0062]) includes a channel structure (channel layer 167, Para [ 0059-0062]) and a memory layer surrounding the channel structure (first and second memory patterns ML1 and ML2 surrounding the channel layer 167, Para [ 0059-0062]), and wherein the memory layer includes a tunnel isolation layer, a data storage layer, and a blocking insulating layer stacked sequentially on a surface of the channel structure ( Para [ 0059-0062]).
Regarding claim 16. LEE discloses the semiconductor memory device of claim 10, LEE further discloses wherein a top width of each of the contact plugs (contact plugs 193B, Para [ 0046]) is greater than a top width of the dummy contact (dummy conductive rings 171DR1, Para [ 0067-0069]).
Regarding claim 17. LEE discloses the semiconductor memory device of claim 10, LEE further discloses wherein the dummy contact (dummy conductive rings 171DR1, Para [ 0067-0069]) having a smaller length than each of the contact plugs (contact plugs 193B, Para [ 0046]) is arranged in the dummy stack (dummy buffer stack structure DM, Para [ 0043]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 2018/0247953 A1; hereafter LEE) in view of LEE (2016/0225697 A1; hereafter LEE’697).
Regarding claim 13. LEE discloses the semiconductor memory device of claim 10, LEE further discloses further comprising:
a first upper insulating layer (slit insulating layer 187, Para [ 0127]) arranged on the dummy stack (dummy buffer stack structure DM, Para [ 0043]) and the cell stack (cell stack structures CS, Para [ 0043]); and a support pillar (insulating layers 181 may be formed of a nitride material, Para [ 0122]) passing through the dummy stack (dummy buffer stack structure DM, Para [ 0043]).
But LEE does not disclose explicitly wherein the first upper insulating layer and the support pillar include a same material.
In a similar field of endeavor, LEE’697 discloses wherein the first upper insulating layer and the support pillar include a same material (Para [0026] discloses “The slit insulating layers 17 and 20 may include an oxide, a nitride, etc. Therefore, both slit insulating layer and insulating layer 181 can be made with same nitride material).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine LEE in light of LEE’697 teaching “wherein the first upper insulating layer and the support pillar include a same material (Para [0026] discloses “The slit insulating layers 17 and 20 may include an oxide, a nitride, etc. Therefore, both slit insulating layer and insulating layer 181 can be made with same nitride material)” for further advantage such as improve device performance by using well-known material.
Allowable Subject Matter
Claims 4, 6-7 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 4. The semiconductor memory device of claim 2, wherein the channel layer of each of the cell plugs is directly coupled to the source structure.
Regarding claim 6. The semiconductor memory device of claim 1, wherein the plurality of contact plugs include first to third contact plugs arranged in a line, wherein the second contact plug is arranged between the first contact plug and the third contact plug, and wherein a distance between the first contact plug and the second contact plug is smaller than a distance between the second contact plug and the third contact plug.
Claim 7 is objected based on the dependency of claim 6.
Regarding claim 18. The semiconductor memory device of claim 10, wherein the plurality of contact plugs include first to third contact plugs passing through the dummy stack and arranged in a line, wherein the second contact plug is arranged between the first contact plug and the third contact plug, and wherein a distance between the first contact plug and the second contact plug is smaller than a distance between the second contact plug and the third contact plug.
Claim 19 is objected based on the dependency of claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898