DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Ahn (KR 20080019915). A machine translation is attached to this office action for Applicant’s convenience and paragraph numbers are made in reference to this attachment.
1. (Currently amended) A method of manufacturing a semiconductor device, the method comprising:
forming first (Fig.3d (D3) and [0091]) and second via holes (Fig.3D (D2) and [0091] in a substrate (Fig.3D (103-105) and [0088-0091];
forming an insulating layer (Fig.3g (109) and [0097-0107]) including a first portion (Fig.3g (109b) and [0101-0107]) and a second portion (Fig.3G (109a) and [0101-0107]), the first portion (Fig.3g (109b) and [0101-0107]) narrowing the first via hole (Fig.3d (D3) and [0101-0107]) to a third via hole (Fig.3g (D3) and [0101-0107]) and the second portion (Fig.3G (109a) and [0101-0107]) narrowing the second via hole (Fig.3d (D2) and [0091]) to a fourth via hole (Fig.3g (D2) and [0101-0107]);
reducing a thickness of the second portion of the insulating layer (Fig.3f-g (109a’-109a) and [0101-0107]) to increase a width of the fourth via hole (Fig.3g (D2) and [0101-0107]); and forming a first through via (Fig.3h (123-D3) and [0108]) and a second through via (Fig.3h (123-D2) and [0108]), the first through via (Fig.3h (123-D3) and [0108]) filling the third via hole (Fig.3g (D3) and [0101-0107]) and the second through via (Fig.3h (123-D2) and [0108]) filling the fourth via hole (Fig.3g (D2) and [0101-0107]) of increased width, wherein the second portion of the insulating layer (Fig.3f-g (109a’-109a) and [0101-0107]) having the reduced thickness (Fig.3h (d1-109a) is thinner than the first portion of the insulating layer (Fig.3h (d2-109b) and [0111]).
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al (US 2022/0139806).
A method of manufacturing a semiconductor device, the method comprising:
forming first and second via holes (Fig.7 (H1’ and H2’) and [0066-0067]) in a substrate (Fig.7 (110) and [0028]);
forming an insulating layer (Fig.8 (151A/151B/162) and [0068-0072]) including a first portion (Fig.8 (151A)) and a second portion (Fig. 8 (151B)), the first portion (Fig.8 (151A)) narrowing the first via hole (Fig.7 (H1’)) to a third via hole (Fig.8 (H1)) and the second portion (Fig. 8 (151B)) narrowing the second via hole (Fig.7 (H2’)) to a fourth via hole (Fig.8 (H2));
reducing a thickness of the second portion of the insulating layer to increase a width of the fourth via hole (Fig.s 8-9 (162/151A and 151B) and [0070-0072]); and
forming a first through via and a second through via (Fig.10 (155A and 155B) and [0075]), the first through via filling the third via hole (Fig.10 (150A) and the second through via filling the fourth via hole of increased width (Fig.10 (150B) wherein the second portion of the insulating layer (Fig. 8-9 (151B)) and [0070-0072]) having the reduced thickness (thickness is zero see Fig. 9 [0072]) is thinner than the first portion of the insulating layer (Fig.8 (151A/151B)) (zero is thinner than the first portion which remains).
The method of claim 1, wherein the first via hole has the same width as the second via hole [0027].
The method of claim 1, wherein the insulating layer is formed such that: the first portion of the insulating layer covers a sidewall surface of the first via hole, and the second portion of the insulating layer covers a sidewall surface of the second via hole (Fig.8 (151A/151B/162) and [0068-0072]).
4. The method of claim 1, wherein the insulating layer is formed such that the first portion of the insulating layer has substantially the same thickness as the second portion of the insulating layer (Fig.8 (151A/151B/162) and [0068-0072]).
5. The method of claim 1, wherein reducing the thickness of the second portion of the insulating layer includes: forming a shielding pattern (Fig.8 (162) and [068-0072]) that shields the first portion of the insulating layer (Fig.8 (151A- top) while leaving the second portion of the insulating layer exposed (Fig.8 (151A- sidewalls); and recessing a portion of the second portion of the insulating layer left exposed by the shielding pattern [0068-0072]).
6. The method of claim 5, wherein the shielding pattern is formed to fill the third via hole while leaving the fourth via hole open (Fig.8 (162) and [068-0072])- it partially fills and partially leaves open the third and fourth holes).
7. The method of claim 5, wherein the shielding pattern includes a photoresist pattern [0065].
8. The method of claim 1, wherein the fourth via hole of increased width has a wider width than the third via hole (Fig.9 (H1 and H2)).
9. The method of claim 1, wherein the second through via has a wider width than the first through via (Fig.9 (H1 and H2)). .
10. The method of claim 1, wherein the second through via has a wider width than the first through via by twice the reduced thickness of the second portion of the insulating layer (Fig.9 (H1 and H2))- implicit since the sidewalls on both sides are etched).
11. The method of claim 1, wherein forming the first through via and the second through via includes: forming a conductive layer filling the third and fourth via holes (Fig.10 (155)); and planarizing the conductive layer to separate the conductive layer into the first through via filling the third via hole and the second through via filling the fourth via hole (Fig.11 (155) and [0077])).
12. The method of claim 11, wherein the conductive layer includes copper (Cu) [0075].
13. The method of claim 1, further comprising recessing a portion of the substrate and exposing end portions of the first through via and the second through via after forming the first through via and the second through via (Fig.11-13 (155)) and [0077]).
14. The method of claim 1, wherein the insulating layer includes silicon dioxide [0069].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2022/0139806), in further view of Ahn (KR 20080019915).
In reference to claim 1, Park teaches the following claimed limitations:
A method of manufacturing a semiconductor device, the method comprising:
forming first and second via holes (Fig.7 (H1’ and H2’) and [0066-0067]) in a substrate (Fig.7 (110) and [0028]);
forming an insulating layer (Fig.8 (151A/151B/162) and [0068-0072]) including a first portion (Fig.8 (151A)) and a second portion (Fig. 8 (151B)), the first portion (Fig.8 (151A)) narrowing the first via hole (Fig.7 (H1’)) to a third via hole (Fig.8 (H1)) and the second portion (Fig. 8 (151B)) narrowing the second via hole (Fig.7 (H2’)) to a fourth via hole (Fig.8 (H2));
reducing a thickness of the second portion of the insulating layer to increase a width of the fourth via hole (Fig.s 8-9 (162/151A and 151B) and [0070-0072]); and
forming a first through via and a second through via (Fig.10 (155A and 155B) and [0075]), the first through via filling the third via hole (Fig.10 (150A) and the second through via filling the fourth via hole of increased width (Fig.10 (150B).
Although the Examiner finds that Park does teach Applicant’s amended claim limitation as explained in the 102 rejection made above, and explained further in the response to arguments made below\- assuming arguendo, that the Applicant is correct and Park does not teach Applicant’s amended limitation : wherein the second portion of the insulating layer having the reduced thickness is thinner than the first portion of the insulating layer.
However, Ahn teaches wherein the second portion of the insulating layer (Fig.3f-g (109a’-109a) and [0101-0107]) having the reduced thickness (Fig.3h (d1-109a) is thinner than the first portion of the insulating layer (Fig.3h (d2-109b) and [0111]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Park’s teachings to include a varying insulating thickness as taught by Ahn because as Ahn teaches- varying the insulating layer thickness varies the electrical properties of the through electrode structure and may be a simple way to customize electrical properties [0101-0111]).
The remaining claim limitations are in reference to Park (‘806):
2. The method of claim 1, wherein the first via hole has the same width as the second via hole [0027].
3. The method of claim 1, wherein the insulating layer is formed such that: the first portion of the insulating layer covers a sidewall surface of the first via hole, and the second portion of the insulating layer covers a sidewall surface of the second via hole (Fig.8 (151A/151B/162) and [0068-0072]).
4. The method of claim 1, wherein the insulating layer is formed such that the first portion of the insulating layer has substantially the same thickness as the second portion of the insulating layer (Fig.8 (151A/151B/162) and [0068-0072]).
5. The method of claim 1, wherein reducing the thickness of the second portion of the insulating layer includes: forming a shielding pattern (Fig.8 (162) and [068-0072]) that shields the first portion of the insulating layer (Fig.8 (151A- top) while leaving the second portion of the insulating layer exposed (Fig.8 (151A- sidewalls); and recessing a portion of the second portion of the insulating layer left exposed by the shielding pattern [0068-0072]).
6. The method of claim 5, wherein the shielding pattern is formed to fill the third via hole while leaving the fourth via hole open (Fig.8 (162) and [068-0072])- it partially fills and partially leaves open the third and fourth holes).
7. The method of claim 5, wherein the shielding pattern includes a photoresist pattern [0065].
8. The method of claim 1, wherein the fourth via hole of increased width has a wider width than the third via hole (Fig.9 (H1 and H2)).
9. The method of claim 1, wherein the second through via has a wider width than the first through via (Fig.9 (H1 and H2)). .
10. The method of claim 1, wherein the second through via has a wider width than the first through via by twice the reduced thickness of the second portion of the insulating layer (Fig.9 (H1 and H2))- implicit since the sidewalls on both sides are etched).
11. The method of claim 1, wherein forming the first through via and the second through via includes: forming a conductive layer filling the third and fourth via holes (Fig.10 (155)); and planarizing the conductive layer to separate the conductive layer into the first through via filling the third via hole and the second through via filling the fourth via hole (Fig.11 (155) and [0077])).
12. The method of claim 11, wherein the conductive layer includes copper (Cu) [0075].
13. The method of claim 1, further comprising recessing a portion of the substrate and exposing end portions of the first through via and the second through via after forming the first through via and the second through via (Fig.11-13 (155)) and [0077]).
14. The method of claim 1, wherein the insulating layer includes silicon dioxide [0069].
Response to Arguments
Applicant's arguments filed 10/2/25 have been fully considered but they are not persuasive. The arguments state, “In contrast, as shown in the FIGS. 5 and 6, below, the presently claimed invention reduces the thickness of the second portion of the insulating layer by reducing the thickness of the second portion of the insulating layer, so that the second portion 502-1 of the insulating layer has a reduced thickness from T2 to T3. As shown in FIG. 6, even after performing the process of reducing the thickness of the second portion of the insulating layer, the second portion 502-1 of the insulating layer does not reveal its lower portion, and therefore, the process of removing the electrode insulating film 151 (151A, 151B) and a portion of the interlayer insulating film 131’ shown in Park FIG. 9 cannot teach the process of reducing the thickness of the second portion of the insulating layer of the presently claimed invention.”
Applicant is respectfully reminded that the name of the game is the claim. Applicant’s claim language does not preclude reducing the thickness to zero in accordance with the Examiner’s interpretation. The argument as recited above that “even after performing the process of reducing the thickness of the second portion of the insulating layer, the second portion 502-1 of the insulating layer does not reveal its lower portion” is not found in the Applicant’s claim language- and therefore is not a persuasive argument.
Moreover, note the additional new rejections made by Ahn (KR 20080019915) and Park (‘806) in further view of Ahn (‘915).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Boyd et al (US 2021/0217655); Lee et al (US 2013/0005133); Choi et al 9US 2023/0077803); Han et al (US 2022/0084885) teach similar via fabrication methods.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAURA M MENZ/Primary Examiner, Art Unit 2813
12/8/25
Machine translation of KR 20080019915 provided by IP.com (paragraph numbers added for Applicant’s convenience) :
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a capacitor of a semiconductor device having a variable capacitor capacity and a method of manufacturing the same.
The capacitor of the semiconductor device according to the present invention is formed through a dual damascene process, has a structure in which a plurality of subcapacitors are connected in parallel, the thickness of the subcapacitor, the number, the size of the damascene pattern, and the like. Capacitor capacity is variably adjustable by adjusting
In addition, the capacitor of the semiconductor device according to the present invention can not only form a sufficient capacitance, but also can form a capacitor at the time of damascene pattern formation, thereby facilitating and simplifying the process.
Capacitor, MIM, Dual Damasin
Detailed Description:
A fabrication method of a capacitor for semiconductor device
1 is a cross-sectional view showing a MIM capacitor of a conventional semiconductor device.
2 is a cross-sectional view showing a capacitor of a semiconductor device according to an embodiment of the present invention.
3A to 3I are cross-sectional views illustrating a process sequence for manufacturing a capacitor of a semiconductor device according to the present invention.
<Description of Signs of Major Parts of Drawings>
100: first insulating film 101: first conductor
103: second insulating film 104: third insulating film
105: fourth insulating film 107: barrier metal film
109 dielectric film 121 contact electrode
123: second conductor 131: first metal wiring
133: second metal wiring
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device having variable capacitor capacity and sufficient capacity.
Recently, a semiconductor device in which an analog capacitor in a logic circuit is integrated with a logic circuit by a high integration technology of a semiconductor device has been researched and developed and used as a product. Analog capacitors used in the logic circuit are mainly used in the form of PIP (Polysilicon / Insulator / Polysilicon) and MIM (Metal / Insulator / Metal).
These PIP or MIM type capacitors, unlike metal oxide silicon (MOS) type capacitors or junction capacitors, are bias-independent and are used in analog products requiring capacitor precision.
Here, the MIM capacitor can be manufactured at the time of forming the metal wiring because the bottom electrode and the top electrode are made of a material.
1 is a cross-sectional view showing a MIM capacitor of a conventional semiconductor device.
Referring to FIG. 1, a MIM capacitor of a conventional semiconductor device may include a bottom electrode 11, an insulator 13, and a top electrode 15 on a semiconductor substrate 10 on which a lower structure is formed. ) Is sequentially stacked, and the lower electrode 11 and the upper electrode 15 is made of metal.
An interlayer insulating layer 17 is formed on the capacitor to a predetermined thickness, and a first via hole 25 for exposing the lower electrode 11 is formed in the interlayer insulating layer 17, and the upper electrode 15 is formed. The second via hole 27 is formed to expose the predetermined amount.
The first via hole 21 is filled with a first plug 21 made of metal, and the second via hole 27 is filled with a second plug 23 made of metal.
In addition, a first metal wire 31 connected to the first plug 21 and a second metal wire 33 connected to the second plug 23 are formed on the interlayer insulating layer 17. A signal for forming capacitance through the wiring 31 and the second metal wiring 33 is input to the lower electrode 11 and the upper electrode 15 of the capacitor.
However, in the capacitor of the conventional semiconductor device, the lower electrode 11, the insulating film 13, and the upper electrode 15 are formed flat in a flat structure, and thus, the size of the capacitor needs to be changed in order to increase the capacitor capacity. Is generated.
Recently, as semiconductor devices have been highly integrated, the area occupied by capacitors in the devices has also been reduced. Therefore, research on methods having a large capacitor capacity within the same area is required. Accordingly, studies on improving the capacitance by increasing the effective area of the capacitor is active.
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a capacitor of a semiconductor device capable of variably operating the capacitor capacity by increasing the capacitor capacity by increasing the effective area of the capacitor.
In order to achieve the above object, a capacitor of a semiconductor device according to the present invention comprises: a capacitor lower metal wiring formed on a substrate; An insulating film formed on the substrate with a plurality of damascene patterns exposing the capacitor lower metal wires; A capacitor lower electrode formed on the insulating film on which the damascene pattern is formed; Dielectric films having different thicknesses formed in the plurality of damascene patterns; A capacitor upper electrode embedded in the damascene pattern in which dielectric films having different thicknesses are formed; A contact electrode is formed on at least one of the plurality of damascene patterns and is connected to the capacitor lower metal line.
The capacitor lower metal wire and the capacitor lower electrode are in contact with each other through the damascene pattern.
The contact electrode and the capacitor upper electrode may be formed of the same metal material.
The dielectric layers having different thicknesses formed in the damascene pattern may have different capacitor capacities.
And a first metal wire connected to the contact electrode to apply a bias to the capacitor lower metal wire, and a second metal wire connected to a capacitor upper electrode of a plurality of damascene patterns having a dielectric film having different thicknesses. It features.
Capacitor capacity is adjusted according to the number of capacitor upper electrodes of the damascene pattern connected to the second metal wiring.
Capacitor capacity is adjusted according to the thicknesses of dielectric films having different thicknesses formed on the plurality of damascene patterns.
In order to achieve the above object, a method of manufacturing a capacitor of a semiconductor substrate according to the present invention includes: forming a capacitor lower metal wiring on the substrate; Forming an insulating film on the entire surface of the substrate; Forming a plurality of damascene patterns by forming a via hole and a trench in the insulating layer to expose the capacitor lower metal wiring; Forming a capacitor lower electrode by depositing a barrier metal layer on the insulating layer on which the damascene pattern is formed; Forming a dielectric film on an entire surface of the substrate on which the damascene pattern is formed; Depositing a mask pattern on the dielectric layer and etching the dielectric layer to form dielectric layers having different thicknesses in the damascene pattern; And forming a capacitor upper electrode by forming and planarizing a conductive metal in the damascene pattern in which dielectric layers having different thicknesses are formed.
In the forming of the capacitor upper electrode,
At least one of the plurality of damascene patterns may further include a contact electrode connected to the capacitor lower metal line.
Depositing a mask pattern on the dielectric layer and etching the dielectric layer to form a dielectric layer having a different thickness in the damascene pattern, the method comprising: forming a first mask pattern on the dielectric layer; Etching the dielectric film at the first damascene pattern position using the first mask pattern as an etching mask; Removing the first mask pattern and forming a second mask pattern on the dielectric layer; Etching the dielectric layers at the first and second damascene pattern positions using the second mask pattern as an etching mask; Exposing the dielectric film at a third damascene pattern position to remove the second mask pattern.
The dielectric film at the first damascene pattern position forms a first dielectric layer having a first thickness, and the dielectric film at the second damascene pattern position forms a second dielectric layer having a second thickness, and the third damascene pattern at The dielectric film forms a third dielectric film of a third thickness,
The first to third thicknesses may be different thicknesses.
In the first to third dielectric layers, the thickness of the first dielectric layer is the thinnest and the thickness of the third dielectric layer is thickest.
The capacitor lower electrode is formed of a multilayer film including TaN or TaN, a multilayer film including TiN or TiN, a multilayer film including WN or WN, or formed of any one of the multilayer films including TaN, TiN, WN or TaN, TiN, WN. It is characterized by.
The capacitor lower metal wire and the capacitor lower electrode are in contact with each other through the damascene pattern to be electrically connected to each other.
After the step of forming a capacitor upper electrode by forming and planarizing a conductive metal in the damascene pattern in which the dielectric films having different thicknesses are formed,
Forming a first metal wire connected to the contact electrode to apply a bias to the lower metal wire of the capacitor, and a second metal wire connected to a capacitor upper electrode of a plurality of damascene patterns having a dielectric film having different thicknesses; It is characterized by including more.
Capacitor capacity is adjusted according to the number of capacitor upper electrodes of the damascene pattern connected to the second metal wiring.
Capacitor capacity is adjusted according to the thicknesses of dielectric films having different thicknesses formed on the plurality of damascene patterns.
Hereinafter, a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
2 is a cross-sectional view illustrating a capacitor of a semiconductor device according to an embodiment of the present invention.
Referring to FIG. 2, the capacitor of the semiconductor device according to the present invention is formed through a dual damascene process, and has a structure in which the first to third subcapacitors SC1, SC2, and SC3 are connected in parallel. Capacitor capacity can be variably adjusted by adjusting the thickness, number, size of the damascene pattern, and the like of the subcapacitors SC1, SC2, and SC3.
The first insulating film 100 is formed on a substrate on which a lower structure including a semiconductor device, a metal wiring, an insulating film, and the like is formed.
The first insulating film 100 is formed with a first conductor 101 formed by burying a metal by a chemical-mechanical polishing (CMP) method in a state where the first insulating film is formed.
The second insulating film 103, the third insulating film 104, and the fourth insulating film 105 are sequentially formed on the entire surface of the semiconductor substrate on which the first conductor 101 is formed.
In addition, via holes h are formed in predetermined regions of the second to fourth insulating films 103, 104, and 105, and trenches T are formed in the fourth insulating film 105 together with the via holes h. have. In the etching process for forming the trench T, the third insulating layer 104 may be etched.
After the ashing and cleaning processes are performed on the first to fourth damascene patterns D1, D2, D3, and D4 formed of the via holes h and the trenches T, Ta / TaN, Ti / TiN, etc. The same barrier metal film 107 is formed on the damascene pattern sidewalls and bottom and on the fourth insulating film 105.
The barrier metal film 107 may be formed of a multilayer film including TaN or TaN, a multilayer film including TiN or TiN, and a multilayer film including WN or WN. In addition, it may be formed of any one of the above-mentioned TaN, TiN, WN or a multilayer film including TaN, TiN, WN.
The barrier metal layer 107 is electrically connected to the first conductor 101, and the first conductor 101 is a capacitor metal for applying a bias to the barrier metal 107 serving as a capacitor lower electrode. Perform the role of wiring.
In addition, dielectric layers 109 having different thicknesses are formed on inner sidewalls and bottoms of the second to fourth damascene patterns D2, D3, and D4.
A first dielectric layer 109a having a first thickness d1 is formed in the second damascene pattern D2, and is connected to the first dielectric layer 109a to form a third dielectric layer 109a in the second damascene pattern D3. A second dielectric layer 109b having a second thickness d2 is formed, and is connected to the first and second dielectric layers 109a and 109b to form a third thickness d3 in the fourth damascene pattern D4. The third dielectric film 109c is formed.
Thereafter, a second conductor 123 is deposited on the second to fourth insulating layers 103, 104, and 105 on which the first to fourth damascene patterns D1, D2, D3, and D4 are formed. The second conductor 123 is embedded in the first to fourth damascene patterns D1, D2, D3, and D4 by planarization.
The second conductor 123 buried in the first damascene pattern D1 has a contact electrode connecting a capacitor lower metal wiring thereon to apply a bias to the barrier metal layer 107 serving as the capacitor lower electrode. And a second conductor 123 embedded in the second to fourth damascene patterns D2, D3, and D4 to form a capacitor upper electrode of the capacitor according to the present invention.
In the second damascene pattern D2, the first dielectric layer 109a formed between the capacitor lower electrode formed of the barrier metal layer 107 and the second conductor 123, which is the capacitor upper electrode, may have a predetermined electrostatic force. Accumulate capacity.
In the third damascene pattern D3, the second dielectric layer 109b formed between the capacitor lower electrode formed of the barrier metal layer 107 and the second conductor 123, which is the capacitor upper electrode, has a predetermined electrostatic force. Accumulate capacity.
In the fourth damascene pattern D4, the third dielectric layer 109c formed between the capacitor lower electrode formed of the barrier metal layer 107 and the second conductor 123, which is the capacitor upper electrode, has a predetermined electrostatic force. Accumulate capacity.
Here, the second to fourth damascene patterns D2, D3, and D4 form capacitors, and they are connected in parallel with each other, and the capacitor capacity according to the present invention can be obtained by the following equation.
The capacitor capacity of the first subcapacitor SC1 formed in the second damascene pattern D2 is
[Image Omitted]
The capacitor capacitance of the second subcapacitor SC2 formed in the third damascene pattern D3 is
[Image Omitted]
The capacitor capacitance of the third subcapacitor SC3 formed in the fourth damascene pattern D4 is
[Image Omitted]
Here, C1, C2, and C3 are capacitances (units; F), ε is permittivity, S is electrode area, and d1, d2, and d3 are distances between electrodes.
Therefore, the total capacitor capacity of the capacitor according to the present invention,
[Image Omitted]
On the other hand, the capacitance of the first to third subcapacitors SC1, SC2, and SC3 is inversely different and varies depending on the thicknesses of the first to third dielectric layers 109a, 109b, and 109c. The capacitor capacity is the largest and the capacitor capacity is increased in the order of the second and third subcapacitors SC2 and SC3 (C1> C2> C3).
As described above, the capacitor of the semiconductor device according to the present invention not only can sufficiently form the capacitance as much as possible, but also can form the capacitor at the time of damascene pattern formation, thereby facilitating and simplifying the process.
In addition, since the selected subcapacitors may be connected in parallel to adjust the thickness of the dielectric layer 109 and to obtain a desired capacitance, there is an advantage in that it has excellent utility.
In addition, second to fourth damascene patterns on the fourth insulating layer 105 are formed on the first metal wire 131 in contact with the contact electrode 121 connected to the capacitor lower electrode, and the capacitor upper electrode is formed. The second metal wires 133 may be formed on the D2, D3, and D4 to apply different signals.
In this case, the second metal wire 133 connected to the capacitor upper electrode may be formed on at least one damascene pattern of the second to fourth damascene patterns D2, D3, and D4 to adjust the capacitor capacity.
The number of subcapacitors may be adjusted.
The method of manufacturing the capacitor of the semiconductor device having the structure as described above is as follows.
3A to 3H are cross-sectional views illustrating a process sequence for manufacturing a capacitor of a semiconductor device according to the present invention.
First, as shown in FIG. 3A, a first insulating film 100 is formed on a substrate, and a damascene pattern is formed on the first insulating film 100 to deposit a predetermined conductive metal and planarize it through CMP. .
The planarization process proceeds until the upper surface of the first insulating film 100 appears to form the first conductor 101.
The second insulating film 103, the third insulating film 104, and the fourth insulating film 105 are sequentially deposited on the upper surfaces of the first insulating film 100 and the first conductor 101, and the first mask pattern 181 is provided. To form.
Here, the first conductor 181 is a capacitor lower metal wiring for applying a bias to a capacitor lower electrode formed later.
Next, as illustrated in FIG. 3B, dry etching is performed using the first mask pattern 181 as an etching mask to form a plurality of via holes h in the second to fourth insulating layers 103, 104, and 105. Form.
3C, the first mask pattern 181 is removed, and a second mask pattern 182 is formed on the fourth insulating layer 105 to form the second mask pattern 182. ) Is formed as an etching mask to form a trench T in the fourth insulating layer 105 by dry etching.
In this case, when the trench T is formed, not only the fourth insulating layer 105 but also the third insulating layer 104 may be etched.
As a result, as illustrated in FIG. 3D, first to fourth damascene patterns D1, D2, D3, and D4 are formed by the via hole h and the trench T. As shown in FIG.
The first damascene pattern D1 exposes a part of the capacitor lower metal wiring of the first conductor 101 and connects the capacitor lower metal wiring to an upper portion.
The second to fourth damascene patterns D2, D3, and D4 partially expose the lower metal wirings of the capacitors of the first conductor 101, and the capacitor lower electrodes to be formed later by the bias applied from the lower metal wirings of the capacitors. Is to deliver on.
Next, as shown in FIG. 3E, the barrier metal layer 107 is formed on the second to fourth insulating layers 103, 104, and 105 on which the second to fourth damascene patterns D2, D3, and D4 are formed. Deposit.
The barrier metal film 107 may be formed of a multilayer film including TaN or TaN, a multilayer film including TiN or TiN, and a multilayer film including WN or WN. In addition, it may be formed of any one of the above-mentioned TaN, TiN, WN or a multilayer film including TaN, TiN, WN.
The barrier metal layer 107 contacts the first conductor 101 through the first to fourth damascene patterns D1, D2, D3, and D4, and the second to fourth damascene pattern D2. , The barrier metal film 107 formed on D3, D4 is used as a capacitor lower electrode.
Thereafter, a dielectric film 109 having a third thickness d3 is formed on the entire surface of the substrate on which the barrier metal film 107 is formed.
The dielectric layer 109 is also formed in the first to fourth damascene patterns D1, D2, D3, and D4.
In addition, a third mask pattern 183 is formed on the dielectric layer 109 at the second to fourth damascene patterns D2, D3, and D4, and the exposed dielectric layer 109 is etched using the third mask pattern 183 as an etching mask. .
The dielectric layer 109 may have different thicknesses at sidewalls and bottoms of the damascene pattern, but is defined as an average thickness.
Thereafter, as shown in FIG. 3F, the third mask pattern 183 is removed and the fourth mask pattern 184 is disposed on the dielectric layer 109 at the third and fourth damascene patterns D3 and D4. The first dielectric layer 109a ′ is formed by etching the exposed dielectric layer 109 using the etching mask.
The dielectric layer may have a thickness different from the sidewalls and the bottom of the damascene pattern, but is defined as an average thickness.
Thereafter, as shown in FIG. 3G, the fourth mask pattern 184 is removed, and a fifth mask pattern 185 is formed on the dielectric layer 109 at the fourth damascene pattern D4 and then etched. The first dielectric film 109a and the second dielectric film 109b are formed by etching the exposed dielectric film 109 as a mask.
Thus, the dielectric film at the second damascene pattern D2 forms a first dielectric film 109a having a first thickness d1, and the dielectric film at the third damascene pattern D3 has a second thickness ( A second dielectric film 109b having D2) is formed.
In this case, the first dielectric layer 109a is etched twice so as to be thinner than the thickness of the second dielectric layer 109b.
The remaining dielectric layer 109 after removing the fifth mask pattern 185 becomes a third dielectric layer 109c having a third thickness d3 at the fourth damascene pattern D4.
Accordingly, dielectric layers 109 having different thicknesses are formed in the second to fourth damascene patterns D2, D3, and D4, respectively.
3H, a conductive metal is deposited on the entire surface of the substrate on which the first to third dielectric layers 109a, 109b, and 109c are formed to form a second conductor 123, and the second conductor 123. ) Is planarized to form a second conductor 123 in the via hole h and the trench T. FIG.
The second conductor formed in the first damascene pattern D1 is a contact electrode 121, which is connected to the capacitor lower metal wire to transfer a bias applied from the upper pad to the capacitor lower electrode.
The second conductor 123 formed in the second to fourth damascene patterns D2, D3, and D4 serves as a capacitor upper electrode, and the barrier metal layer 107, which is the capacitor lower electrode, and the first to fifth layers. The third dielectric layers 109a, 109b, and 109c and the second conductor 123 that is the upper electrode of the capacitor form a capacitor.
In this case, if the sizes of the second to fourth damascene patterns D2, D3, and D4 are the same, the first to third portions formed inside the second to fourth damascene patterns D2, D3, and D4 may be used. Since the thicknesses of the dielectric layers 109a, 109b, and 109c are different, the sizes of the second conductors 123 embedded in the second to fourth damascene patterns D2, D3, and D4 are also different.
The capacitor of the semiconductor device formed as described above is formed through a dual damascene process, and has a structure in which the first to third subcapacitors SC1, SC2, and SC3 are connected in parallel.
Here, the capacitance of the subcapacitor may be variably controlled by adjusting the thickness, number, size of the damascene pattern, and the like of the subcapacitor.
Capacities of the first to third subcapacitors SC1, SC2, and SC3 are inversely different from each other depending on the thicknesses of the first to third dielectric layers 109a, 109b, and 109c. The largest capacitor capacity increases in the order of the second and third subcapacitors SC2 and SC3 (C1> C2> C3).
In the second damascene pattern D2, the first dielectric layer 109a formed between the capacitor lower electrode formed of the barrier metal layer 107 and the second conductor 123, which is the capacitor upper electrode, may have a predetermined electrostatic force. Accumulate capacity.
In the third damascene pattern D3, the second dielectric layer 109b formed between the capacitor lower electrode formed of the barrier metal layer 107 and the second conductor 123, which is the capacitor upper electrode, has a predetermined electrostatic force. Accumulate capacity.
In the fourth damascene pattern D4, the third dielectric layer 109c formed between the capacitor lower electrode formed of the barrier metal layer 107 and the second conductor 123, which is the capacitor upper electrode, has a predetermined electrostatic force. Accumulate capacity.
As described above, the capacitor of the semiconductor device according to the present invention not only can sufficiently form the capacitance as much as possible, but also can form the capacitor at the time of damascene pattern formation, thereby facilitating and simplifying the process.
In addition, since the selected sub-capacitors can be connected in parallel to adjust the thickness of the dielectric film and obtain a desired capacitance, there is an advantage in that it is excellent in utility.
As shown in FIG. 3I, a first metal wire is formed in contact with the contact electrode connected to the first capacitor, and a second metal wire is formed on the second to fourth damascene patterns on which the second capacitor is formed. Different signals can be applied.
In this case, the metal wire connected to the second capacitor may be formed on at least one or more damascene patterns of the second to fourth damascene patterns to adjust the capacitor capacity.
As described above, the present invention has been described in detail through specific embodiments, which are intended to specifically describe the present invention, and the semiconductor device and its manufacturing method according to the present invention are not limited thereto. It is apparent that modifications and improvements are possible by those skilled in the art.
The present invention can increase the capacitance by having the maximum surface area in the minimum space in the capacitor of the semiconductor device, and can be formed in a variety of desired capacitor capacity in a certain area, it is possible to elastic design and to maximize the capacitance There is a first effect.
In addition, the present invention has a second effect of accelerating semiconductor device development by drastically increasing the capacity of a capacitor in accordance with the trend of development research of the latest products, such as dynamic random access memory (DRAM), which have a higher integration and a smaller product size. .
The capacitor of the semiconductor device according to the present invention has a third effect that the process can be made simple and simple since it is possible to form the capacitance to the maximum and to form the capacitor at the time of damascene pattern formation.
In addition, since the selected subcapacitors can be connected in parallel to adjust the thickness of the dielectric film and to obtain a desired capacitance, there is a fourth effect having excellent utility.
Claims:
Forming a capacitor lower metal interconnect on the substrate;
Forming an insulating film on the entire surface of the substrate;
Forming a plurality of damascene patterns by forming a via hole and a trench in the insulating layer to expose the lower metal wiring line;
Depositing a barrier metal film on the insulating film on which the damascene pattern is formed;
Forming a dielectric film on the barrier metal film;
Forming a first mask pattern on the dielectric layer;
Etching the dielectric film at the first damascene pattern position using the first mask pattern as an etching mask;
Removing the first mask pattern and forming a second mask pattern on the dielectric layer;
Etching the dielectric layers at the first and second damascene pattern positions using the second mask pattern as an etching mask;
Exposing a dielectric film at a third damascene pattern position to remove the second mask pattern to form a dielectric film having a different thickness within each damascene pattern;
Forming a conductive metal in the damascene pattern in which dielectric layers having different thicknesses are formed;
Planarizing the conductive metal, the dielectric layer, and the barrier metal layer to expose the upper surface of the insulating layer to form a capacitor lower electrode, a dielectric layer pattern, and a capacitor upper electrode in each damascene pattern. Capacitor Manufacturing Method.
The method of claim 10,
As a result of removing the second mask pattern, the dielectric layer pattern at the first damascene pattern position forms a first dielectric layer pattern having a first thickness, and the dielectric layer pattern at the second damascene pattern position has a second thickness. A second dielectric layer pattern is formed, the dielectric layer pattern at the third damascene pattern position forms a third dielectric layer pattern having a third thickness,
The first to third thickness is a capacitor manufacturing method of the semiconductor device, characterized in that the different thickness.
The method of claim 10,
The thickness of the first dielectric layer pattern is the thinnest in the first to third dielectric layer pattern, the thickness of the third dielectric layer pattern is the manufacturing method of the capacitor of the semiconductor device.
The method of claim 10,
The capacitor lower electrode is formed of a multilayer film including TaN or TaN, a multilayer film including TiN or TiN, a multilayer film including WN or WN, or formed of any one of the multilayer films including TaN, TiN, WN or TaN, TiN, WN. A method for manufacturing a capacitor of a semiconductor device, characterized in that.
The method of claim 10,
And the capacitor lower metal line and the capacitor lower electrode are in electrical contact with each other through the damascene pattern.
The method of claim 10,
After forming the capacitor upper electrode, on the insulating film,
And forming a first metal wire connected to the contact electrode to apply a bias to the capacitor lower metal wire, and a second metal wire connected to at least one of the plurality of capacitor upper electrodes. Method for manufacturing a capacitor of the device.
The method of claim 15,
And a capacitor capacity is adjusted according to the number of the capacitor upper electrodes connected to the second metal wires.
The method of claim 10,
Capacitor capacity of the semiconductor device, characterized in that the capacitor capacity is adjusted according to the thickness of the dielectric film pattern having a different thickness formed on each of the plurality of damascene pattern.