DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/28/2025 has been entered.
Status of the Application
Acknowledgement is made of the amendment received on 11/28/2025. Claims 1, 3-6, and 8-23 are pending in this application. Claims 1, 3-4, 6, 9-10, and 17 are amended. Claims 2 and 7 are previously canceled. Claims 18-20 remain withdrawn. Claims 22-23 are new.
Claims 1, 3-6, 8-17, and 21-23 are presented in this Office Action.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 10-12, 15, 17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2016/0254334; hereinafter ‘Yang’).
Regarding claim 1, Yang teaches a thin film transistor (500, FIG. 14, [0096]), comprising:
a reducing pattern (515 and 518; hereinafter ‘RP’) on a substrate (510);
an active layer (520) on the reducing pattern (RP) and is in contact with the reducing pattern (RP);
a gate insulating layer (525) on the active layer (520); and
a gate electrode (530) on the gate insulating layer (525), and at least partially overlapped with the active layer (520),
wherein the active layer (520) includes:
a channel portion (524, [0102]);
a first conductorization portion (522) connected to one side of the channel portion (524); and
a second conductorization portion (526) connected to the other side of the channel portion (524),
a first diffusion portion (a channel-adjacent portion of 520 between 524 and 522, in which impurity concentration gradually decreases toward 524 as a result of thermal diffusion of impurities associated with 515, [0053, 0054, 0056]; hereinafter ‘FD’) between the channel portion (524) and the first conductorization portion (522); and
a second diffusion portion (a channel-adjacent portion of 520 between 524 and 526, in which impurity concentration gradually decreases toward 524 as a result of thermal diffusion of impurities associated with 518; hereinafter ‘SD’) between the channel portion (524) and the second conductorization portion (526),
wherein the channel portion (524) overlaps the gate electrode (530), and
wherein the reducing pattern (RP) is disposed between the substrate (510) and the active layer (520).
Yang does not explicitly teach the thin film transistor wherein the first diffusion portion and the second diffusion portion do not overlap the reducing pattern and do not contact the reducing pattern, and wherein the channel portion does not contact the reducing pattern, and does not overlap the reducing pattern.
Yang, however, discloses an alternative embodiment of the thin film transistor (300, FIG. 8, [0076]) wherein the first diffusion portion (a channel-adjacent portion of 330 between 334 and 332; hereinafter ‘FD2’) and the second diffusion portion (a channel-adjacent portion of 330 between 334 and 336; hereinafter ‘SD2’) do not overlap the reducing pattern (325 and 328; hereinafter ‘RP2’) and do not contact the reducing pattern (shown in FIG. 8), and wherein the channel portion (334) does not contact the reducing pattern (RP2), and does not overlap the reducing pattern (shown in FIG. 8).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Yang to obtain and achieve the thin film transistor wherein the first diffusion portion and the second diffusion portion do not overlap the reducing pattern and do not contact the reducing pattern, and wherein the channel portion does not contact the reducing pattern, and does not overlap the reducing pattern as claimed, because the diffusion portions are formed by thermal diffusion of impurities from the reducing patterns, and adjusting thermal treatment conditions, such as annealing temperature and duration, predictably changes the diffusion length and lateral extent of the diffused regions [0053, 0056].
Regarding claim 3, Yang teaches the thin film transistor of claim 1, wherein the reducing pattern is in contact with at least one of the first conductorization portion (RP is in contact with 522, FIG. 14) and the second conductorization portion (526).
Regarding claim 4, Yang teaches the thin film transistor of claim 1, wherein the reducing pattern includes;
a first reducing pattern (515, FIG. 14, [0096]) that is in contact with the first conductorization portion (522) and
a second reducing pattern (518) that is in contact with the second conductorization portion (526).
Regarding claim 5, Yang teaches the thin film transistor of claim 1, wherein the reducing pattern (RP2, FIG. 8) does not overlap the gate electrode (315, FIG. 8, [0084]).
Although, Yang discloses a bottom-gate electrode rather that a top-gate electrode, Yang also teaches alternative embodiments in which the gate electrode may be disposed above or below the active layer, indicating that the gate configuration is optional and does not alter the underlying diffusion-based formation of the source/drain regions from the reducing patterns [0020, 0053].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Yang to obtain and achieve the thin film transistor wherein the reducing pattern does not overlap the gate electrode as claimed, because it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 and it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 6, Yang teaches the thin film transistor of claim 1, wherein the reducing pattern includes at least one of a silicon nitride, a silicon oxynitride, a silicon oxide, a silicon hydrogen oxide, aluminum (Al), titanium (Ti), molybdenum (Mo), calcium (Ca) or barium (Ba) (RP includes silicon hydroxide, silicon nitride, silicon oxynitride, [0052]).
Regarding claim 10, Yang teaches the thin film transistor of claim 1, wherein the gate insulating layer (525, FIG. 14) covers the channel portion (524), the first diffusion portion (FD), the second diffusion portion (SD), the first conductorization portion (522), and the second conductorization portion (526).
Regarding claim 11, Yang teaches the thin film transistor of claim 1, wherein the active layer (520, FIG. 14) includes an oxide semiconductor material (520 includes oxide semiconductor material, [0054]).
Regarding claim 12, Yang teaches the thin film transistor of claim 11, wherein the oxide semiconductor material includes at least one of an IZO(InZnO)-based, IGO(InGaO)-based, ITO(InSnO)-based, IGZO(InGaZnO)-based, IGZTO(InGaZnSnO)-based, GZTO(GaZnSnO)-based, GZO(GaZnO)-based, ITZO(InSnZnO)-based, or FIZO(FeInZnO)-based oxide semiconductor material (oxide semiconductor material includes at least one of In, Zn, Ga, Sn, [0054]).
Regarding claim 15, Yang teaches the thin film transistor of claim 1, further comprising:
a source electrode (540, FIG. 14, [0096]) electrically connected to the active layer (520); and
a drain electrode (545) spaced apart from the source electrode (shown in FIG. 14) and electrically connected to the active layer (520).
Regarding claim 17, Yang teaches the thin film transistor of claim 15,
wherein the source electrode (540, FIG. 14) contacts the first conductorization portion (522, [0102]) through a contact hole (a contact hole, [0074]), and
the drain electrode (545) contacts the second conductorization portion (526) through another contact hole (another contact hole, shown in FIG. 14).
Regarding claim 21, Yang teaches a display device (500, FIG. 14, [0096]) comprising the thin film transistor of claim 1 (shown in FIG. 14).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2016/0254334) in view of Ji et al. (US 2021/0313470; hereinafter ‘Ji’).
Regarding claim 8, Yang teaches the thin film transistor of claim 1, but does not teach the thin film transistor wherein the first diffusion portion and the second diffusion portion do not overlap the gate electrode.
Ji teaches a thin film transistor (FIG. 2, [0036]) wherein the first diffusion portion (SA of 110b, [0047]) and the second diffusion portion (SA of 110c, [0047]) do not overlap the gate electrode (SA does not overlap 130, [0051]).
As taught by Ji, one of ordinary skill in the art would utilize and modify the above teaching into Yang to obtain and achieve the thin film transistor wherein the first diffusion portion and the second diffusion portion do not overlap the gate electrode as claimed, because generation of the parasitic capacitance between the gate electrode and the diffusion portion is minimized by preventing their overlap, which contributes to improved device performance and high-speed operation [0051].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ji in combination with Yang due to above reason.
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2016/0254334) in view of Yang et al. (KR 2021/0035694; hereinafter ‘Yang694’).
Regarding claim 9, Yang teaches the thin film transistor of claim 1, but does not teach the thin film transistor wherein the first diffusion portion has a specific resistance smaller than a resistance of the channel portion and greater than a resistance of the first conductorization portion, and the second diffusion portion has a specific resistance smaller than the resistance of the channel portion and greater than a resistance of the second conductorization portion.
Yang694 teaches a thin film transistor (100, FIG. 1, [0036]) wherein the first diffusion portion (132a, [0037]) has a specific resistance smaller than a resistance of the channel portion and greater than a resistance of the first conductorization portion (the resistivity of 132a is lower than 131and higher than 133a, [0058]), and the second diffusion portion (132b, [0037]) has a specific resistance smaller than the resistance of the channel portion and greater than a resistance of the second conductorization portion (the resistivity of 132b is lower than 131and higher than 133b, [0058]).
As taught by Yang694, one of ordinary skill in the art would utilize and modify the above teaching into Yang to obtain and achieve the thin film transistor wherein the first diffusion portion has a specific resistance smaller than a resistance of the channel portion and greater than a resistance of the first conductorization portion, and the second diffusion portion has a specific resistance smaller than the resistance of the channel portion and greater than a resistance of the second conductorization portion as claimed, because during dopant implantation process into the conductorization portions, some dopants inevitably diffuse into the adjacent diffusion portions. As a result, the diffusion portions become partially doped, acquiring an intermediate specific resistance between the undoped channel and the heavily doped conductorization portions [0058-0059].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yang694 in combination with Yang due to above reason.
Regarding claim 16, Yang teaches the thin film transistor of claim 15, but does not teach the thin film transistor wherein the source electrode and the drain electrode are disposed on a same layer as the gate electrode.
Yang694 teaches a thin film transistor (500, FIG. 5, [0095]) wherein the source electrode (161) and the drain electrode (162) are disposed on a same layer as the gate electrode (161, 162 are disposed on the same layer as 140).
As taught by Yang694, one of ordinary skill in the art would utilize and modify the above teaching into Yang to obtain and achieve the thin film transistor wherein the source electrode and the drain electrode are disposed on a same layer as the gate electrode as claimed, because forming the conductive features on the same layer simplifies the manufacturing process reduces step differences, which minimizes metal residual and reduces the risk of shorts or device failure [0215, 0218].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yang694 in combination with Yang due to above reason.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2016/0254334) in view of Tanaka (US 2020/0098933).
Regarding claim 13, Yang teaches the thin film transistor of claim 1, but does not teach the thin film transistor wherein the active layer includes: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer.
Tanaka teaches a thin film transistor (100b, FIG. 30B, [0221]) wherein the active layer includes: a first oxide semiconductor layer (112-1); and a second oxide semiconductor layer on the first oxide semiconductor layer (112-2 on 112-1).
As taught by Tanaka, one of ordinary skill in the art would utilize and modify the above teaching into Yang to obtain and achieve the thin film transistor wherein the active layer includes: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer as claimed, because the multilayer structure of the active layer prevents deterioration caused by defects originating from the low-quality surface formed during the final stage of semiconductor deposition, thereby improving field-effect mobility, suppressing threshold voltage fluctuation, and enhancing the reliability of the transistor [0136-0137].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Tanaka in combination with Yang due to above reason.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2016/0254334) in view of Tanaka (US 2020/0098933), further in view of Matsubayashi et al. (US 2016/0141422; hereinafter ‘Matsubayashi’).
Regarding claim 14, Yang in view of Tanaka teaches the thin film transistor of claim 13, but does not each the thin film transistor wherein the active layer further includes a third oxide semiconductor layer on the second oxide semiconductor layer.
Matsubayashi teaches a thin film transistor wherein the active layer further includes a third oxide semiconductor layer on the second oxide semiconductor layer.
As taught by Matsubayashi, one of ordinary skill in the art would utilize and modify the above teaching into Yang in view of Tanaka to obtain and achieve the thin film transistor wherein the active layer further includes a third oxide semiconductor layer on the second oxide semiconductor layer as claimed, because a multi-layer oxide semiconductor structure provides a synergistic effects by incorporating multiple layers with different functions, ultimately resulting in improved field-effect mobility, threshold voltage stability, and reduced leakage current, compared to a single-layer structure [0103, 0145].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Matsubayashi in combination with Yang in view of Tanaka due to above reason.
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2016/0254334) in view of Ito et al. (US 2015/0053969; hereinafter ‘Ito’).
Regarding claim 22, Yang teaches the thin film transistor of claim 1, but does not teach the thin film transistor wherein the active layer covers an entire upper surface of the reducing pattern in a cross-section view.
Ito teaches a thin film transistor (C4, FIG. 28, [0230]) wherein the active layer (50, [0061]) covers an entire upper surface of the reducing pattern (the upper surface of 8r, [0229]) in a cross-section view (shown in FIG. 28).
As taught by Ito, one of ordinary skill in the art would utilize and modify the above teaching into Yang to obtain and achieve the thin film transistor wherein the active layer covers an entire upper surface of the reducing pattern in a cross-section view as claimed, because the resistance-lowering effect of the reducing layer is contact-dependent, the reducing layer is disposed to cover and contact the conductor region over a sufficient area to achieve uniform conductorization [0186, 0192].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ito in combination with Yang due to above reason.
Regarding claim 23, Yang teaches the thin film transistor of claim 1, but does not teach the thin film transistor wherein the gate insulating layer is disposed over an upper surface of the reducing pattern without contacting the upper surface of the reducing pattern in a cross-sectional view.
Ito teaches a thin film transistor (C4, FIG. 28, [0230]) wherein the gate insulating layer (8b, [0231]) is disposed over an upper surface of the reducing pattern (the upper surface of 8r, [0229]) without contacting the upper surface of the reducing pattern in a cross-sectional view (shown in FIG. 28).
As taught by Ito, one of ordinary skill in the art would utilize and modify the above teaching into Yang to obtain and achieve the thin film transistor wherein the gate insulating layer is disposed over an upper surface of the reducing pattern without contacting the upper surface of the reducing pattern in a cross-sectional view as claimed, because the resistance-lowering effect of the reducing layer is contact-dependent, the reducing layer is disposed to cover and contact the conductor region over a sufficient area to achieve uniform conductorization [0186, 0192].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ito in combination with Yang due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Claim 1 is amended with newly added features, alternative interpretations and rejections are also changed to meet the current amended claims and their dependency. See detail discussed above.
Applicant submits, page 11, “Yang does not disclose that the "active layer 120" (in FIG. 1) or the "active layer 330" (in FIG. 8) has any "diffusion portion," as recited in claim 1. It is telling that FIGs. 1 and 8 of Yang do not identify or illustrate any such "diffusion portion" (or "transition region formed by impurity diffusion" as alleged by the Office).”
The examiner respectfully disagrees.
Yang does not need to explicitly label a “diffusion portion” in the drawings to disclose such a region. Rather, yang expressly teaches forming the source and drain regions by diffusing impurities from the insulation layer patterns into the active layer via thermal treatment (e.g., annealing), i.e., a diffusion-based formation mechanism. See, e.g., Yang [0013, 0025-0026, 0053, 0079-0081, 0090]. Where the source/drain regions are formed by impurity diffusion into the active layer, a channel-adjacent transition region between the channel region and the diffused source/drain regions is inherently present as a predictable result of diffusion, even if not expressly delineated by reference numeral in the figures. Accordingly, the Office’s identification of channel-adjacent “transition regions formed by impurity diffusion” is a reasonable interpretation of Yang’s express diffusion-based teachings, rather than an impermissible addition of a new, non-disclosed structural element.
Further, the Office’s analysis does not improperly combine embodiments, as the diffusion-based formation mechanism and the resulting channel-adjacent diffusion regions are consistently taught across Yang’s embodiments.
Conclusion
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/JIYOUNG OH/Examiner, Art Unit 2818
/EVA Y MONTALVO/Supervisory Patent Examiner, Art Unit 2818