DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 10/11/2022 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Objections
Claim(s) 11 is objected to because of the following informalities: “the first level of interconnect wiring” should be replaced with “the bottom level of interconnect wiring."
Claim(s) 20 is objected to because of the following informalities: “a contact area between the sidewall…” should be replaced with “the contact area between the sidewall…”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6, 7, 14 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 6 recites “wherein a contact area… defines a substantially vertical contact area.” The term “substantially” is unclear as it is unclear how vertical the contact area would have to be to meet the limitation “substantially vertical.” The specification (see figure 2m for example) does not define or show “substantially vertical.” For examination purposes, the examiner has interpreted the claim as a “vertical contact area,” which is consistent with Figure 2 of applicant’s specification.
Claims 7 and 14 recite “a skip via contact resistance of ~2Ω.” This phrase is unclear as it is unclear what contact resistance would be sufficient to meet this claim limitation. The specification at paragraph [0059] states that ~2Ω is an estimated resistance, but does not provide a range or other definition of what would be sufficient to meet ~2Ω. Thus, for examination purposes, the examiner has interpreted ~2Ω to be 2Ω.
Claim 20 recites “wherein a contact area… defines a substantially vertical contact area.” The term “substantially” is unclear as it is unclear how vertical the contact area would have to be to meet the limitation “substantially vertical.” The specification (see figure 2 for example) does not define or show “substantially vertical.” For examination purposes, the examiner has interpreted the claim as a “vertical contact area,” which is consistent with Figure 2 of applicant’s specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min-Shiang Hsu et al, (hereinafter HSU), US 20220216144 A1, in view of SunOo Kim et al, (hereinafter KIM), US 20120104622 A1, and further in view of Shu-Cheng Chin, (hereinafter CHIN), US 20220246535 A1.
Regarding Claim 1, HSU teaches in Figure 10, a semiconductor structure (Fig. 10, semiconductor structure, [0008]) comprising:
a first level of interconnect wiring (Fig. 10, M1, first inter-metal dielectric layer, [0006]);
a second level of interconnect wiring (Fig. 10, M2, second inter-metal dielectric layer, [0006]) disposed above the first level of interconnect wiring;
a third level of interconnect wiring (Fig. 10, M3, third inter-metal dielectric layer, [0006]) disposed above the second level of interconnect wiring; and
a skip via (Fig. 10, 132, super via, [0024]) extending from the third level of interconnect wiring (Fig. 10, M3, third inter-metal dielectric layer, [0006]) to the first level of interconnect wiring (Fig. 10, M1, first inter-metal dielectric layer, [0006]).
HSU does not explicitly disclose a semiconductor structure comprising: a skip via extending from the third level of interconnect wiring to the first level of interconnect wiring, such that a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring.
KIM teaches in Figure 1b, a semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]) comprising:
a skip via (Fig. 1b, 130, through level via, [0037]) extending from the third level of interconnect wiring (Fig. 1b, Mn+1, metallization layers with metal level, [0030]) to the first level of interconnect wiring (Fig. 1b, Mn-1, metallization layers with metal level, [0030]), such that a sidewall (Fig. 1b, 180, metal liner, [0037]) of the skip via (Fig. 1b, 130, through level via, [0037]) maintains electrical contact with the second level of interconnect wiring (Fig. 1b, the metallization layers (Fig. 1b, Mn-1, Mn, Mn+1, [0030]), electrically contact and interconnect (Fig. 1b, metal lines, 30, 60, 110, [0031], [0036]) the active devices, [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HSU to incorporate the teachings of KIM such that a semiconductor structure comprising: a skip via extending from the third level of interconnect wiring to the first level of interconnect wiring, such that a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring. The metal liner (180) as a sidewall of the through level via (130) with a fill metal (190) thus form the third metal lines (110) electrically connecting the third metal lines (110) with the first metal lines (30) and further in contact with the second metal lines (60), so that the metallization layers and active device regions together form a complete functional integrated circuit or in other words, the electrical functions of the chip can be performed by the interconnected active circuitry (KIM, [0029], [0068]).
Though KIM teaches the semiconductor structure, wherein the metallization layers, electrically contact and interconnect the active devices, HSU as modified by KIM does not explicitly disclose a semiconductor structure comprising: a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring.
CHIN teaches in Figure 7, a semiconductor structure (Fig. 7, 700, dual damascene structure) comprising: a sidewall (Fig. 7, 712, sidewall including 720/722, ruthenium oxide film/ruthenium liner, [0075]) of the skip via (Fig. 7, 704, via, [0073]) maintains electrical contact (ruthenium (Ru) or a combination of ruthenium and ruthenium oxide (RuOx) as the sidewall in the formation of BEOL metallization layers and vias increase electrical performance of the electronic device, [0016]) with the second level of interconnect wiring (Fig. 7, 710, dielectric layer, [0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HSU as modified by KIM to incorporate the teachings of CHIN such that a semiconductor structure, a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring. The ruthenium layer (722) as the sidewall (712) enables achieve a low contact resistance and a low sheet resistance for the BEOL metallization layers and vias, to promote adhesion between the various layers and materials in the BEOL metallization layers and vias, and/or to reduce or eliminate defects (such as voids and discontinuities) in the BEOL metallization layers and vias. This may increase the electrical performance of the electronic device and may increase manufacturing yield (CHIN, [0116]).
Regarding Claim 2, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 1.
HSU further teaches in Figure 10, the semiconductor structure (Fig. 10, semiconductor structure, [0008]), wherein the skip via (Fig. 10, 132, super via, [0024]) electrically connects the first (Fig. 10, M1, first inter-metal dielectric layer, [0006]), second (Fig. 10, M2, second inter-metal dielectric layer, [0006]), and third (Fig. 10, M3, third inter-metal dielectric layer, [0006]) levels of interconnect wiring ([0028]).
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein the skip via (Fig. 1b, 130, through level via, [0037]) electrically connects the first (Fig. 1b, Mn-1, metallization layers with metal level, [0030]), second (Fig. 1b, Mn, metallization layers with metal level, [0030]), and third (Fig. 1b, Mn+1, metallization layers with metal level, [0030]) levels of interconnect wiring (Fig. 1b, the metallization layers (Fig. 1b, Mn-1, Mn, Mn+1, [0030]), electrically contact and interconnect (Fig. 1b, metal lines, 30, 60, 110, [0031], [0036]) the active devices, [0029]).
Regarding Claim 3, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 1.
HSU further teaches in Figure 10, the semiconductor structure (Fig. 10, semiconductor structure, [0008]), wherein the skip via (Fig. 10, 132, super via, [0024]) extends entirely through (Fig. 10, 132 within the M2 and M3 layers) the second level of interconnect wiring (Fig. 10, M2, second inter-metal dielectric layer, [0006]).
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein the skip via (Fig. 1b, 130, through level via, [0037]) extends entirely through (Fig. 1b, the through level via 130 passes through at least one metal level, such as Mn, while directly connecting two metal levels such as Mn+1 and Mn−1. [0037]) the second level of interconnect wiring (Fig. 1b, Mn, metallization layers with metal level, [0030]).
Regarding Claim 4, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 1.
CHIN further teaches in Figure 7, the semiconductor structure (Fig. 7, 700, dual damascene structure), wherein a contact area (labeled as CA1 in the annotated Figure 7) between the sidewall (Fig. 7, 712, sidewall including 720/722, ruthenium oxide film/ruthenium liner, [0075]) of the skip via (Fig. 7, 704, via, [0073]) and the second level of interconnect wiring (Fig. 7, 710, dielectric layer, [0073]) is greater than a contact area (labeled as CA2 in the annotated Figure 7) between a bottom portion (Fig. 7, 718, the bottom surface, [0074]) of the skip via (Fig. 7, 704, via, [0073]) and a top portion (annotated Figure 7) of the first level of interconnect wiring (Fig. 7, 706, lower metallization layer, [0073]).
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Regarding Claim 5, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 1.
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein the electrical contact (annotated Figure 1b) between the skip via (Fig. 1b, 130, through level via, including metal liner, 180, [0037]) and the second level of interconnect wiring (Fig. 1b, Mn, metallization layers with metal level, [0030]) defines a lateral line connection (annotated Figure 1b).
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Regarding Claim 6, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 1.
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein a contact area (CA1 as annotated in Figure 1b) between the sidewall (Fig. 1b, 180, metal liner) of the skip via (Fig. 1b, 130, through level via, including metal liner, 180, [0037]) and the second level of interconnect wiring (Fig. 1b, Mn, metallization layers with metal level, [0030]) defines a substantially vertical contact area (CA1 as annotated in Figure 1b).
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CHIN further teaches in Figure 7, the semiconductor structure (Fig. 7, 700, dual damascene structure), wherein a contact area (CA1 as annotated in Figure 1b) between the sidewall (Fig. 7, 712, sidewall including 720/722, ruthenium oxide film/ruthenium liner, [0075]) of the skip via (Fig. 7, 704, via, [0073]; ) and the second level of interconnect wiring (Fig. 7, 710, dielectric layer, [0073]) defines a substantially vertical contact area (CA1 as annotated in Figure 1b).
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Regarding Claim 7, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 6.
CHIN further teaches in Figure 7, the semiconductor structure (Fig. 7, 700, dual damascene structure), wherein the vertical contact area (annotated Figure 1B) results in a skip via (Fig. 7, 704, via, [0073]; including 720/722, ruthenium oxide film/ruthenium liner, [0075]) contact resistance of ~-2Ω (Figs. 3/7, the overall contact resistance of the via 304/704 remains relatively low, as the contact resistance of ruthenium is lower than other copper diffusion barrier layers such as tantalum nitride (TaN), [0039]; since the contact resistance of ~2Ω is an estimated number per the specification [0059] and there are no other information provided by the Applicant, the contact resistance of ~-2Ω as claimed is treated as relatively low and supported by CHIN art, of Ru liner contact resistance as mentioned above).
Regarding Claim 8, HSU teaches in Figure 10, a semiconductor structure (Fig. 10, semiconductor structure, [0008]) comprising:
a bottom level of interconnect wiring (Fig. 10, M1, first inter-metal dielectric layer, [0006]);
a plurality of middle levels of interconnect wiring (Fig. 10, M2, second inter-metal dielectric layer, [0006]) disposed above the bottom level of interconnect wiring;
a top level of interconnect wiring (Fig. 10, M3, third inter-metal dielectric layer, [0006]) disposed above the plurality of middle levels of interconnect wiring; and
a skip via extending (Fig. 10, 132, super via, [0024]) from the top level of interconnect wiring Fig. 10, (M3, third inter-metal dielectric layer, [0006]) to the bottom level of interconnect wiring (Fig. 10, M1, first inter-metal dielectric layer, [0006]).
HSU does not explicitly disclose a semiconductor structure comprising: a skip via extending from the top level of interconnect wiring to the bottom level of interconnect wiring, such that a sidewall of the skip via maintains electrical contact with all of the plurality of middle levels of interconnect wiring.
KIM teaches in Figure 1b, a semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]) comprising:
a skip via extending (Fig. 1b, 130, through level via, [0037]) from the top level of interconnect wiring (Fig. 1b, Mn+1, metallization layers with metal level, [0030]) to the bottom level of interconnect wiring (Fig. 1b, Mn-1, metallization layers with metal level, [0030]), such that a sidewall (Fig. 1b, 180, metal liner, [0037]) of the skip via (Fig. 1b, 130, through level via, [0037]) maintains electrical contact with all of the plurality of middle levels of interconnect wiring (Fig. 1b, the metallization layers (Fig. 1b, Mn-1, Mn, Mn+1, [0030]), electrically contact and interconnect (Fig. 1b, metal lines, 30, 60, 110, [0031], [0036]) the active devices, [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HSU to incorporate the teachings of KIM such that a semiconductor structure comprising: a skip via extending from the top level of interconnect wiring to the bottom level of interconnect wiring, such that a sidewall of the skip via maintains electrical contact with all of the plurality of middle levels of interconnect wiring. The metal liner (180) as a sidewall of the through level via (130) with a fill metal (190) thus form the third metal lines (110) electrically connecting the third metal lines (110) with the first metal lines (30) and further in contact with the second metal lines (60), so that the metallization layers and active device regions together form a complete functional integrated circuit or in other words, the electrical functions of the chip can be performed by the interconnected active circuitry (KIM, [0029], [0068]).
Though KIM teaches the semiconductor structure, wherein the metallization layers, electrically contact and interconnect the active devices, HSU as modified by KIM does not explicitly disclose a semiconductor structure comprising: a sidewall of the skip via maintains electrical contact with all of the plurality of middle levels of interconnect wiring.
CHIN teaches in Figure 7, a semiconductor structure (Fig. 7, 700, dual damascene structure) comprising: a sidewall (Fig. 7, 712, sidewall including 720/722, ruthenium oxide film/ruthenium liner, [0075]) of the skip via (Fig. 7, 704, via, [0073]) maintains electrical contact (ruthenium (Ru) or a combination of ruthenium and ruthenium oxide (RuOx) as the sidewall in the formation of BEOL metallization layers and vias increase electrical performance of the electronic device, [0016]) with the second level of interconnect wiring (Fig. 7, 710, dielectric layer, [0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HSU as modified by KIM to incorporate the teachings of CHIN such that a semiconductor structure, a sidewall of the skip via maintains electrical contact with all of the plurality of middle levels of interconnect wiring. The ruthenium layer (722) as the sidewall (712) enables achieve a low contact resistance and a low sheet resistance for the BEOL metallization layers and vias, to promote adhesion between the various layers and materials in the BEOL metallization layers and vias, and/or to reduce or eliminate defects (such as voids and discontinuities) in the BEOL metallization layers and vias. This may increase the electrical performance of the electronic device and may increase manufacturing yield (CHIN, [0116]).
Regarding Claim 9, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 8.
HSU further teaches in Figure 10, the semiconductor structure (Fig. 10, semiconductor structure, [0008]), wherein the skip via (Fig. 10, 132, super via, [0024]) electrically connects the bottom (Fig. 10, M1, first inter-metal dielectric layer, [0006]), the top (Fig. 10, M3, third inter-metal dielectric layer, [0006]), and the middle (Fig. 10, M2, second inter-metal dielectric layer, [0006]) levels of interconnect wiring ([0028]).
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein the skip via (Fig. 1b, 130, through level via, [0037]) electrically connects the bottom (Fig. 1b, Mn-1, metallization layers with metal level, [0030]), the top (Fig. 1b, Mn+1, metallization layers with metal level, [0030]), and the middle (Fig. 1b, Mn, metallization layers with metal level, [0030]) levels of interconnect wiring (Fig. 1b, the metallization layers (Fig. 1b, Mn-1, Mn, Mn+1, [0030]), electrically contact and interconnect (Fig. 1b, metal lines, 30, 60, 110, [0031], [0036]) the active devices, [0029]).
Regarding Claim 10, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 8.
HSU further teaches in Figure 10, the semiconductor structure (Fig. 10, semiconductor structure, [0008]), wherein the skip via (Fig. 10, 132, super via, [0024]) extends entirely through (Fig. 10, 132 within the M2 and M3 layers) all of the plurality of middle level of interconnect wiring (Fig. 10, M2, second inter-metal dielectric layer, [0006]).
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein the skip via (Fig. 1b, 130, through level via, [0037]) extends entirely through (Fig. 1b, the through level via 130 passes through at least one metal level, such as Mn, while directly connecting two metal levels such as Mn+1 and Mn−1. [0037]) all of the plurality of middle level of interconnect wiring (Fig. 1b, Mn, metallization layers with metal level, [0030]).
Regarding Claim 11, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim.
CHIN further teaches in Figure 7, the semiconductor structure (Fig. 7, 700, dual damascene structure), wherein a contact area (labeled as CA1 in the annotated Figure 7) between the sidewall (Fig. 7, 712, sidewall including 720/722, ruthenium oxide film/ruthenium liner, [0075]) of the skip via (Fig. 7, 704, via, [0073]) and a middle level of the plurality of middle level of interconnect wiring (Fig. 7, 710, dielectric layer, [0073]) is greater than a contact area (labeled as CA2 in the annotated Figure 7) between a bottom portion (Fig. 7, 718, the bottom surface, [0074]) of the skip via (Fig. 7, 704, via, [0073]) and a top portion (annotated Figure 7) of the first level of interconnect wiring (Fig. 7, 706, lower metallization layer, [0073]).
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Regarding Claim 12, teaches the semiconductor structure of claim 8.
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein the electrical contact (annotated Figure 1b) between the skip via (Fig. 1b, 130, through level via, including metal liner, 180, [0037]) and each of the plurality of middle level of interconnect wiring (Fig. 1b, Mn, metallization layers with metal level, [0030]) defines a lateral line connection (annotated Figure 1b).
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Regarding Claim 13, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 8.
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein a contact area (CA1 as annotated in Figure 1b) between the sidewall (Fig. 1b, 180, metal liner) of the skip via (Fig. 1b, 130, through level via, including metal liner, 180, [0037]) and a middle level of the plurality of middle level of interconnect wiring (Fig. 1b, Mn, metallization layers with metal level, [0030]) defines a substantially vertical contact area (CA1 as annotated in Figure 1b).
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CHIN further teaches in Figure 7, the semiconductor structure (Fig. 7, 700, dual damascene structure), wherein a contact area (CA1 as annotated in Figure 1b) between the sidewall (Fig. 7, 712, sidewall including 720/722, ruthenium oxide film/ruthenium liner, [0075]) of the skip via (Fig. 7, 704, via, [0073]; ) and a middle level of the plurality of level of interconnect wiring (Fig. 7, 710, dielectric layer, [0073]) defines a substantially vertical contact area (CA1 as annotated in Figure 1b).
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Regarding Claim 14, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 13.
CHIN further teaches in Figure 7, the semiconductor structure (Fig. 7, 700, dual damascene structure), wherein the vertical contact area (annotated Figure 1B) results in a skip via (Fig. 7, 704, via, [0073]; including 720/722, ruthenium oxide film/ruthenium liner, [0075]) contact resistance of ~-2Ω (Figs. 3/7, the overall contact resistance of the via 304/704 remains relatively low, as the contact resistance of ruthenium is lower than other copper diffusion barrier layers such as tantalum nitride (TaN), [0039]; since the contact resistance of ~2Ω is an estimated number per the specification [0059] and there are no other information provided in the instant application, the contact resistance of ~-2Ω as claimed is treated as relatively low and supported by CHIN art, of Ru liner contact resistance as mentioned above).
Regarding Claim 15, HSU teaches in Figures 1-11, a method (Figs. 1-11, a method of manufacturing a semiconductor structure with a super via, [0006]) comprising:
forming a first level of interconnect wiring (Fig. 10, M1, first inter-metal dielectric layer, [0006]);
forming a second level of interconnect wiring (Fig. 10, M2, second inter-metal dielectric layer, [0006]) disposed above the first level of interconnect wiring;
forming a third level of interconnect wiring (Fig. 10, M3, third inter-metal dielectric layer, [0006]) disposed above the second level of interconnect wiring; and
forming a skip via (Fig. 10, 132, super via, [0024]) extending from the third level of interconnect wiring (Fig. 10, M3, third inter-metal dielectric layer, [0006]) to the first level of interconnect wiring (Fig. 10, M1, first inter-metal dielectric layer, [0006]).
HSU does not explicitly disclose a method comprising: forming a skip via extending from the third level of interconnect wiring to the first level of interconnect wiring, such that a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring.
KIM teaches (Figures 3a-3f), a method (Figs. 3a-3f, method of fabrication of a through level via, [0044]) comprising:
forming a skip via (Fig. 1b, 130, through level via, [0037]) extending from the third level of interconnect wiring (Fig. 1b, Mn+1, metallization layers with metal level, [0030]) to the first level of interconnect wiring (Fig. 1b, Mn-1, metallization layers with metal level, [0030]), such that a sidewall (Fig. 1b, 180, metal liner, [0037]) of the skip via (Fig. 1b, 130, through level via, [0037]) maintains electrical contact with the second level of interconnect wiring (Fig. 1b, the metallization layers (Fig. 1b, Mn-1, Mn, Mn+1, [0030]), electrically contact and interconnect (Fig. 1b, metal lines, 30, 60, 110, [0031], [0036]) the active devices, [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HSU to incorporate the teachings of KIM such that a method comprising: forming a skip via extending from the third level of interconnect wiring to the first level of interconnect wiring, such that a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring. The metal liner (180) as a sidewall of the through level via (130) with a fill metal (190) thus form the third metal lines (110) electrically connecting the third metal lines (110) with the first metal lines (30) and further in contact with the second metal lines (60), so that the metallization layers and active device regions together form a complete functional integrated circuit or in other words, the electrical functions of the chip can be performed by the interconnected active circuitry (KIM, [0029], [0068]).
Though KIM teaches the semiconductor structure, wherein the metallization layers, electrically contact and interconnect the active devices, HSU as modified by KIM does not explicitly disclose a semiconductor structure comprising: a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring.
CHIN teaches in Figure 7, a semiconductor structure (Fig. 7, 700, dual damascene structure) comprising: a sidewall (Fig. 7, 712, sidewall including 720/722, ruthenium oxide film/ruthenium liner, [0075]) of the skip via (Fig. 7, 704, via, [0073]) maintains electrical contact (ruthenium (Ru) or a combination of ruthenium and ruthenium oxide (RuOx) as the sidewall in the formation of BEOL metallization layers and vias increase electrical performance of the electronic device, [0016]) with the second level of interconnect wiring (Fig. 7, 710, dielectric layer, [0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HSU as modified by KIM to incorporate the teachings of CHIN such that a semiconductor structure, a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring. The ruthenium layer (722) as the sidewall (712) enables achieve a low contact resistance and a low sheet resistance for the BEOL metallization layers and vias, to promote adhesion between the various layers and materials in the BEOL metallization layers and vias, and/or to reduce or eliminate defects (such as voids and discontinuities) in the BEOL metallization layers and vias. This may increase the electrical performance of the electronic device and may increase manufacturing yield (CHIN, [0116]).
Regarding Claim 16, HSU as modified by KIM and CHIN teaches the method (Figs. 1-11, a method of manufacturing a semiconductor structure with a super via, [0006]) of claim 15.
HSU further teaches in Figure 10, the semiconductor structure (Fig. 10, semiconductor structure, [0008]), wherein the skip via (Fig. 10, 132, super via, [0024]) electrically connects the first (Fig. 10, M1, first inter-metal dielectric layer, [0006]), second (Fig. 10, M2, second inter-metal dielectric layer, [0006]), and third (Fig. 10, M3, third inter-metal dielectric layer, [0006]) levels of interconnect wiring ([0028]).
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein the skip via (Fig. 1b, 130, through level via, [0037]) electrically connects the first (Fig. 1b, Mn-1, metallization layers with metal level, [0030]), second (Fig. 1b, Mn, metallization layers with metal level, [0030]), and third (Fig. 1b, Mn+1, metallization layers with metal level, [0030]) levels of interconnect wiring (Fig. 1b, the metallization layers (Fig. 1b, Mn-1, Mn, Mn+1, [0030]), electrically contact and interconnect (Fig. 1b, metal lines, 30, 60, 110, [0031], [0036]) the active devices, [0029]).
Regarding Claim 17, HSU as modified by KIM and CHIN teaches the method (Figs. 1-11, a method of manufacturing a semiconductor structure with a super via, [0006]) of claim 15.
HSU further teaches in Figure 10, the semiconductor structure (Fig. 10, semiconductor structure, [0008]), wherein the skip via (Fig. 10, 132, super via, [0024]) extends entirely through (Fig. 10, 132 within the M2 and M3 layers) the second level of interconnect wiring (Fig. 10, M2, second inter-metal dielectric layer, [0006]).
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein the skip via (Fig. 1b, 130, through level via, [0037]) extends entirely through (Fig. 1b, the through level via 130 passes through at least one metal level, such as Mn, while directly connecting two metal levels such as Mn+1 and Mn−1. [0037]) the second level of interconnect wiring (Fig. 1b, Mn, metallization layers with metal level, [0030]).
Regarding Claim 18, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 1.
CHIN further teaches in Figure 7, the semiconductor structure (Fig. 7, 700, dual damascene structure), wherein a contact area (labeled as CA1 in the annotated Figure 7) between the sidewall (Fig. 7, 712, sidewall including 720/722, ruthenium oxide film/ruthenium liner, [0075]) of the skip via (Fig. 7, 704, via, [0073]) and the second level of interconnect wiring (Fig. 7, 710, dielectric layer, [0073]) is greater than a contact area (labeled as CA2 in the annotated Figure 7) between a bottom portion (Fig. 7, 718, the bottom surface, [0074]) of the skip via (Fig. 7, 704, via, [0073]) and a top portion (annotated Figure 7) of the first level of interconnect wiring (Fig. 7, 706, lower metallization layer, [0073]).
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Regarding Claim 19, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 1.
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein the electrical contact (annotated Figure 1b) between the skip via (Fig. 1b, 130, through level via, including metal liner, 180, [0037]) and the second level of interconnect wiring (Fig. 1b, Mn, metallization layers with metal level, [0030]) defines a lateral line connection (annotated Figure 1b).
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930
1162
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Regarding Claim 20, HSU as modified by KIM and CHIN teaches the semiconductor structure of claim 1.
KIM further teaches in Figure 1b, the semiconductor structure (Fig. 1b, 1, semiconductor device, [0028]), wherein a contact area (CA1 as annotated in Figure 1b) between the sidewall (Fig. 1b, 180, metal liner) of the skip via (Fig. 1b, 130, through level via, including metal liner, 180, [0037]) and the second level of interconnect wiring (Fig. 1b, Mn, metallization layers with metal level, [0030]) defines a substantially vertical contact area (CA1 as annotated in Figure 1b).
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1012
1236
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CHIN further teaches in Figure 7, the semiconductor structure (Fig. 7, 700, dual damascene structure), wherein a contact area (CA1 as annotated in Figure 1b) between the sidewall (Fig. 7, 712, sidewall including 720/722, ruthenium oxide film/ruthenium liner, [0075]) of the skip via (Fig. 7, 704, via, [0073]; ) and the second level of interconnect wiring (Fig. 7, 710, dielectric layer, [0073]) defines a substantially vertical contact area (CA1 as annotated in Figure 1b).
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800
1099
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20170117371 A1 – Figure 4; [0055]
Statement of Relevance - The contacts are low resistance contacts. The term low resistance denotes a resistivity for the contacts having an average area of approximately 700 nm2 of 45 micro ohms per cm or less.
US 20210313217 A1 – Figure 1K
Statement of Relevance – Supervia opening formation relative to a metal-containing etch stop layer.
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/SESHA SAIRAMAN SRINIVASAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812