DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR
1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/15/2026 has been entered.
Response to Amendment
The Amendment filed on 03/26/2026 has been entered. Applicant's amendment overcome
to the objections to the Drawings, Specifications and to the Claims previously set forth in the Final Office Action dated on 02/23/2026.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Final Reject" filed on 03/26/2026, have been fully considered, the Applicant’s arguments describe Pagani’s device (US 20180226307 A1), "…is a binary system that tests whether the TSV's are made correctly by applying a current… …There is not teaching or suggestion of applying a voltage to measure a property of the layer, only the quality of the TSV formation. Thus, claim 1, as amended, is neither taught nor suggested by the prior art…". However, the Applicant’s arguments are not persuasive because the Pagani’s device describes a circuit formed by TSVs and a conductive layer 3’, wherein a current 50 applied to node A is detected at the node C, it concluded that the TSVs associated with nodes A and C are properly conducting current flow ([0037], Fig. 7C, Pagani). Due to the TSVs and the conductive layer 3’ form part of the circuit, then, electrical properties of the TSVs and the conductive layer are measured at the same time. In addition, in the specification of the current Application is disclosed “…if an electrical property (at least one of an electrical conduction or an electrical resistance) measured between the first test TSV 134 and the second test TSV 136 through the conductive layer 140 (e.g., doped silicon substrate) is outside a predetermined value range, then the test TSVs 134 and 136 are not formed to a sufficient depth or not properly formed within the substrate 110…”, this indicates that information regarding the electrical properties of the test TSVs is also obtained ([0060,0063]), see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6-12 and 15-16 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lu (US 20230290695 A1, of the record) in view of Pagani (US 20180226307 A1, hereinafter Pagani, of the record).
Re: Independent Claim 1, Lu discloses a test structure (through-substrate via (TSV) test structure in [0002], Fig. 1) configured to facilitate testing (when the TSV 102 is abnormal then it can be known that the TSV 106 in the device region RD is abnormal in [0045], Fig. 1) of the integrity of one or more circuit TSVs (TSVs 106 in [0037], Fig. 1) associated with an integrated circuit (IC) (chip region RC, in [0034], Fig. 2), the circuit TSVs (TSVs 106) being formed at least partially through a substrate (substrate including a dielectric layer 108 and a silicon layer 100 in [0034, 0038], Fig. 1-Annotated) comprising an insulating layer (108 in [0038], Fig. 1) adjacent to a layer (100 made of silicon in [0034], Fig. 1), the test structure device comprising:
PNG
media_image1.png
656
838
media_image1.png
Greyscale
Lu’s Figure 1-Annotated.
a first test TSV (TSV 102 in [0035], Fig. 1) formed partially through the layer (100) of the substrate (substrate);
Lu does not expressly disclose a substrate comprising a conductive layer, a first test TSV formed through the insulating layer and a second test TSV formed through the insulating layer and partially through the conductive layer of the substrate, wherein the first test TSV and the second test TSV comprise test TSVs to the circuit TSVs; and wherein the test TSVs are formed such that an electrical test meter can contact and apply a voltage to the test TSVs to test an electrical property of the conductive layer between the test TSVs.
PNG
media_image2.png
302
480
media_image2.png
Greyscale
Pagani’s Figure 6-Annotated.
However, in the same semiconductor device field of endeavor, Pagani discloses
a substrate (substrate including 6,5,4 and 3 in [0003], Fig. 6-Annotated) comprising a conductive layer (3’ a semiconductor material doped n and p type in [0031], Fig. 6), a first test TSV (9-left a TSV having a lateral insulating layer 18 in [0012,0013], Fig. 6-Annotated) formed through the insulating layer (4 a dielectric layer in [0003], Fig. 6) and a second test TSV (9-right a TSV having a lateral insulating layer 18 in [0012,0013], Fig. 6-Annotated) formed through the insulating layer (4 in [0003], Fig. 6) and partially through the conductive layer (3 in [0003], Fig. 6) of the substrate (substrate), wherein the first test TSV (9-left, Fig. 6-Annotated) and the second test TSV (9-right, Fig. 6-Annotated) comprise test TSVs to the circuit TSVs ([0037]); and wherein the test TSVs (9-left 9-right, Fig. 6-Annotated) are formed such that an electrical test meter (32, probe head in [0014], Fig. 6) can contact and apply a voltage to the test TSVs (9-left 9-right, Fig. 6-Annotated) to test an electrical property of the conductive layer (3’) between the test TSVs (the resistance of the TSVs is measured to determine a fault of the TSVs in [0013, 0037], due the TSVs and the conductive layer 3’ are part of the circuit, electrical properties of the conductive layer 3’ are also measure because it is between the TSVs).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Pagani’s feature of a substrate comprising a conductive layer, a first test TSV formed through the insulating layer and a second test TSV formed through the insulating layer and partially through the conductive layer of the substrate, wherein the first test TSV and the second test TSV comprise test TSVs to the circuit TSVs; and wherein the test TSVs are formed such that an electrical test meter can contact and apply a voltage to the test TSVs to test an electrical property of the conductive layer between the test TSV to Lu’s device to measure a resistance of a differential type causing the test current to assume two distinct values and thus measure two corresponding differences of potential ([0013], Pagani).
Re: Claim 2, Lu modified by Pagani discloses the test structure of claim 1, wherein the first test TSV (TSV 102, Lu) and the second test TSV (TSVs-9, Pagani applied to Lu) are at least partially insulated (Fig. 1, Lu) from one or more layers (108, Lu) of the substrate.
Re: Claim 3, Lu modified by Pagani discloses the test structure of claim 1, wherein the first test TSV (9-left from Pagani applied to Lu, Fig. 6-Annotated) and the second test TSV (9-right from Pagani applied to Lu, Fig. 6-Annotated) are at least partially lined with a lining (18 from Pagani applied to Lu, Fig. 6) comprising an electrically insulating material (18 from Pagani [0012] applied to Lu, Fig. 6) to at least partially insulate the first test TSV (9-left from Pagani applied to Lu, Fig. 6-Annotated) and the second test TSV (9-right from Pagani applied to Lu, Fig. 6-Annotated) from one or more layers (4,3 from Pagani applied to Lu, Fig. 6-Annotated) of the substrate (substrate from Pagani applied to Lu, Fig. 6-Annotated)); and wherein the lining is at least partially open (Fig. 6, Pagani) at a portion of the first (9-left from Pagani applied to Lu, Fig. 6-Annotated) and second (9-right from Pagani applied to Lu, Fig. 6-Annotated) TSVs.
Re: Claim 6, Lu modified by Pagani discloses the test structure of claim 1, wherein the test structure is formed as part of a circuit wafer (wafer W in [0034], Fig. 2, Lu) comprising a substrate (100 made of silicon in [0034], Fig. 2, Lu), a plurality of ICs (chip region RC, in [0034], Fig. 2), and one or more dicing streets (scribe line region RSL, in [0034], Fig. 2, Lu), the circuit wafer (wafer W, Lu) being configured to be separated into dies (the scribe line region RSL may be used to define the chip region RC in [0034], Fig. 2, Lu), each die comprising an IC (RC, Lu), and wherein, the test structure is disposed in at least one of the dicing streets (the test region RT of FIG. 1 may be located in the scribe line region RSL Fig. 2, Lu) of the circuit wafer (wafer W, Lu).
Re: Claim 7, Lu modified by Pagani discloses the test structure of claim 1, wherein the first test TSV (9-left from Pagani applied to Lu, Fig. 6-Annotated) and the second test TSV (9-right from Pagani applied to Lu, Fig. 6-Annotated) are configured to be connected by a test probe during testing (it is possible to measure a resistance of a differential type causing the test current to assume two distinct values and thus measure two corresponding differences of potential in [0013], Pagani) of the integrity of the first and second TSVs, wherein the circuit TSVs are established to be inoperable when an electrical property of the conductive layer measured between the first and second test TSVs is outside of a predetermined value range (the resistance of the TSVs are measured to determine a fault of the TSVs in [0013], due the TSVs and the conductive layer 3’ are part of the circuit, electrical properties of the conductive layer 3’ are also measure because it is between the TSVs); and wherein the circuit TSVs are established to be operable when the electrical property of the conductive layer measured between the first and second test TSVs is within the predetermined value range ([0013, 0037], Pagani).
Re: Claim 8, Lu modified by Pagani discloses an integrated circuit wafer (wafer W in [0034], Fig. 2, Lu) comprising: a substrate (substrate including a dielectric layer 108 and a silicon layer 100 in [0034, 0038], Fig. 1-Annotated, Lu) comprising a conductive layer (100 made of silicon in [0034], Fig. 1, Lu) and an insulating layer (108 in [0038], Fig. 1, Lu); one or more circuit TSVs (TSVs 106 in [0037], Fig. 1, Lu) formed at least partially through the substrate (substrate, Lu) and associated with an integrated circuit (IC) (chip region RC, in [0034], Fig. 2, Lu); and a test structure (test structure from Pagani applied to Lu in [0002], Fig. 1) as recited in claim 1.
Re: Claim 9, Lu modified by Pagani discloses the integrated circuit wafer of claim 8, wherein the first test TSV (9-left from Pagani applied to Lu, Fig. 6-Annotated) and the second test TSV (9-right from Pagani applied to Lu, Fig. 6-Annotated) are at least partially insulated (Fig. 1, Lu) from one or more layers (108, Lu) of the substrate (substrate, Lu).
Re: Claim 10, Lu modified by Pagani discloses the integrated circuit wafer of claim 9, wherein the first test TSV (9-left from Pagani applied to Lu, Fig. 6-Annotated) and the second test TSV (9-right from Pagani applied to Lu, Fig. 6-Annotated) are at least partially lined with a lining (18 from Pagani applied to Lu, Fig. 6) comprising an electrically insulating material (18 from Pagani [0012] applied to Lu, Fig. 6) to at least partially insulate the first test TSV (9-left from Pagani applied to Lu, Fig. 6-Annotated) and the second test TSV (9-right from Pagani applied to Lu, Fig. 6-Annotated) from one or more layers (4,3 from Pagani applied to Lu, Fig. 6-Annotated) of the substrate (substrate from Pagani applied to Lu, Fig. 6-Annotated)); and wherein the lining is at least partially open (Fig. 6, Pagani) at a portion of the first (9-left from Pagani applied to Lu, Fig. 6-Annotated) and second (9-right from Pagani applied to Lu, Fig. 6-Annotated) TSVs.
Re: Claim 11, Lu modified by Pagani discloses the integrated circuit wafer of claim 8, wherein the one or more circuit TSVs (TSV 106, Lu) are electrically insulated (Fig. 1, Lu) from one or more layers (108, Lu) of the substrate.
Re: Claim 12, Lu modified by Pagani discloses the integrated circuit wafer of claim 8, wherein the one or more circuit TSVs (9-left, 9-right from Pagani applied to Lu, Fig. 6-Annotated) is at least partially lined (18 from Pagani applied to Lu, Fig. 6) with an electrically insulating material (18 from Pagani [0012] applied to Lu, Fig. 6) to insulate the one or more circuit TSVs (9-left, 9-right from Pagani applied to Lu, Fig. 6-Annotated) from one or more layers of the substrate (108, Lu).
Re: Claim 15, Lu modified by Pagani discloses the integrated circuit wafer (wafer W, Fig. 2, Lu) of claim 8, further comprising: a plurality of ICs (chip region RC, in [0034], Fig. 2, Lu) formed thereon; and one or more dicing streets (scribe line region RSL, in [0034], Fig. 2, Lu); wherein the integrated circuit wafer (wafer W, Fig. 2, Lu) is configured to be separated into dies (the scribe line region RSL may be used to define the chip region RC in [0034], Fig. 2, Lu), each die comprising an IC (RC, Lu); and wherein, the test structure is disposed in at least one of the dicing streets (the test region RT of FIG. 1 may be located in the scribe line region RSL Fig. 2, Lu) of the circuit wafer (wafer W, Lu).
Re: Claim 16, Lu modified by Pagani discloses the integrated circuit wafer of claim 8, wherein the first test TSV (9-left from Pagani applied to Lu, Fig. 6-Annotated) and the second test TSV (9-right from Pagani applied to Lu, Fig. 6-Annotated) are configured to be connected by a test probe during testing (it is possible to measure a resistance of a differential type causing the test current to assume two distinct values and thus measure two corresponding differences of potential in [0013], Pagani) of the integrity of the first and second TSVs, wherein the circuit TSVs are established to be inoperable when an electrical property of the conductive layer measured between the first and second test TSVs is outside of a predetermined value range (the resistance of the TSVs are measured to determine a fault of the TSVs in [0013], due the TSVs and the conductive layer 3’ are part of the circuit, electrical properties of the conductive layer 3’ are also measure because it is between the TSVs); and wherein the circuit TSVs are established to be operable when the electrical property of the conductive layer measured between the first and second test TSVs is within the predetermined value range ([0013, 0037], Pagani).
Claim(s) 4-5 and 13-14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lu in view of Pagani and further in view of Rahman (US 8933345 B1, hereinafter Rahman, of the record).
Re: Claim 4, Lu modified by Pagani discloses the test structure of claim 1,
Lu modified by Pagani does not expressly disclose further comprising a first array of test TSVs comprising the first test TSV.
However, in the same semiconductor device field of endeavor, Rahman discloses further comprising a first array (TSVs-222 Fig. 2C-Annotated) of test TSVs comprising the first test TSV (TSVs-222).
PNG
media_image3.png
272
658
media_image3.png
Greyscale
Rahman’s Figure 2C-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Rahman’s feature of further comprising a first array of test TSVs comprising the first test TSV to the combination of Lu and Pagani to electrically connects more conducting vias to obtain more information of TSVs (Col. 1, lines 61-64, Rahman).
Re: Claim 5, Lu modified by Pagani discloses the test structure of claim 1,
Lu modified by Pagani does not expressly disclose further comprising a second array of test TSVs comprising the second test TSV.
However, in the same semiconductor device field of endeavor, Rahman discloses further comprising a second array (TSVs-224 Fig. 2C-Annotated) of test TSVs comprising the first test TSV (TSVs-224).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Rahman’s feature of further comprising a second array of test TSVs comprising the second test TSV the combination of Lu and Pagani to electrically connects more conducting vias to obtain more information of TSVs (Col. 1, lines 61-64, Rahman).
Re: Claim 13, Lu modified by Pagani discloses the integrated circuit wafer of claim 8,
Lu modified by Pagani does not expressly disclose further comprising a first array of test TSVs comprising the first test TSV.
However, in the same semiconductor device field of endeavor, Rahman discloses further comprising a first array (TSVs-222 Fig. 2C-Annotated) of test TSVs comprising the first test TSV (TSVs-222).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Rahman’s feature of further comprising a first array of test TSVs comprising the first test TSV to the combination of Lu and Pagani to electrically connects more conducting vias to obtain more information of TSVs (Col. 1, lines 61-64, Rahman).
Re: Claim 14, Lu modified by Pagani discloses the integrated circuit wafer of claim 8,
Lu modified by Pagani does not expressly disclose further comprising a second array of test TSVs comprising the second test TSV.
However, in the same semiconductor device field of endeavor, Rahman discloses further comprising a second array (TSVs-224 Fig. 2C-Annotated) of test TSVs comprising the first test TSV (TSVs-224).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Rahman’s feature of further comprising a second array of test TSVs comprising the second test TSV to the combination of Lu and Pagani to electrically connects more conducting vias to obtain more information of TSVs (Col. 1, lines 61-64, Rahman).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
Prosecution Insights