DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Continued Examination Under 37 CFR 1.114
5. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/05/2026 has been entered.
Response to Arguments
6. Applicant’s arguments, see Remarks, filed 3/05/2026, with respect to the rejection of claim 1 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Cheng, Chung-Liang (Pub No. US 20210375698 A1) (hereinafter, Cheng) in view of Lee, Choonghyun et al. (Pub No. US 20200020768 A1) (hereinafter, Lee).
7. Applicant’s arguments with respect to claim 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 1, 3-5, 7 and 9 rejected under 35 U.S.C. 103 as being unpatentable over Cheng, Chung-Liang (Pub No. US 20210375698 A1) (hereinafter, Cheng), and further in view of Lee, Choonghyun et al. (Pub No. US 20200020768 A1) (hereinafter, Lee).
Cheng, Fig 1A: 3D view of semiconductor device
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Re Claim 1 (Currently Amended), Cheng teaches a semiconductor structure comprising;
a semiconductor substrate (Semiconductor substrate; 106; Figs 1H/1I; ¶[0021]) having a pFET device region (Fig 1I) and an nFET device region (Fig 1H);
a shallow trench isolation structure (Shallow trench isolation regions; 119; Figs 1H/1I; ¶[0022]; Note: per ¶[0022] they electrically isolate NFETS and PFETS) located in the semiconductor substrate;
a pFET (PFET; 102P1; Fig 1I; ¶[0020]) located in the pFET device region, wherein the pFET comprises a first functional gate structure (Gate structure and source/drain regions; 112P1/112P2 and 110P; Figs 1A/1I; ¶[0028]) wrapped around a plurality of pFET semiconductor channel material nanosheets (Nanostructured channel regions; 122P; Fig 1K; ¶[0028]);
wherein the first functional gate structure comprises a first gate dielectric material (Gate dielectric layers in pFET; 128; Fig 1I; ¶[0029]), a p-type work function metal (Glue layers; 136P; Fig 1I; ¶[0035]), and a first gate electrode (Gate metal fill layer; 144P; Figs 1I/1K; ¶[0040]);
Cheng, Figs 1H & 1I: Cross-section in zy-plane of semiconductor device
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Cheng, Figs 1J & 1K: Cross-section in zx-plane of semiconductor device
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an nFET (NFET; 102N1; Fig 1H; ¶[0020]) located in the nFET device region, wherein the nFET comprises a second functional gate structure (Gate structure and source/drain regions; 112N1/112N2 and 110N; Fig 1H; ¶[0028]) wrapped around a plurality of nFET semiconductor channel material nanosheets (Nanostructured channel regions; 120N; Fig 1J; ¶[0028]),
wherein the second functional gate structure comprises a second gate dielectric material (Gate dielectric layers in nFET; 128; Fig 1H; ¶[0029]), an n-type work function metal (Glue layers; 136N; Fig 1H; ¶[0035]), and a second gate electrode (Gate metal fill layer; 144N; Figs 1H/1J; ¶[0039]) and
each pFET semiconductor channel material nanosheet of the plurality of pFET semiconductor channel material nanosheets is vertically offset (Vertically staggered; Figs 1J/1K) from each nFET semiconductor channel material nanosheet of the plurality of pFET semiconductor channel material nanosheets; and
a bottom dielectric isolation structure (Gate dielectric immediately above 119; 128; Figs 1H/1I; ¶[0028]) located in both the pFET device region and the nFET device region, and above the semiconductor substrate,
wherein the bottom dielectric isolation structure is located between the first functional gate structure and the semiconductor substrate and between the second functional gate structure and the semiconductor substrate,
and wherein each of the p-type work function metal of the first functional gate structure and the n-type work functional metal of the second functional gate structure has a bottommost surface (Bottommost surface of 136N/136P; Fig 1A) that extends beneath a topmost surface (Highest surface of gate dielectric 128; Fig 1I) of the bottom dielectric isolation structure and is above a topmost surface of the shallow trench isolation structure.
However, Cheng does not teach a bottom dielectric isolation structure located in both the pFET device region and the nFET device region and above and in direct physical contact with the semiconductor substrate.
In the same field of endeavor, Lee teaches a bottom dielectric isolation structure (Dielectric isolation layer; 11; Fig 13; ¶[0046]) located in both the pFET device region (Region below pFET; Fig 13) and the nFET device region (Region below nFET; Fig 13) and above and in direct physical contact with the semiconductor substrate (10; Fig 13; ¶[0023]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a bottom dielectric isolation structure located in both the pFET device region and the nFET device region and above and in direct physical contact with the semiconductor substrate, as taught by Lee, for the semiconductor structure of Cheng. One would have been motivated to do this with a reasonable expectation of success in order to electrically isolate the semiconducting substrate from the pFET/nFET regions above. Further, by electrically isolating the transistors and substrate, the parasitic capacitance between them is reduced, as well as eliminating junction leakage currents into the substrate.
Re Claim 3 (Original), Cheng teaches the semiconductor structure of Claim 1, wherein the bottom dielectric isolation structure (Gate dielectric immediately above 119; 128; Figs 1H/1I; ¶[0028]) is a single layered structure (Composed of the same material; Figs 1H/1I).
Re Claim 4 (Original), Cheng teaches the semiconductor structure of Claim 1, wherein each pFET semiconductor channel material nanosheet (Nanostructured channel regions; 122P; Fig 1K; ¶[0028]) of the plurality of pFET semiconductor channel material nanosheets is dumbbell shaped (Polygonal; ¶[0024]).
Re Claim 5 (Original), Cheng teaches the semiconductor structure of Claim 1, wherein each nFET semiconductor channel material nanosheet (Nanostructured channel regions; 120N; Fig 1K; ¶[0028]) of the plurality of nFET semiconductor channel material nanosheets is dumbbell shaped (Polygonal; ¶[0024]).
Re Claim 7 (Original), Cheng teaches the semiconductor structure of Claim 1, wherein the pFET (PFET; 102P1; Fig 1I; ¶[0020]) further comprises a first source/drain region (Source/drain regions; 110P; Fig 1K; ¶[0022]) extending outward from each pFET semiconductor channel material nanosheet (Nanostructured channel regions; 122P; Fig 1K; ¶[0028]) of the plurality of pFET semiconductor channel material nanosheets and present on both sides of the first functional gate structure (Gate structure and source/drain regions; 112P1/112P2 and 110P; Figs 1A/1I; ¶[0028]),
and wherein the nFET (NFET; 102N1; Fig 1H; ¶[0020]) further comprises a second source/drain region (Source/drain regions; 110N; Fig 1J; ¶[0022]) extending outward from each nFET semiconductor channel material nanosheet (Nanostructured channel regions; 120N; Fig 1J; ¶[0028]) of the plurality of nFET semiconductor channel material nanosheets and present on both sides of the second functional gate structure (Gate structure and source/drain regions; 112N1/112N2 and 110N; Fig 1H; ¶[0028]),
and wherein the first source/drain region and the second source/drain region are both isolated from the semiconductor substrate (Semiconductor substrate; 106; Figs 1A; ¶[0021]) by the bottom dielectric isolation structure (Shallow trench isolation (STI) regions; 119; Fig 1A; ¶[0022]; Note: per ¶[0022] they electrically isolate NFETS and PFETS).
Re Claim 9 (Original), Cheng teaches the semiconductor structure of Claim 1, wherein the first functional gate structure (Gate structure and source/drain regions; 112P1/112P2 and 110P; Figs 1A/1I; ¶[0028]) and the second functional gate structure (Gate structure and source/drain regions; 112N1/112N2 and 110N; Fig 1H; ¶[0028]) are independent gate structures that are spaced apart by a gate cut region (Isolation structure; 104; Fig 1A; ¶[0022]).
10. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng, Chung-Liang (Pub No. US 20210375698 A1) (hereinafter, Cheng) in view of Lee, Choonghyun et al. (Pub No. US 20200020768 A1) (hereinafter, Lee) as applied to Claim 1 above, and further in view of Chen, Ting-Yeh et al. (Pub No. US 20220384660 A1) (hereinafter, Chen).
Chen, Fig 16A: Semiconductor device with epitaxial bridge feature
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Re Claim 2 (Original), Cheng in view of Lee does not teach the semiconductor structure of Claim 1, wherein the bottom dielectric isolation structure is a bottom dielectric isolation bilayer structure comprising a first dielectric material layer composed of a first dielectric material,
and a second dielectric material layer composed of a second dielectric material that is compositionally different from the first dielectric material.
In the same field of endeavor, Chen teaches the semiconductor structure of Claim 1, wherein the bottom dielectric isolation structure is a bottom dielectric isolation (Isolation structure; 204; Fig 16A; ¶[0017]) bilayer structure (Per ¶[0017] one or more dielectric materials is deposited over substrate 202... to form isolation structure 204) comprising a first dielectric material layer composed of a first dielectric material (Silicon oxide (SiO); ¶[0017]),
and a second dielectric material layer (Isolation structure; 204; Fig 16A; ¶[0017]) composed of a second dielectric material (Silicon nitride (SiN); ¶[0017]) that is compositionally different from the first dielectric material.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a bottom dielectric isolation bilayer structure composed of two different materials, as taught by Chen, for the semiconductor structure of Cheng in view of Lee. One would have been motivated to do this with a reasonable expectation of success because the pFET and nFET regions are comprised of different materials, and therefore they may be substantially more electrically isolated from each other based on the surrounding dielectric materials.
11. Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng, Chung-Liang (Pub No. US 20210375698 A1) (hereinafter, Cheng) in view of Lee, Choonghyun et al. (Pub No. US 20200020768 A1) (hereinafter, Lee) as applied to Claim 1 above, and further in view of Kim, Jinbum et al. (Pub No. US 20220352309 A1) (hereinafter, Kim).
Kim, Figs 19B/19C: Semiconductor structure with bottom dielectric isolation structure and a shared gate electrode
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Re Claim 8 (Original), Cheng in view of Lee does not teach the semiconductor structure of Claim 1, wherein the bottom dielectric isolation structure in a gate region of both the nFET has a first thickness,
and the bottom dielectric isolation structure in a source/drain region of the nFET has a second thickness that differs from the first thickness.
In the same field of endeavor, Kim teaches the semiconductor structure of Claim 1, wherein the bottom dielectric isolation structure (Air gap regions; AG; Fig 19B; ¶[0019]) in a gate region (Under gate structure 160; Fig 19B) of both the nFET has a first thickness (Thickness includes AG1/AG2/AG3; Fig 19B),
and the bottom dielectric isolation structure in a source/drain region (Source/drain regions; 150; Fig 19B; ¶[0019]) of the nFET has a second thickness (Thickness includes AG1/AG2; Fig 19B) that differs from the first thickness.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a bottom dielectric isolation structure with varying thicknesses in the gate region and source/drain region, as taught by Kim, for the semiconductor structure of Cheng in view of Lee. One would have been motivated to do this with a reasonable expectation of success because a dielectric isolation structure, such as the air gaps of Kim, causes manufacturing difficulty if the thickness exceeds a range of 10 nm and causes less than optimal electrical performance of the transistors if the range is less than 1 nm, as suggested by Kim (¶[0031]).
Re Claim 10 (Original), Cheng in view of Lee does not teach the semiconductor structure of Claim 1, wherein the first functional gate structure and the second functional gate structure comprise a shared gate electrode.
In the same field of endeavor, Kim teaches the semiconductor structure of Claim 1, wherein the first functional gate structure (Left hand side gate structures vertically aligned with channel structures 140; Fig 19C) and the second functional gate structure (Right hand side gate structures vertically aligned with channel structures 140; Fig 19C) comprise a shared gate electrode (Gate electrode; 165; Fig 19C; ¶[0020]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have created the first functional gate structure and the second functional gate structure to comprise of a shared gate electrode, as taught by Kim, for the semiconductor structure of Cheng in view of Lee. One would have been motivated to do this with a reasonable expectation of success in order to yield lower leakage currents, increased performance and faster switching speeds and meet the demand for devices of a higher density by integrated a shared gate electrode between separate channel layers, as suggested by Kim ¶[0003]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Bi, Zhenxing et al. (Pub No. US 10263100 B1) discloses fabrication methods and resulting structures for vertically stacked nanosheet transistors configured and arranged to provide selectively formed buffer regions for blocking unwanted diffusion between sacrificial nanosheets and channel nanosheets.
[2] Zhang, Jingyun et al. (Pub No. US 10886368 B2) discloses a semiconductor structure (i.e., input/output (I/O) device) having improved inter-nanosheet spacing between each semiconductor channel material nanosheet of a plurality of stacked and suspended semiconductor channel material nanosheets, as well as a method of forming the same, which method is compatible with nominal logic device processing.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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