DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Oct. 21st, 2025 has been entered. Claims 1-3, 5-17 and 19 remain pending in the application. Claims 1-3, 5, 17 and 19 are examined in this office action. Claims 6-16 are withdrawn from further consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US 20110127522) in view of Wang et al. (US 20200044095).
Regarding claim 1, Yamazaki teaches a vertical field effect transistor (Abstract) comprising:
a substrate (fig. 1B, substrate 101; para. 0135);
a source electrode (first electrode 105 as source electrode; para. 0015, 0135) positioned on the substrate (101);
an active layer (oxide semiconductor film 107; para. 0135) positioned on the source electrode (105) and having vertically grown crystal grains (detail in fig. 9E, oxide semiconductor film has upward crystal growth proceeds as vertically grown crystal grains of the second oxide semiconductor film; para. 0202);
a drain electrode (second electrode 109 as a drain electrode; para. 0015, 0135) positioned on the active layer (107) in such a manner (fig. 11B, 109 spaced away from 105) that the drain electrode (209) is spaced away from the source electrode (105) by the active layer (107);
a gate insulating layer (gate insulating film 111; para. 0135) positioned on a lateral surface (side surface) of the active layer (107); and
a gate electrode (third electrode 113as a gate electrode; para. 0015, 0135) positioned on the gate insulating layer (111).
Yamazaki fails to teach the active layer contains Cu2O.
However, Wang teaches the active layer (Wang: fig. 1B, semiconductor layer 120; para. 0031, similar to 107 of Yamazaki) contains Cu2O (Wang: 120 is Cu2O; para. 0031).
Wang and Yamazaki are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the material of the active layer contains Cu2O as taught by Wang.
Doing so would realize a material of the active layer more suitable for p-type conductivity and low cost (Wang: para. 0031). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 2, Yamazaki further teaches the vertical field effect transistor of claim 1, wherein the gate insulating layer (fig. 1B, 111) is positioned between the source electrode (105) and the gate electrode (113), between the active layer (107) and the gate electrode (113), and between the drain electrode (109) and the gate electrode (113).
Regarding claim 3, Yamazaki further teaches the vertical field effect transistor of claim 1, wherein the active layer (fig. 1B, 107) contains a p-type oxide semiconductor (107 is oxide semiconductor can with p-type carriers; para. 0130).
Regarding claim 5, Yamazaki further teaches the vertical field effect transistor of claim 1 including the active layer (fig. 1B, 107).
Yamazaki in view of Wang as applied to claim 1 above fails to explicitly teach the active layer has a thickness that is more than 0.5 μm and equal to or less than 2.0 μm.
However, Yamazaki teaches the active layer (fig. 1B, 107) has a thickness that is greater than or equal to 1 μm (greater than or equal to 1 μm; para. 0066), which overlaps the thickness range more than 0.5 μm and equal to or less than 2.0 μm.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness range from greater than or equal to 1 μm to more than 0.5 μm and equal to or less than 2.0 μm.
Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Claims 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Wang as applied to claim 1 above, and further in view of Okushima et al. (US 20070194380).
Regarding claim 17, Yamazaki in view of Wang teaches a generic inverter (Yamazaki: inverter; para. 0285) comprising:
a generic transistor (Yamazaki: fig. 1B, p-channel transistor; para. 0130) in which the active layer (Yamazaki: 107) of the vertical field effect transistor of claim 1 is formed of a P-type oxide semiconductor (Yamazaki: 107 is oxide semiconductor with p-type carriers; para. 0130); and
another generic transistor (Yamazaki: another fig. 1B, n-channel transistor; para. 0130) in which the active layer (Yamazaki: 107) of the vertical field effect translator of claim 1 is formed of an N-type oxide semiconductor (Yamazaki: another fig. 1B, 107 is oxide semiconductor with n-type carriers; para. 0130).
Yamazaki in view of Wang fails to explicitly teach the generic inverter is a CMOS inverter comprising:
a PMOS; and an NMOS.
However, Okushima teaches the generic inverter is a CMOS inverter (Okushima: fig. 1, CMOS transistor 100; para. 0054) comprising:
a PMOS (Okushima: PMOS transistor 102; para. 0054); and
an NMOS (Okushima: NMOS transistor 101; para. 0054).
Okushima, Wang and Yamazaki are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modifed the inverter as CMOS inverter comprising PMOS and NMOS as taught by Okushima.
Doing so would realize an inverter for more complex functions and increase miniaturization (Okushima: para. 0005).
Regarding claim 19, Yamazaki further teaches the CMOS inverter of claim 17, wherein the active layer (fig. 1B, 107) of the PMOS (p-channel transistor) and the active layer of the NMOS (n-channel transistor).
Yamazaki in view of Wang and Okushima as applied to claim 17 fails to explicitly the active layer has a thickness that is more than 0.5 μm and equal to or less than 2.0 μm.
However, Yamazaki teaches the active layer (fig. 1B, 107) have a thickness is greater than or equal to 1 μm (greater than or equal to 1 μm; para. 0066), which overlaps the thickness range is more than 0.5 μm and equal to or less than 2.0 μm.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness range from greater than or equal to 1 μm to more than 0.5 μm and equal to or less than 2.0 μm.
Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 5, 17 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHIJUN XU/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 1/22/26