Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/12/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11-13, and 36-37 are rejected under 35 U.S.C. 103 as being unpatentable over Xie’21 et al (US 20210210349 A1) in view of Xie ’23 et al (US 20230299085 A1) and further in view of Xie’21 #2 et al (US 20210210349 A1). Xie’21 et al, Xie’23 et al, and Xie’21 #2 et al will be referenced to as Xie’21, Xie’23, and Xie’21 #2 henceforth.
Regarding Claim 1,
Xie’21 teaches:
“A multi-stack semiconductor device comprising: a substrate (substrate 102, [0032], FIG. 12);
a lower field-effect transistor (NFET nanosheets, [0041], annotated FIG. 12 #1) in which a lower channel structure (layer of Si 106b, [0035], FIG. 12: a channel is a layer of silicon, or other semiconductor material, in which current passes through when the gate of the transistor is activated.) is surrounded by a lower gate structure (gate insulator 137 lower, work function metal 138, work function metal 142 lower, [0058], [0059], [0063], annotated FIG. 12 #2: To be clear, 137 is referenced in [0058] and 142 is referenced in [0063]. However, both 137 and 142 have different geometries in the PFET nanowires than from the NFET nanosheets. Therefore, the Examiner has labeled 142 upper and 142 lower in annotated FIG. 12 #2 to distinguish between the two.) comprising a lower work-function metal layer (work function metal layer 138, [0059], FIG. 12) and a lower gate electrode (N-FET work function metal 142, [0063], FIG. 12);
and an upper field-effect transistor (PFET nanowires, [0042], annotated FIG. 12 #1) in which an upper channel structure (layers of Si 110a, [0037], FIG. 12) is surrounded by an upper gate structure (gate insulator upper, work function 142 upper, metal gate 144, [0058], [0063], annotated FIG. 12 #2 ) comprising an upper work-function metal layer (work function 142 upper, annotated, [0058], FIG. 12 #2) and an upper gate electrode (metal gate 144, [0063], FIG. 12) and the upper gate electrode comprises a metal or a metal compound ([0063]: 144 may comprise tungsten (W) which is a metal.).”
Xie’21 doesn’t substantially teach:
“and a gate inner spacer which is formed between the lower work-function metal layer and the upper work-function metal layer at selected regions where the lower channel structure is not vertically overlapped by the upper channel structure
However, Xie’21 #2 teaches:
“and a gate inner spacer (Xie’21 #2: sidewall spacer 702, [0092], FIG. 27: where the upper channel structure comprises 226’b [0092], the lower channel structure comprises 214’b [0092], and the work-function metals are 2602 and 2002 [0092].) which is formed between the lower work-function metal layer and the upper work-function metal layer at selected regions (Xie’21 #2: annotated FIG. 27 #3) where the lower channel structure is not vertically overlapped by the upper channel structure (Xie’21 #2: annotated FIG. 27 #3: Neither the upper channel structure nor the lower channel structure vertically overlap 702.)
Neither Xie’21 nor Xie’21 #2 substantially teach:
“wherein the lower gate electrode comprises polycrystalline silicon (poly-Si) or poly-Si,”
However, Xie’23 teaches:
“wherein the lower gate electrode comprises polycrystalline silicon (poly-Si) or poly-Si (Xie ‘23: functional gates 164, [0091], FIG 21: the functional gates of Xie’23are also gate electrodes which surround channels (118 in Xie’23).) comprising a dopant (Xie’23: [0091], the polysilicon is doped),”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Xie’21 is modifiable in view of Xie’21 #2 and Xie’23.
This is because the invention of Xie’21 #2 teaches the advantage of dielectric separation between the work-function materials of a PFET and NFET (Xie’21 #2: [0092]). Providing this dielectric separation is advantageous because the dielectric separation of work-function metals near channels reduces electrical interference between the NFET and PFET devices as one of ordinary skill in the art would recognize. Therefore one of ordinary skill in the art would incorporate the dielectric separation of work function metals of Xie’21 #2 into Xie’21.
Further this is because Xie’21 teaches a gate electrode made of a metal such as titanium, tantalum, aluminum, or a work function metal which has a work function similar to that of N-doped polysilicon (Xie 21: [0062]). Xie’21 doesn’t substantively teach a gate electrode made from doped polysilicon. Xie’23teaches a gate electrode made of doped polysilicon, titanium, tantalum, or aluminum. Because both Xie’21 and Xie’23 have a gate electrode made of similar materials which have a work function similar to N-doped polysilicon (Xie’21: [0062]), one of ordinary skill in the art would have deemed it obvious to substitute the gate electrode of Xie’21 for the gate electrode of Xie’23for the predictable result of conducting electricity throughout a transistor with the desired work function layer properties.
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Xie’21: Annotated FIG. 12 #1
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Xie’21: Annotated FIG. 12 #2
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Xie’21 #2: Annotated FIG. 27 #3
Regarding Claim 11,
Xie’21/ Xie ‘23/ Xie’21 #2 teaches:
“The multi-stack semiconductor device of claim [[10]] 1, wherein, at the selected regions, a top surface of the lower work-function metal layer below the gate inner spacer (Xie’21 #2: annotated FIG. 27 #2) is lower than a level of a top surface of the lower gate electrode (Xie’21 #2: work-function setting metal 2602, [0092], annotated FIG. 27 #2: Xie’21 also teaches a lower gate electrode, Xie’21: 142.)”
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Xie’21 #2: Annotated FIG. 27 #2
Regarding Claim 12,
Xie’21/ Xie ‘23/ Xie’21 #2 teaches:
“The multi-stack semiconductor device of claim [[10]] 1, wherein a channel width of the upper channel structure (Xie’21: annotated FIG. 12 #3) is smaller than a channel width of the lower channel structure (Xie’21: annotated FIG. 12 #3), wherein each of the lower channel structure and the upper channel structure has one or more nanosheet channel layers (Xie’21: annotated FIG. 12 #3), and wherein the upper channel structure has a greater number of the nanosheet channel layers than the lower channel structure (Xie’21: annotated FIG. 12 #3).”
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Xie’21: Annotated FIG. 12 #3
Regarding Claim 13,
Xie’21/ Xie ‘23/ Xie’21 #2 teaches:
“The multi-stack semiconductor device of claim [[10]] 1, wherein the selected regions comprise a side of the lower gate electrode (Xie’21: annotated FIG. 12 #3) when viewed in a channel-width direction (Xie’21 FIG. 12: The channel-width direction is along Y on the right side of FIG. 12.) where the gate inner spacer is not vertically overlapped by any of the lower channel structure and the upper channel structure (Xie’21 #2: sidewall spacer 702, [0092], FIG. 27: where the upper channel structure comprises 226’b [0092], the lower channel structure comprises 214’b [0092], and the work-function metals are 2602 and 2002 [0092].) ”
Regarding Claim 36,
Xie’21/ Xie ‘23/ Xie’21 #2 teaches:
“The multi-stack semiconductor device of claim 1, wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure (Xie’21: annotated FIG. 12 #3), wherein each of the lower channel structure and the upper channel structure has one or more nanosheet channel layers (Xie’21: annotated FIG. 12 #3), and wherein the upper channel structure has a greater number of the nanosheet channel layers than the lower channel structure (Xie’21: annotated FIG. 12 #3).”
Regarding Claim 37,
Xie’21/ Xie ‘23/ Xie’21 #2 teaches:
“The multi-stack semiconductor device of claim 1, wherein the lower work-function metal layer and the upper work-function metal layer comprise different materials, respectively (Xie’21: 142 may comprise aluminum carbide. 138 may comprise titanium nitride. Aluminum carbide is not titanium nitride.).”
Allowable Subject Matter
Claims 4-5, and 35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 4,
Xie’21/ Hekmatshoartabari/Xie’23/Xie’21 #2 fails to explicitly teach :
“wherein the gate inner spacer which is formed between the lower work-function metal layer and the upper work-function metal layer at selected regions the upper work-function metal layer vertically overlaps the lower work-function metal layer.” In view of the rest of the limitations of claim 4.
Xie’21/ Hekmatshoartabari/Xie’23/Xie’21 #2 fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record.
This is because Xie’21/ Hekmatshoartabari/Xie’23/Xie’21 #2 does not simultaneously teach the above limitation along with the limitation, “the lower channel structure is not vertically overlapped by the upper channel structure”. This is because in Xie’21 #2, the gate spacer is horizontally between the lower work-function metal and the upper work-function metal in a region where the lower channel structure is not vertically overlapped by the upper channel structure. In this same region however, the upper work-function metal does not overlap the lower work-function metal layer.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Xie’21/ Hekmatshoartabari/Xie’23/Xie’21 to reach all of the limitations of the claim.
Regarding Claims 5 and 35 these claims depend on claim 4 and are objected to for the same reasons.
Response to Arguments
Applicant’s amendments to the Claims have overcome the Examiner’s 103 rejections in the Examiner’s final action dated to 12/23/2025. However, Applicant’s amendments to the claims have not overcome the Examiner’s rejections as set forth in the Examiner’s non-final office action dated on 07/09/2025.
This is because the limitations of claim 1 as described in Applicant’s claims as set forth on 3/12/2026 are the same as the limitations of claim 4 in Applicant’s claims as set forth on 10/12/2022. Because of this, the Examiner’s rejection of claim 4 as set forth in the Examiner’s non-final office action dated on 07/09/2025 may be made on claim 1 of Applicant’s claim set as set forth on 3/12/2026. Therefore, claim 1 of the claim set as set forth on 3/12/2026 is rejected with Xie’21/Xie’23/Xie’ 21 #2.
In the interest of compact prosecution, the Examiner suggests Applicant incorporates the limitations of claim 4 into independent claim 1.
Doing so would overcome the current rejections for independent claim 1. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights