Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-3 and 12-15are rejected under 35 U.S.C. 103 as being unpatentable over Huang (PGPub No. 20210375758) in further view of Yoon (US Patent No. 10249503).
Regarding claim 1, Huang teaches a semiconductor structure comprising: a contact structure comprising a source/drain contact and a via contact, wherein the via contact is located above the source/drain contact and includes a first via portion having a first critical dimension, and a second via portion having a second critical dimension (Fig. 10A points to a source/drain contact structure 2120 comprising a base portion 212b (source/drain contact) and a via portion 212T (via contact) including a bottom portion (first via portion) and a top portion (second via portion) of different widths.); a source/drain region of a transistor located beneath the contact structure (Id. points to source/drain regions 202SD.); and an electrically conductive structure located on top of the contact structure and contacting the first via portion of the via contact (It is considered obvious that the source/drain contact structure 2120 would be used to place the source/drain regions 202SD in contact with at least one external component (electrically conductive structure), such that said component would be required to be in contact with the entirety of the via portion 212T (via contact).).
Huang fails to teach the second via portion having a second critical dimension that is greater than the first critical dimension.
Yoon teaches the second via portion having a second critical dimension that is greater than the first critical dimension (Fig. 4 points to a first metal layer 110 comprising an upper surface C (second critical dimension) and a lower surface B (first critical dimension).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Huang and Yoon, such that second via portion has a second critical dimension that is greater than the first critical dimension of the first via portion in order to create a tapered shape that allows for better contact at the top surface but increases contact resistance towards the bottom surface.
Regarding claim 2, Huang teaches wherein the first via portion is located on top of the second via portion (Fig. 10A points to the via portion 212T (via contact) including a bottom portion (first via portion) and a top portion (second via portion) of different widths.), and both the first via portion and the second via portion of the via contact are liner-less ([0013] points to a liner that may be optionally formed on the via portion.).
Regarding claim 3, Huang teaches a metal liner present along at least a sidewall of the source/drain contact (Fig. 10A and [0020] point to a glue layer 210.).
Regarding claim 12, Huang teaches a metal layer located along a sidewall of the second via portion of the via contact and on a horizontal surface of the source/drain contact (Fig. 11A points to a liner 224.).
Regarding claim 13, Huang teaches wherein the metal layer is composed of a compositionally same contact metal as the contact structure ([0020] and [0029] point to embodiments of material composition for the conductive feature 212 (contact structure) and the liner 224 (metal layer), respectively, such that both components may comprise the same metal(s) such as cobalt, tungsten, or ruthenium.).
Regarding claim 14, Huang teaches wherein the metal layer is composed of a compositionally different contact metal as the contact structure ([0020] and [0029] point to embodiments of material composition for the conductive feature 212 (contact structure) and the liner 224 (metal layer), respectively, such that only the liner 224 may a metal such as cobalt, tungsten, or ruthenium, while the conductive feature 212 may comprise aluminum or copper.).
Regarding claim 15, Huang teaches wherein the source/drain contact and the via contact including the first via portion and the second via portion are of unitary construction ([0024] points to the via portion 212T (via contact) and the base portion 212B (source/drain contact) being continuous or one-piece.).
Claim(s) 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. in further view of Wu (PGPub No. 20210375753).
Regarding claim 4, Wu teaches wherein the source/drain contact is spaced apart from the source/drain region by at least a metal semiconductor alloy layer (Fig. 5B points to a structure comprising source/drain regions 36/38, metal-semiconductor alloy regions 66/68, and contact via structure(s) 78.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Huang et al. and Wu, such that a metal semiconductor alloy layer is formed between the source/drain contact and source/drain region in order to create a low-resistance electrical connection between the two source/drain components.
Regarding claim 5, Wu teaches wherein the source/drain region contacts a sidewall of a semiconductor channel material structure, the semiconductor channel material structure is located beneath a gate structure of the transistor (Fig. 5B points to the source/drain regions 36/38, a semiconductor material layer 10, and a gate stack made up of a gate dielectric 50 and a gate electrode 54.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Huang et al. and Wu, such that a semiconductor channel material structure is formed in order to provide a level of electrical isolation for the source/drain region.
Claim(s) 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. in further view of Wan (PGPub No. 20200135859).
Regarding claim 6, Wan teaches wherein the semiconductor channel material structure comprises a vertical stack of spaced apart nanosheets (Fig. 2A and [0025] point to a semiconductor device comprising a semiconductor fin 102, which may be further patterned into nanosheets.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Huang et al. and Wan, such that the semiconductor channel material structure comprises a vertical stack of spaced apart nanosheets in order to create a gate-all-around field-effect transistor (GAAFET) structure optimized for high drive current and performance.
Regarding claim 7, Wan teaches wherein the semiconductor channel material structure comprises a semiconductor fin (Fig. 2A points to a semiconductor device comprising the semiconductor fin 102.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Huang et al. and Wan, such that the semiconductor channel material structure comprises a semiconductor fin in order to create a FinFET structure.
Regarding claim 8, Wan teaches wherein the semiconductor channel material structure comprises at least one semiconductor nanowire (Fig. 2A and [0025] point to the semiconductor fin 102, which may be further patterned into nanowires.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Huang et al. and Wan, such that the semiconductor channel material structure comprises at least one semiconductor nanowire in order to create a gate-all-around field-effect transistor (GAAFET) structure with improved power efficiency.
Claim(s) 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. in further view of Otsu (PGPub No. 20200402992).
Regarding claim 9, Otsu teaches herein the source/drain contact is embedded in a first interlayer dielectric material layer (Fig. 1A points to a structure comprising active regions 742 (i.e., source regions and drain regions) and the bottom portion of contact via structures 782 (source/drain contact) which is embedded in a dielectric liner 762 (first interlayer dielectric material layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Huang et al. and Otsu, such that the source/drain contact is embedded in a first interlayer dielectric material layer in order to block the diffusion of mobile ions and/or apply appropriate stress to underlying structures.
Regarding claim 10, Otsu teaches a second interlayer dielectric material layer located above the first interlayer dielectric material layer, wherein the second interlayer dielectric material layer embeds the first via portion and the second via portion of the via contact and the electrically conductive structure (Fig. 1A points to the device contact via structures 782 (first via portion), lower-level metal via structures 786 (second via portion), landing-pad-level metal line structures 788 (electrically conductive structure), and first dielectric material layers 764 (second interlayer dielectric material layer). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Huang et al. and Otsu, such that a second interlayer dielectric material layer is formed in order to provide a level of electrical isolation and/or physical stability.
Regarding claim 11, Otsu teaches wherein the electrically conductive structure has a topmost surface that is coplanar with a topmost surface of the second interlayer dielectric material layer (Fig. 1A points to the landing-pad-level metal line structures 788 (electrically conductive structure) and first dielectric material layers 764 (second interlayer dielectric material layer). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Huang et al. and Otsu, such that the electrically conductive structure has a topmost surface that is coplanar with a topmost surface of the second interlayer dielectric material layer in order to allow electrical access/communication while still providing a level of electrical isolation and/or physical stability.
Conclusion
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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