DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/13/2026 has been entered.
Response to Amendment
The amendment with respect to claim(s) 1, 13, and 19 filed on 6/28/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 2-12, 14-18, and 20 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 7-9, filed 02/05/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of KWON.
Regarding Claim 1. The Applicant argues (see Remarks, page 7) that none of the prior art disclose or suggest the amended features of Claim 1, now recites, “an image sensor comprising: wherein the intermediate substrate…,the first semiconductor layer being directly on the silicon oxide layer, the silicon oxide layer being directly on the second semiconductor layer pattern…” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of KWON teaches an image sensor (Fig. 7, 501), wherein the intermediate substrate (Fig. 6, stack of layers, 300/390/400) includes a stack of a first semiconductor layer (Fig. 5, 300, third semiconductor substrate), a silicon oxide layer (Fig. 6, 390, oxide layer), and a second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate), the first semiconductor layer (Fig. 6, 300) being directly on the silicon oxide layer (Fig. 6, 390), the silicon oxide layer (Fig. 6, 390) being directly on the second semiconductor layer pattern (Fig. 6, 400).
The Applicant argues (see Remarks, page 8) that the LEE prior art does not teach the claimed “second semiconductor layer pattern” of Claim 1. The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of KWON teaches an image sensor (Fig. 7, 501), wherein a sidewall (Fig. 6, 416, spacers) of the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate) defines a trench (Fig. 6, electrical connection via, [0042]) extending from a first end of the second semiconductor layer pattern (Fig. 6, 400) to a second end of the second semiconductor layer pattern (Fig. 6, 400).
Regarding Claim(s) 2-12, 14-19, and 20: The independent Claim(s) 13, and 19, and dependent claims 2-12, 14-18, and 20 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over KOHYAMA, MATSUGAI (prior art used in the previous Office Action filed on 12/05/2025), Doo Won Kwon, (hereinafter KWON), US 20170179181 A1, and LEE (prior art used in the previous Office Action filed on 12/05/2025).
Regarding Claim 1, KOHYAMA teaches an image sensor (Fig. 1, 1, imaging device), comprising:
a lower device (Fig. 4, 30, third substrate) on a lower substrate (Fig. 4, 31, semiconductor substrate), the lower device (Fig. 4, 30, third substrate) including a logic transistor (Fig. 4, 32, logic circuit);
an intermediate device (Fig. 4, 20, second substrate) on an intermediate substrate (Fig. 4, 21, semiconductor substrate) on the lower substrate (Fig. 4, 31, semiconductor substrate), the intermediate device (Fig. 4, 20, second substrate) including at least one transistor (Fig. 4, 22, readout circuit has for example reset transistor, RST, a selection transistor, SEL and an amplification transistor, AMP); and
an upper device (Fig. 4, 10, first substrate) on an upper substrate (Fig. 4, 11, semiconductor substrate) on the intermediate substrate (Fig. 4, 21, semiconductor substrate), the upper device (Fig. 4, 10, first substrate) including a photodiode (Fig. 4, 41, PD or photodiode) and a floating diffusion (Fig. 4, FD, Floating Diffusion) region,
wherein the lower substrate (Fig. 4, 31, semiconductor substrate), the intermediate substrate (Fig. 4, 21, semiconductor substrate) and the upper substrate (Fig. 4, 11, semiconductor substrate) are stacked (annotated Figure 4).
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KOHYAMA does not explicitly disclose an image sensor comprising: wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, wherein the first semiconductor layer includes one or more inner surfaces at least partially defining an opening in the first semiconductor layer, and an insulation pattern fills the opening, and wherein at least one sidewall surface of the second semiconductor layer pattern at least partially defines a trench extending through the second semiconductor layer pattern, and a buried insulation pattern fills the trench extending through the second semiconductor layer pattern.
MATSUGAI teaches an image sensor (Fig. 3, 79, state imaging device) comprising:
wherein the intermediate substrate (Fig. 3, 45, second semiconductor substrate) includes a stack of a first semiconductor layer (Fig. 3, 46, semiconductor well region), a silicon oxide layer (Fig. 3, 43a, first insulating layer is made of, for example, a silicon oxide), and a second semiconductor layer pattern (Fig. 3, 32, semiconductor well region),
wherein the first semiconductor layer (Fig. 3, 46, semiconductor well region) includes one or more inner surfaces (Fig. 3, 45B, second main surface) at least partially defining an opening (Fig. 3, 77, an opening) in the first semiconductor layer (Fig. 3, 46, semiconductor well region), and an insulation pattern fills the opening (Fig. 3, 52, insulating layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KOHYAMA to incorporate the teachings of MATSUGAI, such that an image sensor comprising: wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, wherein the first semiconductor layer includes one or more inner surfaces at least partially defining an opening in the first semiconductor layer, and an insulation pattern fills the opening, so that the said arrangement enables to manufacture a semiconductor device which are capable of improving the bonding accuracy in a configuration in which semiconductor substrates are bonded each other via a through-electrode, passing through the first semiconductor substrate and a wiring layer. (MATSUGAI, [0006], [0209]).
KOHYAMA as modified by MATSUGAI does not disclose an image sensor comprising:
wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, the first semiconductor layer being directly on the silicon oxide layer, the silicon oxide layer being directly on the second semiconductor layer pattern, wherein a sidewall of the second semiconductor layer pattern defines a trench extending from a first end of the second semiconductor layer pattern to a second end of the second semiconductor layer pattern.
KWON teaches an image sensor (Fig. 7, 501), wherein the intermediate substrate (annotated Figure 6) includes a stack of a first semiconductor layer (Fig. 5, 300, third semiconductor substrate), a silicon oxide layer (Fig. 6, 390, oxide layer), and a second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate), the first semiconductor layer (Fig. 6, 300, third semiconductor substrate) being directly on the silicon oxide layer (Fig. 6, 390, oxide layer), the silicon oxide layer (Fig. 6, 390, oxide layer) being directly on the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate),
wherein a sidewall (annotated Figure 6) of the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate) defines a trench (Fig. 6, electrical connection via, [0042]) extending from a first end (annotated Figure 6) of the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate) to a second end (annotated Figure 6) of the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KOHYAMA as modified by MATSUGAI to incorporate the teachings of KWON, such that an image sensor comprising:
wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, the first semiconductor layer being directly on the silicon oxide layer, the silicon oxide layer being directly on the second semiconductor layer pattern, wherein a sidewall of the second semiconductor layer pattern defines a trench extending from a first end of the second semiconductor layer pattern to a second end of the second semiconductor layer pattern. The above arrangement enables to realize an image sensor, circuits having different functions such as sensing, pixel array, logic etc. in which case, electrical connections are required to be provided between the circuits while being sufficiently insulated to be effective (KWON, [0006]).
Though KWON teaches the formation of trench or contact via in the second semiconductor layer pattern as mentioned above, the contact via fills with an electrode, 418, KOHYAMA as modified by MATSUGAI and KWON does not explicitly disclose that an image sensor comprising: wherein a buried insulation pattern fills the trench.
LEE teaches an image sensor (Fig. 5, [0009]) comprising:
wherein a buried insulation pattern (Fig. 50, SOG, Spin on Glass as insulators, https://ieeexplore.ieee.org/document/8006124, [0017], [0036]) fills the trench (Fig. 5, 45/35, upper/lower trench).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KOHYAMA as modified by MATSUGAI, and KWON to incorporate the teachings of LEE, such that an image sensor comprising: wherein a buried insulation pattern fills the trench, so that the incident light can be condensed to the photodiode, and further reduce the diffraction and scattering of light to enhance the photo sensitivity of the image sensor device (LEE, [0007], [0017]).
Regarding Claim 2, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 1.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein the buried insulation pattern (Fig. 3, the groove of 38/50, separation region/STI, [0108]) includes silicon oxide or silicon nitride (silicon oxide is buried in the groove of 38/50, separation region/STI, [0108]).
Regarding Claim 3, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 1.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein a first surface of the buried insulation pattern (Fig. 3, the groove of 38/50, separation region/STI, [0108]) at a bottom of the trench (Fig. 3, 38/50, separation region, STI, [0108]) contacts the silicon oxide layer (Fig. 3, 43a, first insulating layer, [0064]).
Regarding Claim 4, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 1.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein a surface of the second semiconductor layer pattern (Fig. 3, 32, semiconductor well region) and a surface of the buried insulation pattern (Fig. 3, silicon oxide is buried in the groove of 38/50, separation region/STI, [0108]) are coplanar with each other (annotated Figure 3).
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Regarding Claim 5, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 1.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein a gate of the transistor (Fig. 3, 36, gate electrode) is on an upper surface (Fig. 3, 31A, first main surface) of the second semiconductor layer pattern (Fig. 3, 32, semiconductor well region).
Regarding Claim 6, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 5.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), further comprising a first through silicon via (annotated Figure 3) electrically connected (Fig. 3, 55/41, multilayer wiring layer) to the transistor (Fig. 3, Tr6-Tr8) on the intermediate substrate (Fig. 3, 45, second semiconductor substrate),
wherein the first through silicon via (annotated Figure 3) extends through the buried insulation pattern (Fig. 3, silicon oxide is buried in the groove of 38/50, separation region/STI, [0108]), the silicon oxide layer (Fig. 3, 43a, first insulating layer is made of, for example, a silicon oxide), and the insulation pattern in the opening (Fig. 3, 52, insulating layer), and the first through silicon via (annotated Figure 3) extends to the floating diffusion region (Fig. 3, 33, the source/drain region equivalent to a floating diffusion, [0059]) of the upper substrate (Fig. 3, 31, first semiconductor substrate) from the intermediate substrate (Fig. 3, 45, second semiconductor substrate).
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Regarding Claim 7, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 5.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein the image sensor (Fig. 3, 79, state imaging device) includes a pixel array region (Fig. 3, 23) and a signal processing region (Fig. 3, 24-25, control circuit region and logic circuit region, annotated Figure 3), and the image sensor (Fig. 3, 79, state imaging device) includes a second through silicon via (annotated Figure 3) extending through the upper substrate (Fig. 3, 31, first semiconductor substrate) and the intermediate substrate (Fig. 3, 45, second semiconductor substrate), the second through silicon via (annotated Figure 3) located in the signal processing region (Fig. 3, 24-25, control circuit region and logic circuit region, annotated Figure 3).
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Regarding Claim 8, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 5.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), further comprising a contact plug (Fig. 3. 53/40/54/44, conductive layers/connection conductors) extending through the buried insulation pattern (Fig. 3, silicon oxide is buried in the groove of 38/50, separation region/STI, [0108]) and the silicon oxide layer (Fig. 3, 43a, first insulating layer is made of, for example, a silicon oxide) from the intermediate substrate (Fig. 3, 45, second semiconductor substrate) contacting a surface of the first semiconductor layer (Fig. 3, 46, semiconductor well region).
Regarding Claim 9, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 1.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device) of claim 1, wherein the second semiconductor layer pattern (Fig. 3, 32, semiconductor well region is within 31, first semiconductor substrate) has a thickness in a range of 0.3 µm to 1 µm ([0145]).
Regarding Claim 10, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 1.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein a gate of the transistor (Fig. 3, 48, gate electrode) is on an upper surface of the first semiconductor layer (Fig. 3, 46, semiconductor well region).
Regarding Claim 11, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 10.
KOHYAMA further teaches the image sensor (Fig. 1, 1, imaging device), further comprising:
a first insulating interlayer (Fig. 4, 61, interlayer insulating film) covering the intermediate device (Fig. 4, 20, second substrate);
a first bonding pad pattern (annotated Figure 4, 58, pad electrodes and 59, connection portion) in the first insulating interlayer (Fig. 4, 61, interlayer insulating film), an upper surface of the first bonding pad pattern (annotated Figure 4, 58, pad electrodes and 59, connection portion) exposed by a surface of the first insulating interlayer (Fig. 4, 61, interlayer insulating film);
a second insulating interlayer (Fig. 4, 52, insulating layer; part of 51, interlayer insulating layer) covering the upper device (Fig. 4, 10, first substrate); and
a second bonding pad pattern (annotated Figure 4, 58, pad electrodes and 59, connection portion, 54, wiring) in the second insulating interlayer (Fig. 4, 52, insulating layer; part of 51, interlayer insulating layer), an upper surface of the second bonding pad pattern (annotated Figure 4, 58, pad electrodes and 59, connection portion, 54, wiring) exposed by a surface of the second insulating interlayer (Fig. 4, 52, insulating layer; part of 51, interlayer insulating layer),
wherein the first bonding pad pattern (annotated Figure 4, 58, pad electrodes and 59, connection portion) and the second bonding pad pattern (annotated Figure 4, 58, pad electrodes and 59, connection portion, 54, wiring) are bonded to each other (annotated Figure 4).
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), further comprising:
a first insulating interlayer (Fig. 3, 49, an insulating interlayer) covering (annotated Figure 3) the intermediate device (Fig. 3, 45, second semiconductor substrate);
a first bonding pad pattern (Fig. 3, 53, conductor layers) in the first insulating interlayer (Fig. 3, 49, an insulating interlayer), an upper surface (annotated Figure 3) of the first bonding pad pattern (Fig. 3, 53, conductor layers) exposed by a surface of the first insulating interlayer (Fig. 3, 49, an insulating interlayer);
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a second insulating interlayer (Fig. 3, 39, insulating interlayer) covering (annotated Figure 3) the upper device (Fig. 3, 31, first semiconductor substrate); and
a second bonding pad pattern (Fig. 3, 40, conducting layers) in the second insulating interlayer (Fig. 3, 39, insulating interlayer), an upper surface (annotated Figure 3) of the second bonding pad pattern (Fig. 3, 40, conducting layers) exposed by a surface of the second insulating interlayer (Fig. 3, 39, insulating interlayer),
wherein the first bonding pad pattern (Fig. 3, 53, conductor layers) and the second bonding pad pattern (Fig. 3, 40, conducting layers are bonded to each other (Fig. 3, 15, bonding layer, [0100]).
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Regarding Claim 12, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 10.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein the image sensor (Fig. 3, 79, state imaging device) includes a pixel array region (Fig. 3, 23) and a signal processing region (Fig. 3, 24-25, control circuit region and logic circuit region, annotated Figure 3), and the image sensor (Fig. 3, 79, state imaging device) includes a second through silicon via (annotated Figure 3) extending through the upper substrate (Fig. 3, 31, first semiconductor substrate) and the intermediate substrate (Fig. 3, 45, second semiconductor substrate), the second through silicon via (annotated Figure 3) located in the signal processing region (Fig. 3, 24-25, control circuit region and logic circuit region, annotated Figure 3).
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Regarding Claim 13, KOHYAMA teaches an image sensor (Fig. 1, 1, imaging device), comprising:
a lower device (Fig. 4, 30, third substrate) on a lower substrate (Fig. 4, 31, semiconductor substrate), the lower device (Fig. 4, 30, third substrate) including a logic transistor (Fig. 4, 32, logic circuit);
a first insulating interlayer (Fig. 4, 61, interlayer insulating film) covering the lower device (Fig. 4, 30, third substrate);
an intermediate device (Fig. 4, 20, second substrate) on a first surface (annotated
Figure 4) of an intermediate substrate (Fig. 4, 21, semiconductor substrate) on the lower substrate (Fig. 4, 31, semiconductor substrate), the intermediate device (Fig. 4, 20, second substrate) including at least one transistor (Fig. 4, 22, readout circuit has for example reset transistor, RST, a selection transistor, SEL and an amplification transistor, AMP);
a second insulating interlayer (Fig. 4, 52, insulating layer; part of 51, interlayer insulating layer) covering the intermediate device (Fig. 4, 20, second substrate);
an upper device (Fig. 4, 10, first substrate) on an upper substrate (Fig. 4, 11, semiconductor substrate) on the intermediate substrate (Fig. 4, 21, semiconductor substrate), the upper device (Fig. 4, 10, first substrate) including a photodiode (Fig. 4, 41, PD or photodiode) and a floating diffusion region (Fig. 4, FD, Floating Diffusion); and
a third insulating interlayer (Fig. 4, 47, insulating layer; part of 51, interlayer insulating layer) covering the upper device (Fig. 4, 10, first substrate),
wherein a surface of the first insulating interlayer (Fig. 4, 61, interlayer insulating film) and a surface of the second insulating interlayer (Fig. 4, 52, insulating layer; part of 51, interlayer insulating layer) are bonded to each other (annotated Figure 4),
wherein a second surface (annotated Figure 4) opposite to the first surface of the intermediate substrate (Fig. 4, 21, semiconductor substrate) and a surface of the third insulating interlayer (Fig. 4, 47, insulating layer; part of 51, interlayer insulating layer) are bonded to each other (annotated Figure 4),
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KOHYAMA does not explicitly disclose an image sensor comprising: wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, wherein the first semiconductor layer includes one or more inner surfaces at least partially defining an opening in the first semiconductor layer, and an insulation pattern fills the opening, and wherein at least one sidewall surface of the second semiconductor layer pattern at least partially defines a trench extending through the second semiconductor layer pattern, and a buried insulation pattern fills the trench extending through the second semiconductor layer pattern.
MATSUGAI teaches an image sensor (Fig. 3, 79, state imaging device) comprising:
wherein the intermediate substrate (Fig. 3, 45, second semiconductor substrate) includes a stack of a first semiconductor layer (Fig. 3, 46, semiconductor well region), a silicon oxide layer (Fig. 3, 43a, first insulating layer is made of, for example, a silicon oxide), and a second semiconductor layer pattern (Fig. 3, 32, semiconductor well region),
wherein the first semiconductor layer (Fig. 3, 46, semiconductor well region) includes one or more inner surfaces (Fig. 3, 45B, second main surface) at least partially defining an opening (Fig. 3, 77, an opening) in the first semiconductor layer (Fig. 3, 46, semiconductor well region), and an insulation pattern fills the opening (Fig. 3, 52, insulating layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KOHYAMA to incorporate the teachings of MATSUGAI, such that an image sensor comprising: wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, wherein the first semiconductor layer includes one or more inner surfaces at least partially defining an opening in the first semiconductor layer, and an insulation pattern fills the opening, so that the said arrangement enables to manufacture a semiconductor device which are capable of improving the bonding accuracy in a configuration in which semiconductor substrates are bonded each other via a through-electrode, passing through the first semiconductor substrate and a wiring layer. (MATSUGAI, [0006], [0209]).
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KOHYAMA as modified by MATSUGAI does not disclose an image sensor comprising:
wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, the first semiconductor layer being directly on the silicon oxide layer, the silicon oxide layer being directly on the second semiconductor layer pattern, wherein a sidewall of the second semiconductor layer pattern defines a trench extending from a first end of the second semiconductor layer pattern to a second end of the second semiconductor layer pattern.
KWON teaches an image sensor (Fig. 7, 501), wherein the intermediate substrate (annotated Figure 6) includes a stack of a first semiconductor layer (Fig. 5, 300, third semiconductor substrate), a silicon oxide layer (Fig. 6, 390, oxide layer), and a second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate), the first semiconductor layer (Fig. 6, 300, third semiconductor substrate) being directly on the silicon oxide layer (Fig. 6, 390, oxide layer), the silicon oxide layer (Fig. 6, 390, oxide layer) being directly on the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate),
wherein a sidewall (annotated Figure 6) of the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate) defines a trench (Fig. 6, electrical connection via, [0042]) extending from a first end (annotated Figure 6) of the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate) to a second end (annotated Figure 6) of the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KOHYAMA as modified by MATSUGAI to incorporate the teachings of KWON, such that an image sensor comprising: wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, the first semiconductor layer being directly on the silicon oxide layer, the silicon oxide layer being directly on the second semiconductor layer pattern, wherein a sidewall of the second semiconductor layer pattern defines a trench extending from a first end of the second semiconductor layer pattern to a second end of the second semiconductor layer pattern. The above arrangement enables to realize an image sensor, circuits having different functions such as sensing, pixel array, logic etc. in which case, electrical connections are required to be provided between the circuits while being sufficiently insulated to be effective (KWON, [0006]).
Though KWON teaches the formation of trench or contact via in the second semiconductor layer pattern as mentioned above, the contact via fills with an electrode, 418, KOHYAMA as modified by MATSUGAI and KWON does not explicitly disclose that an image sensor comprising: wherein a buried insulation pattern fills the trench.
LEE teaches an image sensor (Fig. 5, [0009]) comprising:
wherein a buried insulation pattern (Fig. 50, SOG, Spin on Glass as insulators, https://ieeexplore.ieee.org/document/8006124, [0017], [0036]) fills the trench (Fig. 5, 45/35, upper/lower trench).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KOHYAMA as modified by MATSUGAI, and KWON to incorporate the teachings of LEE, such that an image sensor comprising: wherein a buried insulation pattern fills the trench, so that the incident light can be condensed to the photodiode, and further reduce the diffraction and scattering of light to enhance the photo sensitivity of the image sensor device (LEE, [0007], [0017]).
Regarding Claim 14, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 13.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein a first surface of the buried insulation pattern (Fig. 3, the groove of 38/50, separation region/STI, [0108]) at a bottom of the trench (Fig. 3, 38/50, separation region, STI, [0108]) contacts the silicon oxide layer (Fig. 3, 43a, first insulating layer, [0064]).
Regarding Claim 15, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 13.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein a gate of the transistor (Fig. 3, 48, gate electrode) is on an upper surface of the first semiconductor layer (Fig. 3, 46, semiconductor well region).
Regarding Claim 16, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 15.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein the first semiconductor layer (Fig. 3, 46, semiconductor well region) includes one or more inner surfaces (Fig. 3, 45B, second main surface) at least partially defining an opening (Fig. 3, 77, an opening) in the first semiconductor layer (Fig. 3, 46, semiconductor well region), and an insulation pattern fills the opening (Fig. 3, 52, insulating layer).
Regarding Claim 17 KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 16.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), further comprising a first through silicon via (annotated Figure 3) electrically connected (Fig. 3, 55/41, multilayer wiring layer) to the transistor (Fig. 3, Tr6-Tr8) on the intermediate substrate (Fig. 3, 45, second semiconductor substrate),
wherein the first through silicon via (annotated Figure 3) extends through the buried insulation pattern (Fig. 3, silicon oxide is buried in the groove of 38/50, separation region/STI, [0108]), the silicon oxide layer (Fig. 3, 43a, first insulating layer is made of, for example, a silicon oxide), and the insulation pattern in the opening (Fig. 3, 52, insulating layer), and the first through silicon via (annotated Figure 3) extends to the floating diffusion region (Fig. 3, 33, the source/drain region equivalent to a floating diffusion, [0059]) of the upper substrate (Fig. 3, 31, first semiconductor substrate) from the intermediate substrate (Fig. 3, 45, second semiconductor substrate).
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Regarding Claim 18, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 15.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein the image sensor (Fig. 3, 79, state imaging device) includes a pixel array region (Fig. 3, 23) and a signal processing region (Fig. 3, 24-25, control circuit region and logic circuit region, annotated Figure 3), and the image sensor (Fig. 3, 79, state imaging device) includes a second through silicon via (annotated Figure 3) extending through the upper substrate (Fig. 3, 31, first semiconductor substrate) and the intermediate substrate (Fig. 3, 45, second semiconductor substrate), the second through silicon via (annotated Figure 3) located in the signal processing region (Fig. 3, 24-25, control circuit region and logic circuit region, annotated Figure 3).
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Regarding Claim 19, KOHYAMA teaches an image sensor (Fig. 1, 1, imaging device), comprising:
a lower device (Fig. 4, 30, third substrate) on a lower substrate (Fig. 4, 31, semiconductor substrate), the lower device (Fig. 4, 30, third substrate) including a logic transistor (Fig. 4, 32, logic circuit);
a first insulating interlayer (Fig. 4, 61, interlayer insulating film) covering the lower device (Fig. 4, 30, third substrate);
an intermediate device (Fig. 4, 20, second substrate) on a first surface (annotated Figure 4) of an intermediate substrate (Fig. 4, 21, semiconductor substrate) on the lower substrate (Fig. 4, 31, semiconductor substrate), the intermediate device (Fig. 4, 20, second substrate) including at least one transistor (Fig. 4, 22, readout circuit has for example reset transistor, RST, a selection transistor, SEL and an amplification transistor, AMP);
a second insulating interlayer (Fig. 4, 52, insulating layer; part of 51, interlayer insulating layer) covering the intermediate device (Fig. 4, 20, second substrate);
a first bonding pad pattern (annotated Figure 4, 58, pad electrodes and 59, connection portion) in the second insulating interlayer (Fig. 4, 52, insulating layer; part of 51, interlayer insulating layer), an upper surface of the first bonding pad pattern (Fig. 4, 58, pad electrodes) exposed by a first surface of the second insulating interlayer (Fig. 4, 52, insulating layer; part of 51, interlayer insulating layer);
an upper device (Fig. 4, 10, first substrate) on an upper substrate (Fig. 4, 11, semiconductor substrate) on the intermediate substrate (Fig. 4, 21, semiconductor substrate), the upper device (Fig. 4, 10, first substrate) including a photodiode (Fig. 4, 41, PD or photodiode) and a floating diffusion region (Fig. 4, FD, Floating Diffusion); and
a third insulating interlayer (Fig. 4, 47, insulating layer; part of 51, interlayer insulating layer) covering the upper device (Fig. 4, 10, first substrate),
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a second bonding pad pattern (annotated Figure 4, 58, pad electrodes and 59, connection portion, 54, wiring) in the third insulating interlayer (Fig. 4, 47, insulating layer; part of 51, interlayer insulating layer), an upper surface of the second bonding pad pattern (annotated Figure 4, 58, pad electrodes and 59, connection portion 54, wiring) exposed by a first surface of the third insulating interlayer (Fig. 4, 47, insulating layer; part of 51, interlayer insulating layer),
wherein a surface of the first insulating interlayer (Fig. 4, 61, interlayer insulating film) and a surface of the second insulating interlayer (Fig. 4, 52, insulating layer; part of 51, interlayer insulating layer) are bonded to each other (annotated Figure 4), wherein the first bonding pad pattern and the second bonding pad pattern are bonded to each other,
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KOHYAMA does not explicitly disclose an image sensor comprising: wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, wherein the first semiconductor layer includes one or more inner surfaces at least partially defining an opening in the first semiconductor layer, and an insulation pattern fills the opening, and wherein at least one sidewall surface of the second semiconductor layer pattern at least partially defines a trench extending through the second semiconductor layer pattern, and a buried insulation pattern fills the trench extending through the second semiconductor layer pattern.
MATSUGAI teaches an image sensor (Fig. 3, 79, state imaging device) comprising:
wherein the intermediate substrate (Fig. 3, 45, second semiconductor substrate) includes a stack of a first semiconductor layer (Fig. 3, 46, semiconductor well region), a silicon oxide layer (Fig. 3, 43a, first insulating layer is made of, for example, a silicon oxide), and a second semiconductor layer pattern (Fig. 3, 32, semiconductor well region),
wherein the first semiconductor layer (Fig. 3, 46, semiconductor well region) includes one or more inner surfaces (Fig. 3, 45B, second main surface) at least partially defining an opening (Fig. 3, 77, an opening) in the first semiconductor layer (Fig. 3, 46, semiconductor well region), and an insulation pattern fills the opening (Fig. 3, 52, insulating layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KOHYAMA to incorporate the teachings of MATSUGAI, such that an image sensor comprising: wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, wherein the first semiconductor layer includes one or more inner surfaces at least partially defining an opening in the first semiconductor layer, and an insulation pattern fills the opening, so that the said arrangement enables to manufacture a semiconductor device which are capable of improving the bonding accuracy in a configuration in which semiconductor substrates are bonded each other via a through-electrode, passing through the first semiconductor substrate and a wiring layer. (MATSUGAI, [0006], [0209]).
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KOHYAMA as modified by MATSUGAI does not disclose an image sensor comprising:
wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, the first semiconductor layer being directly on the silicon oxide layer, the silicon oxide layer being directly on the second semiconductor layer pattern, wherein a sidewall of the second semiconductor layer pattern defines a trench extending from a first end of the second semiconductor layer pattern to a second end of the second semiconductor layer pattern.
KWON teaches an image sensor (Fig. 7, 501), wherein the intermediate substrate (annotated Figure 6) includes a stack of a first semiconductor layer (Fig. 5, 300, third semiconductor substrate), a silicon oxide layer (Fig. 6, 390, oxide layer), and a second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate), the first semiconductor layer (Fig. 6, 300, third semiconductor substrate) being directly on the silicon oxide layer (Fig. 6, 390, oxide layer), the silicon oxide layer (Fig. 6, 390, oxide layer) being directly on the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate),
wherein a sidewall (annotated Figure 6) of the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate) defines a trench (Fig. 6, electrical connection via, [0042]) extending from a first end (annotated Figure 6) of the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate) to a second end (annotated Figure 6) of the second semiconductor layer pattern (Fig. 6, 400, fourth semiconductor substrate).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KOHYAMA as modified by MATSUGAI to incorporate the teachings of KWON, such that an image sensor comprising:
wherein the intermediate substrate includes a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern, the first semiconductor layer being directly on the silicon oxide layer, the silicon oxide layer being directly on the second semiconductor layer pattern, wherein a sidewall of the second semiconductor layer pattern defines a trench extending from a first end of the second semiconductor layer pattern to a second end of the second semiconductor layer pattern. The above arrangement enables to realize an image sensor, circuits having different functions such as sensing, pixel array, logic etc. in which case, electrical connections are required to be provided between the circuits while being sufficiently insulated to be effective (KWON, [0006]).
Though KWON teaches the formation of trench or contact via in the second semiconductor layer pattern as mentioned above, the contact via fills with an electrode, 418, KOHYAMA as modified by MATSUGAI and KWON does not explicitly disclose that an image sensor comprising: wherein a buried insulation pattern fills the trench.
LEE teaches an image sensor (Fig. 5, [0009]) comprising:
wherein a buried insulation pattern (Fig. 50, SOG, Spin on Glass as insulators, https://ieeexplore.ieee.org/document/8006124, [0017], [0036]) fills the trench (Fig. 5, 45/35, upper/lower trench).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KOHYAMA as modified by MATSUGAI, and KWON to incorporate the teachings of LEE, such that an image sensor comprising: wherein a buried insulation pattern fills the trench, so that the incident light can be condensed to the photodiode, and further reduce the diffraction and scattering of light to enhance the photo sensitivity of the image sensor device (LEE, [0007], [0017]).
Regarding Claim 20, KOHYAMA as modified by MATSUGAI, KWON and LEE teaches the image sensor of claim 19.
MATSUGAI further teaches the image sensor (Fig. 3, 79, state imaging device), wherein a gate of the transistor (Fig. 3, 48, gate electrode) is on an upper surface of the first semiconductor layer (Fig. 3, 46, semiconductor well region).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20140042299 A1 – Figures 7
STATEMENT OF RELEVANCE – The chip or wafer layers wherein the oxide layer, 144 is disposed between the two semiconductor substrate and the substrate vias, 146 are connecting the above mentioned layers.
US 20150115131 A1 – Figures 5
STATEMENT OF RELEVANCE – The image sensor system, wherein the first device wafer comprising: semiconductor layer, 310, and second device wafer, 306 sandwiched with the oxide layer connected via interconnect layers, 312 and 316.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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