DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-6, 9-11, 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US Publication No. 2023/0163127) in view of Cheng et al (US Publication No. 2020/0294866).
PNG
media_image1.png
458
494
media_image1.png
Greyscale
Regarding claim 1, Wu discloses a multi-stack semiconductor device comprising: a lower nanosheet transistor comprising a plurality of lower channel layers Fig 15, 120/130 surrounded by a gate structure Fig 15; and an upper nanosheet transistor stacked on the lower nanosheet transistor Fig 15 and comprising a plurality of upper channel layers Fig 15, 150/160 surrounded by the gate structure Fig 15, wherein the lower channel layers have a smaller channel interval than the upper channel layers Fig 14 ¶0045 and 0050; a lower work-function metal layer Fig 15, 221 ¶0047-0048 formed on the lower channel layers; and a gate electrode pattern Fig 225/227/230 ¶0048-0050 configured to receive a gate input signal, wherein the lower work-function metal layer is formed between the lower channel layers Fig 15, 221 ¶0047-0048, and the gate electrode pattern Fig 225/227/230 ¶0048-0050 is not formed between the lower channel layers. Wu discloses all the limitations but silent on the arrangement of the layers. Whereas Cheng discloses wherein the gate structure Fig 10A-10B comprises: a lower work-function metal layer Fig 10A, 804 formed on the lower channel layers Fig 10A, 110 ;an upper work-function metal layer Fig 10A, 1002 formed on the upper channel layers and a gate electrode pattern Fig 10A, 1004 configured to receive a gate input signal, wherein the lower work-function metal layer Fig 10A, 804 is formed between the lower channel layers Fig 10A-10B, and the gate electrode pattern is not formed between the lower channel layers Fig 10B,wherein the upper work-function metal layer Fig 10A, 1002 and the gate electrode pattern are formed between the upper channel layers Fig 10B, and wherein the gate electrode pattern comprises at least one of tungsten (W), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon, and doped-polycrystalline silicon ¶0075. Wu and Cheng are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Wu and incorporate the teachings of Cheng to improve device performance ¶0003-0004.
Regarding claim 2, Wu discloses wherein each of the lower work function metal layer and the upper work function metal layer comprises titanium ¶0071-0072.
Regarding claim 4, Wu discloses a multi-stack semiconductor device comprising: a lower nanosheet transistor comprising a plurality of lower channel layers Fig 15, 120/130 surrounded by a gate structure Fig 15; and an upper nanosheet transistor stacked on the lower nanosheet transistor Fig 15 and comprising a plurality of upper channel layers Fig 15, 150/160 surrounded by the gate structure Fig 15, wherein the lower channel layers have a smaller channel interval than the upper channel layers Fig 14 ¶0045 and 0050; a lower work-function metal layer Fig 15, 221 ¶0047-0048 formed on the lower channel layers; and a gate electrode pattern Fig 225/227/230 ¶0048-0050 configured to receive a gate input signal, wherein the lower work-function metal layer is formed between the lower channel layers Fig 15, 221 ¶0047-0048, and the gate electrode pattern Fig 225/227/230 ¶0048-0050 is not formed between the lower channel layers. Wu discloses all the limitations but silent on the arrangement of the layers. Whereas Cheng discloses wherein the gate structure further comprises an upper work-function metal layer formed on the upper channel layers, wherein the upper work-function metal layer and the lower work-function metal layer are formed of different materials, respectively ¶0071, and wherein the upper work-function metal contacts a gate dielectric layer formed on side surfaces of the lower channel layers Fig 10A-10B. Wu and Cheng are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Wu and incorporate the teachings of Cheng to improve device performance ¶0003-0004.
Regarding claim 5, Cheng discloses wherein the upper work- function metal layer is further formed on side surfaces of the lower work-function metal layer formed between the lower channel layers Fig 10A-10B.
Regarding claim 6, Cheng discloses wherein the gate electrode pattern is formed between the upper channel layers Fig 10A-10B.
Regarding claim 9, Wu discloses wherein each of the lower channel layers and the upper channel layers has an equal thickness Fig 15.
Regarding claim 10, Wu discloses a multi-stack semiconductor device comprising: a lower nanosheet transistor Fig 15 comprising a plurality of lower channel layers Fig 15, 120/130 surrounded by a gate structure Fig 15; and an upper nanosheet transistor Fig 15 stacked on the lower nanosheet transistor and comprising a plurality of upper channel layers Fig 15, 150/160 surrounded by the gate structure, wherein the gate structure comprises a lower work-function metal layer Fig 15, 220 formed on the lower channel layers ¶0047-0048, an upper work-function metal layer formed on the upper channel layers Fig 15,221 ¶0047-0048, and a gate electrode pattern Fig 225/227/230 ¶0048-0050 formed on the upper work-function metal layer Fig 15, and wherein the gate electrode pattern Fig 225/227/230 ¶0048-0050 is not formed between the lower channel layers Fig 15. Wu discloses all the limitations but silent on the arrangement of the layers and material choice of the work function layers. Whereas Cheng discloses wherein the gate structure Fig 10A-10B comprises: a lower work-function metal layer Fig 10A, 804 formed on the lower channel layers Fig 10A, 110 ;an upper work-function metal layer Fig 10A, 1002 formed on the upper channel layers and a gate electrode pattern Fig 10A, 1004 configured to receive a gate input signal, wherein the lower work-function metal layer Fig 10A, 804 is formed between the lower channel layers Fig 10A-10B, and the gate electrode pattern is not formed between the lower channel layers Fig 10B,wherein the upper work-function metal layer Fig 10A, 1002 and the gate electrode pattern are formed between the upper channel layers Fig 10B, wherein the upper work-function metal layer and the lower work-function metal layer are formed of different materials, respectively ¶0071-0072. Wu and Cheng are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Wu and incorporate the teachings of Cheng to improve device performance ¶0003-0004 and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Regarding claim 11, Cheng discloses wherein the gate electrode pattern comprises at least one of tungsten (W), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon, and doped-polycrystalline silicon ¶0075. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Regarding claim 13, Wu discloses wherein the upper work-function metal layer is formed on side surfaces of the lower channel layers, and side surfaces of the lower work-function metal layer formed between the lower channel layers Fig 15.
Regarding claim 14, Wu discloses wherein each of the lower channel layers and the upper channel layers has an equal thickness Fig 15.
Regarding claim 15, Wu discloses wherein the lower channel layers have a smaller channel interval than the upper channel layers Fig 10-11.
Claims 3 and12 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US Publication No. 2023/0163127) and Cheng et al (US Publication No. 2020/0294866) in further view of Thomas et al (US Publication No. 2021/0408257).
Regarding claim 3, Wu discloses all the limitations but silent on the thickness. Whereas Thomas discloses wherein the gate structure further comprises an upper work-function metal layer formed on the upper channel layers, and wherein the upper work-function metal layer and the lower work-function metal layer have different thicknesses, respectively Fig 5E-5F. Wu and Thomas are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the transistor layers and incorporate the teachings of Thomas to improve device performance and control device threshold and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Regarding claim 12, Thomas wherein the upper work-function metal layer and the lower work-function metal layer have different thicknesses, respectively Fig 3A-3B, Fig 4K, Fig 5F.
Claims 7-8, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US Publication No. 2023/0163127) and Cheng et al (US Publication No. 2020/0294866) in further view of Hong et al (US Publication No. 2022/0109046).
Regarding claim 7, Wu discloses all the limitations but silent on the width. Whereas Hong discloses wherein the upper channel layers have a smaller width than the lower channel layers Fig 3C. Wu and Hong are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify channel width and incorporate the teachings of Hong to improve device performance ¶0007-0008.
Regarding claim 8, Hong discloses wherein a number of the upper channel layers is greater than a number of the lower channel layers Fig 3C.
Regarding claim 16, Hong discloses wherein the upper channel layers have a smaller width than the lower channel layers, and wherein a number of the upper channel layers is greater than a number of the lower channel layers Fig 3C.
Response to Arguments
Applicant’s arguments with respect to claims 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTINE A ENAD/ Primary Examiner, Art Unit 2811