Prosecution Insights
Last updated: April 19, 2026
Application No. 17/965,888

TESTING A SEMICONDUCTOR DIE USING TEMPORARY TEST PADS APPLIED TO CONDUCTIVE PADS OF THE SEMICONDUCTOR DIE

Final Rejection §103
Filed
Oct 14, 2022
Examiner
ADHIKARI DAWADI, BIPANA
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Micro Devices, Inc.
OA Round
2 (Final)
100%
Grant Probability
Favorable
3-4
OA Rounds
3y 9m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
3 granted / 3 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
39 currently pending
Career history
42
Total Applications
across all art units

Statute-Specific Performance

§103
52.4%
+12.4% vs TC avg
§102
12.7%
-27.3% vs TC avg
§112
31.9%
-8.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 3 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claims 1 and 21 have been fully considered but they are not persuasive. The examiner respectfully disagrees for at least the following reasons: Applicant argues Klein does not explicitly call the micro-bumps/traces a “temporary pad” and UBM 712 is not a conductive pad. The argument is not persuasive because Klein teaches forming temporary probing/interconnect structures for wafer test (e.g., micro-bumps and temporary metallization) and then removing those temporary metallized connections after testing. A temporary conductive contact structure used for probing/testing and then removed reasonably reads on “temporary pad” under broadest reasonable interpretation. Likewise, Klein’s UBM 712 is a conductive landing/metallization used to interface with micro-bumps and traces (i.e., a conductive contact/landing area), and thus reasonably reads on the recited “conductive pad”. Applicant’s arguments with respect to the amended independent claims 1 and 21 reciting "wherein the conductive pad is coupled to an active pad of the semiconductor die by a conductive via passing completely through a passivation layer covering the active pad" is not taught by Klein or other cited references have been considered but moot because the arguments do not apply to the newly combined references being used in the current rejection. In view of this amendment, the office has entered a new ground of rejection that is necessitated by Applicant’s amendment, by relying on Cheng to teach the newly emphasized “conductive via through passivation coupling an active pas to a conductive pad” feature, while continuing to rely on Klein for the temporary test contact and post-test removal. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 11, 21 and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Klein (US 10204841 B1) in view of Cheng (US 20050032353 A1). Re: Independent Claim 1 (Currently Amended), Klein discloses a method comprising: applying a temporary pad (Klein, Fig 7, Column 6, lines 36-38, micro-bumps 200 and/or trace 210/212) to a conductive pad of a semiconductor die (UBM 712 that serves as conductive landing) of a semiconductor die (IC die 100), wherein the conductive pad is coupled to an active pad of the semiconductor die (Klein, Fig 7, active pad as the die bond pad 710) by a via passing through a passivation layer covering the active pad (Klein, Fig 7, active pad 710 is covered by passivation layer 606 and the conductive pad 712 is coupled to active pad 710 via the opening on the passivation layer 606); after testing the semiconductor die, removing the temporary pad (Klein, Fig 11, step 1124; Column 9, lines 22-29; while Klein does not explicitly refer to the micro-bump/temporary traces as “temporary pad”, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to recognize that a temporary conductive contact structure used for probing and then removed after testing is a “temporary pad”). Klein is silent regarding the “via” being a conductive via and passing completely through the passivation layer. However, Cheng teaches forming conductive via passing completely through a passivation layer (Cheng, in Fig. 6d and ¶ [0040], teaches forming a via holes 22a/b/c completely through the passivation layer 18 and filling the vias with conductive material to electrically couple an underlying pad/contact region to an overlying conductive pad/contact pad). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Klein’s via-through-passivation coupling by implementing the via as a conductive via as taught by Cheng (i.e., a conductive filling via/plug through the passivation opening), in order to provide a robust electrical connection through the passivation layer between the active pad and the conductive pad. Re: Claim 2 (Original), Klein and Cheng disclose all the limitations of claim 1 on which this claim depends. Klein further discloses, wherein testing the semiconductor die comprises: coupling a probe to the temporary pad (Klein Column 6, lines 3-10, probe is coupled to micro-bumps 200 for testing); and executing one or more tests of the semiconductor die using the probe (Klein Column 2, lines 59-63 and column 5, lines 17-22, tests like measuring performance metrics of on-die circuitry are done prior to dicing). Re: Claim 3 (Original), Klein and Cheng disclose all the limitations of claim 2 on which this claim depends. Klein further discloses, wherein removing the temporary pad comprises: removing the temporary pad from the conductive pad after executing the one or more tests (Klein, Column 9, lines 21-25, after completion of wafer testing, metalized connections, i.e., the micro-bumps, temporary connection traces are removed at operation 1124). Re: Claim 11 (Original), Klein and Cheng disclose all the limitations of claim 1 on which this claim depends. Klein further discloses, wherein applying the temporary pad on the conductive pad comprises: applying a layer of metal to a top surface of the conductive pad (Klein, Fig. 7, column 7, lines 19-22, temporary pad e.g., temporary connection trace 210/212 is formed from an electrically conductive material, such as metal and deposited onto the conductive pad UBM 712). Re: Independent Claim 21 (Currently Amended), Klein discloses a method comprising: applying a temporary pad (Klein, Fig 7, Column 6, lines 36-38, temporary micro-bumps 200 and/or trace 210/212) to a conductive pad (UBM 712 that serves as conductive landing) of a semiconductor die (IC die 100); coupling a probe to the temporary pad (Klein, Column 6, lines 3-10, probe is coupled to micro-bumps 200 for testing; while Klein does not explicitly refer to the micro-bump/temporary traces as “temporary pad”, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to recognize that a temporary conductive contact structure used for probing and then removed after testing is a “temporary pad”); executing one or more tests of the semiconductor die using the probe (Klein, Column 2, lines 59-63 and column 5, lines 17-22, tests like measuring performance metrics of on-die circuitry are done prior to dicing); and after executing the one or more tests, removing the temporary pad from the conductive pad (Klein, Column 9, lines 21-25, after completion of wafer testing, metalized connections, i.e., the micro-bumps, temporary connection traces are removed at operation 1124). Klein is silent regarding the “via” being a conductive via and passing completely through the passivation layer. However, Cheng teaches forming conductive via passing completely through a passivation layer (Cheng, in Fig. 6d and ¶ [0040], teaches forming a via holes 22a/b/c completely through the passivation layer 18 and filling the vias with conductive material to electrically couple an underlying pad/contact region to an overlying conductive pad/contact pad). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Klein’s via-through-passivation coupling by implementing the via as a conductive via as taught by Cheng (i.e., a conductive filling via/plug through the passivation opening), in order to provide a robust electrical connection through the passivation layer between the active pad and the conductive pad. Re: Claim 28 (New), Klein and Cheng disclose all the limitations of claim 1 on which this claim depends. Klein further teaches wherein the conductive pad has a substantially planar top surface (Klein, Fig. 7, top surface portion of UBM 712 that serves as conductive landing is substantially planar in the opening section of passivation layer 606), and wherein the temporary pad completely covers the substantially planar top surface (Klein, Fig. 7, temporary pad 200 covers the top surface portion of UBM 712). Re: Claim 29 (New), Klein and Cheng disclose all the limitations of claim 21 on which this claim depends. Klein further teaches wherein the conductive pad has a substantially planar top surface (Klein, Fig. 7, top surface portion of UBM 712 that serves as conductive landing is substantially planar in the opening section of passivation layer 606), and wherein the temporary pad completely covers the substantially planar top surface (Klein, Fig. 7, temporary pad 200 covers the top surface portion of UBM 712). Claims 4 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Klein (US 10204841 B1) in view of Cheng (US 20050032353 A1) further in view of Chen (US 20210343667 A1). Re: Claim 4 (Original), Klein and Cheng disclose all the limitations of claim 1 on which this claim depends. Klein and Cheng are silent regarding, wherein removing the temporary pad comprises: grinding away the temporary pad to expose the conductive pad. However, Chen teaches wherein removing the temporary pad comprises: grinding away the temporary pad to expose the conductive pad (Chen, ¶ [0017], the solder bump may be removed by top die grinding after the chip probe is complete i.e., grinding away the temporary/probe bump to re-expose the underlying pad stack). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select a Chen's well known removal technique such as top-die grinding as a removal method in the process of Klein in view of Cheng in order to expose the conductive/bond pad after testing (Chen, ¶ [0017]). Re: Claim 22 (Previously Presented), Klein and Cheng disclose all the limitations of claim 21 on which this claim depends. Klein and Cheng are silent regarding, wherein removing the temporary pad comprises: grinding away the temporary pad to expose the conductive pad. However, Chen teaches wherein removing the temporary pad comprises: grinding away the temporary pad to expose the conductive pad (Chen, ¶ [0017], the solder bump may be removed by top die grinding after the chip probe is complete i.e., grinding away the temporary/probe bump to re-expose the underlying pad stack). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select a Chen's well known removal technique such as top-die grinding as a removal method in the process of Klein in view of Cheng in order to expose the conductive/bond pad after testing (Chen, ¶ [0017]). Claims 5 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Klein (US 10204841 B1) in view of Cheng (US 20050032353 A1) further in view of Zhang (US 20130072011 A1). Re: Claim 5 (Original), Klein and Cheng disclose all the limitations of claim 1 on which this claim depends. Klein and Cheng are silent regarding, wherein removing the temporary pad comprises: chemical-mechanical polishing away the temporary pad to expose the conductive pad. However, Zhang teaches wherein removing the temporary pad comprises: chemical-mechanical polishing away the temporary pad to expose the conductive pad (Zhang ¶ [0029], teaches chemical mechanical polishing (CMP) that removes top portion of the passivation layer. CMP is a process that applies chemical and mechanical forces to a surface to prepare a smooth surface and re-expose the pad surface). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select a Zhang's well known removal technique such as chemical-mechanical polishing as a removal method in the process of Klein in order to planarize and thus expose the conductive/bond pad after testing (Zhang, ¶ [0006]). Re: Claim 23 (Previously Presented), Klein and Cheng disclose all the limitations of claim 21 on which this claim depends. Klein and Cheng are silent regarding, wherein removing the temporary pad comprises: chemical-mechanical polishing away the temporary pad to expose the conductive pad. However, Zhang teaches wherein removing the temporary pad comprises: chemical-mechanical polishing away the temporary pad to expose the conductive pad (Zhang ¶ [0029], teaches chemical mechanical polishing (CMP) that removes top portion of the passivation layer. CMP is a process that applies chemical and mechanical forces to a surface to prepare a smooth surface and re-expose the pad surface). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select a Zhang's well known removal technique such as chemical-mechanical polishing as a removal method in the process of Klein in view of Cheng in order to planarize and thus expose the conductive/bond pad after testing (Zhang, ¶ [0006]). Claims 7, 12 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Klein (US 10204841 B1) in view of Cheng (US 20050032353 A1) further in view of Chang (US 20080157362 A1). Re: Claim 7 (Currently Amended), Klein and Cheng disclose all the limitations of claim 1 on which this claim depends. Klein and Cheng are silent regarding, further comprising: applying a bonding layer to a top surface of the passivation layer after removing the temporary pad, the bonding layer covering the conductive pad. However, Chang teaches further comprising: applying a bonding layer to a top surface of the passivation layer after removing the temporary pad, the bonding layer covering the conductive pad (Chang discloses in figure 2D, forming additional UMB/cap layer 8A deposited over existing UBM that spans the passivation opening i.e., applying a bonding layer on the passivation top surface that overlies/covers the underlying conductive landing). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Chang (adding a bonding cap/finish over UBM) to the method of Klein in view of Cheng (post-test removal of temporary bumps and traces 200/210/212) with UBM 712 on 606, coupled to 710) to apply a bonding layer on the passivation top that covers the conductive pad 712, in order to allow for better bonding and wetting of the solder material to the uppermost UBM layer i.e., bonding layer adjacent to the solder material, and for protection of the bonding pad by the lowermost UBM layer i.e. conductive pad (Chang, ¶ [0023]). Re: Claim 12 (Original), Klein and Cheng disclose all the limitations of claim 11 on which this claim depends. Klein is silent regarding, wherein applying the layer of metal to the top surface of the conductive pad comprises: electroplating the layer of metal to the top surface of the conductive pad. However, Chang teaches wherein applying the layer of metal to the top surface of the conductive pad comprises: electroplating the layer of metal to the top surface of the conductive pad (as explained above in claim 1, Klein (Fig 7) teaches forming temporary metal traces 210/212 used with micro bump 200 on the top surface of conductive pad UBM 712. Furthermore, Chang (Fig 2C, ¶ [0025]) teaches that UBM layers are deposited by conventional process such as electroplating). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Klein's flow of method to choose electroplating - a conventional wafer-level bump/UBM deposition method- as the specific plating technique taught by Chang in order to apply the temporary metal layer onto UBM 712 (Chang, ¶ [0025]). Re: Claim 25 (Currently Amended), Klein and Cheng disclose all the limitations of claim 21 on which this claim depends. Klein and Cheng are silent regarding, further comprising: applying a bonding layer to a top surface of the passivation layer after removing the temporary pad, the bonding layer covering the conductive pad. However, Chang teaches further comprising: applying a bonding layer to a top surface of the passivation layer after removing the temporary pad, the bonding layer covering the conductive pad (Chang discloses in figure 2D, forming additional UMB/cap layer 8A deposited over existing UBM that spans the passivation opening i.e., applying a bonding layer on the passivation top surface that overlies/covers the underlying conductive landing). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Chang (adding a bonding cap/finish over UBM) to the method of Klein in view of Cheng (post-test removal of temporary bumps and traces 200/210/212) with UBM 712 on 606, coupled to 710) to apply a bonding layer on the passivation top that covers the conductive pad 712, in order to allow for better bonding and wetting of the solder material to the uppermost UBM layer i.e., bonding layer adjacent to the solder material, and for protection of the bonding pad by the lowermost UBM layer i.e. conductive pad (Chang, ¶ [0023]). Claims 8-9 and 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Klein (US 10204841 B1) in view of Cheng (US 20050032353 A1) further in view of Chang (US 20080157362 A1) and further in view of Tu (US 8569886 B2). Re: Claim 8 (Original), Klein, Cheng and Chang disclose all the limitations of claim 7 on which this claim depends. Klein, Cheng and Chang are silent regarding, further comprising: applying a second passivation layer to a top surface of the bonding layer; and forming a second via in the second passivation layer, the second via traversing through the second passivation layer and having an end coupled to the conductive pad and an opposite end coupled to an external conductive pad. However, Tu teaches applying a second passivation layer to a top surface of the bonding layer; and forming a second via in the second passivation layer, the second via traversing through the second passivation layer and having an end coupled to the conductive pad and an opposite end coupled to an external conductive pad (Fig 3(b), Tu teaches forming a second passivation layer 54 over underlying metal, then creating an opening (second via) 65 through 54 to the underlying metal layer, and depositing an overlying metal pad (UBM/external pad) 73 across the top of 54 and the opening, optionally receiving solder ball 82). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tu with the method of Klein in view of Cheng and Chang by applying a second passivation layer 54 on the top surface of the bonding layer, then form a second via 65 so its lower end couples to conductive pad 712 (via the bonding layer) and its upper end couples to an external conductive pad 73, in order to reduce cracks by shifting solder-ball loading onto passivation layer (Tu, Column 4, lines 15-19). Re: Claim 9 (Original), Klein, Cheng, Chang and Tu disclose all the limitations of claim 8 on which this claim depends. Tu further teaches, further comprising: applying a solder bump to the external conductive pad (Tu, Fig. 3(b), solder bump 82 applied to the external conductive pad 73). Re: Claim 26 (Previously Presented), Klein, Cheng and Chang disclose all the limitations of claim 25 on which this claim depends. Klein, Cheng and Chang are silent regarding, further comprising: applying a second passivation layer to a top surface of the bonding layer; and forming a second via in the second passivation layer, the second via traversing through the second passivation layer and having an end coupled to the conductive pad and an opposite end coupled to an external conductive pad. However, Tu teaches applying a second passivation layer to a top surface of the bonding layer; and forming a second via in the second passivation layer, the second via traversing through the second passivation layer and having an end coupled to the conductive pad and an opposite end coupled to an external conductive pad (Fig 3(b), Tu teaches forming a second passivation layer 54 over underlying metal, then creating an opening (second via) 65 through 54 to the underlying metal layer, and depositing an overlying metal pad (UBM/external pad) 73 across the top of 54 and the opening, optionally receiving solder ball 82). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tu with the method of Klein in view of Cheng and Chang by applying a second passivation layer 54 on the top surface of the bonding layer, then form a second via 65 so its lower end couples to conductive pad 712 (via the bonding layer) and its upper end couples to an external conductive pad 73, in order to reduce cracks by shifting solder-ball loading onto passivation layer (Tu, Column 4, lines 15-19). Re: Claim 27 (Previously Presented), Klein, Cheng, Chang and Tu disclose all the limitations of claim 26 on which this claim depends. Tu further teaches, further comprising: applying a solder bump to the external conductive pad (Tu, Fig. 3(b), solder bump 82 applied to the external conductive pad 73). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Klein (US 10204841 B1) in view of Cheng (US 20050032353 A1) further in view of Lei (US 20120064712 A1) and further in view of Chen (US 20140077356 A1). Re: Claim 10 (Currently Amended), Klein and Cheng disclose all the limitations of claim 1 on which this claim depends. Klein and Cheng are silent regarding, further comprising: removing one or more portions of the conductive pad to leave a remaining portion of the conductive pad; applying a second passivation layer to a top surface of the conductive pad; and forming a second via in the second passivation layer, the second via traversing through the second passivation layer and having an end coupled to the remaining portion of the conductive pad and an opposite end coupled to an external conductive pad. However, Lei teaches removing one or more portions of the conductive pad to leave a remaining portion of the conductive pad (Lei, Fig 3-6, teaches etch back where, after formation of metal bump 50 through mask 46/opening 45, the uncovered seed layer 42B is etched away, then the exposed barrier layer 40 is removed, leaving UBM portion under the bump intact i.e. removing one or more portions of the conductive pad to leave a remaining portion); Klein, Cheng and Lei are silent regarding, applying a second passivation layer to a top surface of the conductive pad; and forming a second via in the second passivation layer, the second via traversing through the second passivation layer and having an end coupled to the remaining portion of the conductive pad and an opposite end coupled to an external conductive pad. However, Chen teaches applying a second passivation layer to a top surface of the conductive pad; and forming a second via in the second passivation layer, the second via traversing through the second passivation layer and having an end coupled to the remaining portion of the conductive pad and an opposite end coupled to an external conductive pad (Chen, Fig 4A, ¶ [0017], further teaches depositing a second polymer/passivation layer 48 over metal (PPI 44), patterning an opening (via) in 48, forming an overlying UBM 50 (external conductive pad) that extends into the opening to contact the under metal, and then forming a connector 52, which corresponds to applying a second passivation, forming a second via, and creating and external conductive pad). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine Lei's UBM trim/etch-back with Chen's polymer-over-metal via/pad build-up in the Klein's flow i.e., etch back portions of UBM 712 to leave a remainder, apply Chen's second passivation 48 over Klein's UBM 712, open a via to the remaining 712, and form Chen's external conductive pad 50 above in order to reduce the delamination between the PPI 44 and polymer layer caused by CTE mismatch during thermal cycling (Chen, ¶ [0028]). Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Klein (US 10204841 B1) in view of Cheng (US 20050032353 A1) further in view of Tu (US 8569886 B2). Re: Claim 13 (Original), Klein and Cheng disclose all the limitations of claim 1 on which this claim depends. Klein and Cheng are silent regarding, wherein applying the temporary pad on the conductive pad comprises: applying a layer of solder to a top surface of the conductive pad. However, Tu teaches wherein applying the temporary pad on the conductive pad comprises: applying a layer of solder to a top surface of the conductive pad (as explained above in claim 1, Klein (Fig 7) teaches forming temporary metal traces 210/212 used with micro bump 200 on the top surface of conductive pad UBM 712. Furthermore, Tu (Tu, Fig. 2-3) teaches applying solder to an over-passivation pad-e.g., forming UBM 73 over passivation 53 and then applying a solder bump 82 onto that pad). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select solder as the material for the temporary pad as taught in Tu in the Klein's flow to leverage well know solder properties like good wettability/ soft contact for probing. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BIPANA ADHIKARI DAWADI/ Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
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Prosecution Timeline

Oct 14, 2022
Application Filed
Sep 19, 2025
Non-Final Rejection — §103
Nov 03, 2025
Interview Requested
Nov 14, 2025
Examiner Interview Summary
Dec 18, 2025
Response Filed
Feb 14, 2026
Final Rejection — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
3y 9m
Median Time to Grant
Moderate
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