Response to Amendment
The amendment filed 12/29/2025 has been accepted and entered.
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive.
Applicant argues that Park does not disclose a connection pad 150 is located in the through hole, however, as can be seen in Park Figs. 1 and 3, from a top down view in Fig. 3, the through hole #150H occupies the same space as the first connection pad #150.
Additionally, applicant argues that etching is not performed on the first dielectric layer located in the first through hole. The argument is drawn to a product by process limitation, and is also not persuasive, see 103 rejection of claim 1 below, [E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." See MPEP 2113. The structure of Park in view of Zhan, specifically the dielectric material in Zhan is identical; there is a portion of dielectric 102 on a sidewall of the first contact pad 103 between the contact plug 31C and first contact pad 103 as shown in the annotated figures below.
Status of Claims
Claims 1-20 are pending.
Claims 8-20 withdrawn from consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5, 7, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0198552 A1 Park (herein “Park”) et al in view of CN 109148360 A Zhan (herein “Zhan”).
Regarding Claim 1, Park discloses:
A semiconductor device (see cross section of first embodiment shown in Fig. 1 unless otherwise specified. Other embodiments shown in Figs. 16-25), comprising:
a first wafer (comprises #51 and #57, see annotated Fig. 1 below, herein #1W);
a second wafer (comprises #21 and #27, see annotated Fig. 1 below, herein #2W); and
a contact plug (#200), wherein
the first wafer (#1W) comprises a first dielectric layer (#57) having a first connection pad (#150),
the second wafer (#2W) is bonded to the first wafer (#1W),
the second wafer (#2W) comprises a second dielectric layer (#27) having a second connection pad (#120),
the contact plug (#200) is made of a conductive material (see paragraph [0017]: “The via plug 200 may include a via conductive layer 270 and a core pattern 280.”) filled in a vertical through hole (Fig. 3, #150H), and the contact plug (#200) is configured to electrically connect the first connection pad (#150) and the second connection pad (#120);
the vertical through hole (#150H) is formed through etching, passes through the first wafer (#1W), and partially passes through the second wafer (#2W) to an upper surface (top surface) and/or a sidewall (right sidewall) of the second connection pad (#120); and
the first connection pad (#150) is located in the vertical through hole (#150, from a top down view in Fig. 3, the through hole #150H occupies the same space as the first connection pad #150), and etching is not performed on the first dielectric layer (#57, see Fig. 1, space below first connection pad does not contain the through hole) located below the first connection pad (#150).
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Park Fig. 1 – Annotated by Examiner
Park does not explicitly disclose:
in the vertical through hole, the first dielectric layer is reserved on the sidewall of the first connection pad.
However, in analogous art, Zhan teaches:
See Fig. 1, specifically Pad #103 and dielectric layer #102.
in the vertical through hole (hole not explicitly labelled, see space that interconnect layer #104 occupies), the first dielectric layer (#102) is reserved on the sidewall (right sidewall, see annotated Fig. 1 below) of the first connection pad (#103).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Zhan to the device disclosed by Park and include reserved dielectric material on the sidewall of the first conductive pad structure. Zhan teaches that etching is not performed on the first dielectric 102 below the first contact pad 103. Had such etching been performed, there would be some opening or any other indication of etching in the first dielectric 102 between the first contact pad 103 and 204. Furthermore, [E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." See MPEP 2113. The structure of Park in view of Zhan, specifically the dielectric material in Zhan is identical; there is a portion of dielectric 102 on a sidewall of the first contact pad 103 between the contact plug 31C and first contact pad 103 as shown in the annotated figure. Additionally, doing such a combination would provide etching protection to the pad, which in turn would improve the structure integrity of the first connection pad and further improve function integrity of the first connection pad.
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Zhan Fig. 1 – Annotated by Examiner
Regarding Claim 2, Park in view of Zhan discloses: The semiconductor device according to claim 1,
Park further discloses:
wherein the second connection pad (#120) is disposed opposite to the first connection pad (#150) in a vertical direction (with respect to the bonding surface/layers #61 and #31, the first connection pad #150 is disposed above the bonding layers, and on the opposite side, the second bonding pad #120 is disposed below the bonding layers.),
the sidewall (right sidewall) on at least one side of the second connection pad (#120) exceeds a sidewall (left sidewall) of the first connection pad (#150) in a horizontal direction (as interpreted by examiner, the right surface of the second connection pad is not vertically in line with the right surface of the first connection pad, which therefore implies that in a horizontal direction (with respect to the page), the right sidewall of the second connection pad exceeds the left sidewall of the first connection pad), and
the vertical through hole (#150H) exposes the upper surface (top surface) adjacent to the sidewall (right sidewall) on the at least one side of the second connection pad (#120), or the adjacent upper surface (top surface) and the sidewall (right sidewall) on the at least one side of the second connection pad (#120).
Regarding Claim 3, Park in view of Zhan discloses: The semiconductor device according to claim 1,
Park further discloses:
wherein the vertical through hole (#150H) exposes a sidewall (left sidewall) of the first connection pad (#150, see Fig. 1, through hole is directly adjacent to left sidewall).
Regarding Claim 5, Park in view of Zhan discloses: The semiconductor device according to claim 1,
Park further discloses:
wherein the second connection pad (#120) and the first connection pad (#150) are disposed in a staggered manner in a vertical direction (not located on the same plane with respect to the vertical direction), and
a size of a top opening of the vertical through hole (#150H, see annotated Fig. 1 above) is greater than or equal to a horizontal distance (the first (#150) and second (#120) connection pads vertically overlap as can be seen in Fig. 1, thus the horizontal distance between them is 0 since they overlap, therefore the width of the hole shown in annotated Fig. 1 above is greater than 0) between the second connection pad (#120) and the first connection pad (#150).
Regarding Claim 7, Park in view of Zhan discloses: The semiconductor device according to claim 1,
Park further discloses:
wherein the vertical through hole (#150H) passes through a direction (vertical or horizontal) of a sidewall (top or bottom) on a plurality of sides of the first connection pad (#150, top or bottom).
Note, as interpreted by the examiner, the phrase “passes through a direction of a sidewall on a plurality of sides” reads simply as “passes through a sidewall on a plurality of sides”. By passing through a sidewall on a plurality of sides, by definition the vertical hole must pass through multiple sides which therefore implies multiple directions. The top, bottom, and left surfaces of the first connection pad are considered by the examiner as sides of the connection pad, i.e. the top side, the bottom side, and the left side. Looking at the processing step shown in Figure 33 (in this case the through hole has been renumbered as #200H), the through hole passes through the first connection pad #150 and exposes the top surface, the bottom surface, and the left side surface. Therefore, Park discloses this limitation.
Regarding Claim 20 Park in view of Zhan discloses: The semiconductor device according to claim 1,
Zhan further teaches:
wherein no overlap region exists between the second connection pad and the first connection pad in a direction perpendicular to a bonding surface.
See annotated Zhan Fig. 1 above.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Zhan to the device disclosed by Park in view of Zhan and form the conductive pads such that there is no overlap region in a vertical direction with respect to the figure / perpendicular to a bonding surface. Doing so would be a simple substitution of the orientation or placement of the bonding pads to meet the needs of the device. Additionally, any orientation chosen would not change the mode of operation of the device, i.e. the placement/orientation of the conductive pads, see MPEP 2144.04 IV.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0198552 A1 Park et al in view of CN 109148360 A Zhan and further in view of US 2017/0040373 A1 Kim et al (herein “Kim”).
Regarding Claim 4, Park in view of Zhan discloses: The semiconductor device according to claim 1.
Park further discloses:
wherein the second connection pad (#120) is disposed opposite to the first connection pad (#150) in a vertical direction (with respect to the bonding surface/layers #61 and #31, the first connection pad #150 is disposed above the bonding layers, and on the opposite side, the second bonding pad #120 is disposed below the bonding layers.),
Park in view of Zhan does not explicitly disclose:
the sidewall on at least one side of the second connection pad is flush with a sidewall of the first connection pad, and
the vertical through hole exposes the sidewall on the at least one side of the second connection pad and the sidewall that is of the first connection pad and that is flush with the second connection pad.
However, in analogous art, Kim teaches:
See Fig. 3A.
the sidewall (left sidewall) on at least one side of the second connection pad (#334a) is flush with a sidewall (left sidewall) of the first connection pad (#144), and
the vertical through hole (#334H) exposes the sidewall (left sidewall) on the at least one side of the second connection pad (#334a) and the sidewall (left sidewall) that is of the first connection pad (#144) and that is flush with the second connection pad (#334a).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Kim to the device disclosed by Park in view of Zhan and form the through hole such that the sidewalls of the first and second pads are flush with one another. This would be a simple substitution of one method of forming the through hole for another that a person skilled in the art would do to obtain predictable results.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0198552 A1 Park et al in view of CN 109148360 A Zhan and further in view of US 2018/0068984 A1 Beyne e al (herein “Beyne”).
Regarding Claim 6, Park in view of Zhan discloses: The semiconductor device according to claim 1.
Park in view of Zhan does not explicitly disclose:
further comprising: a third wafer having, a third connection pad, wherein the third wafer is bonded to the first wafer implementing, an electrical connection between the third connection pad and the contact plug
However, in analogous art, Beyne teaches:
See Figs. 7B and 7C, and paragraphs [0080]-[0081].
further comprising: a third wafer (#20c) having, a third connection pad (#4c), wherein the third wafer (#20c) is bonded to the first wafer (#20a) implementing an electrical connection between the third connection pad (#4c) and the contact plug (see paragraph [0081]: “…These process steps are followed (not shown) by the deposition of a liner, removal of the liner from all horizontal surfaces, and deposition of an interconnection plug that interconnects the four levels.”).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Beyne to the device disclosed by Park in view of Zhan and include another wafer with another bonding pad to the semiconductor device. Doing so would expand the device allowing for more electrical connections and functionality.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812