DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
4. Claim(s) 11, 12, 15-18, is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi et al., US 2007/0085198 A1.
Claim 11. Shi et al., disclose an apparatus (such as the one in fig. 2a) comprising:
-a die (item 200) comprising an active device (item 210);
-one or more interconnects (item 225) coupled to the active device;
-and a passivation layer (item 240) disposed in areas between adjacent interconnects of the one or more interconnects;
-wherein the passivation layer includes one or more trenches (item 250), each trench of the one or more trenches respectively formed between at least two adjacent interconnects of the one or more interconnects, and longitudinally coextensive with the at least two adjacent interconnects of the one or more interconnects (this limitation would read through the structure of fig. 2a).
In the embodiment of FIG. 2a, Shi appears not to explicitly disclose the limitation of the one or more trenches being positioned inside bonding interfaces to form one or more channels.
However, in other embodiments (see the embodiment of FIG. 3E, [0036]) Shi discloses in FIG. 3E, substrates 300 and 330 may be aligned and bonded. Substrates 300 and 330 may be aligned and bonded by any suitable techniques. In an embodiment, substrates 300 and 330 may be aligned such that openings 320 and 340 are substantially aligned. In an embodiment, a number of openings 340 may align with openings 310 such that inputs and outputs for a micro-channel may be formed (such alignments are not shown in FIG. 3E for the sake of clarity). In an embodiment, substrates 300 and 330 may be bonded by diffusion bonding. In another embodiment, substrate 300 and 330 may include silicon and they may be bonded by silicon-to-silicon diffusion bonding. In other embodiments, substrates 300 and 330 may be bonded using an adhesive or epoxy.
To form microelectronics packaging, it would have been obvious to one of ordinary skill in the art at the time of invention to form microchannels during semiconductor substrate bonding primarily to provide a highly efficient, integrated thermal management solution, directly enabling superior heat dissipation and allowing for higher performance and reliability of electronic devices.
Claim 12. Shi et al., disclose the apparatus of claim 11, wherein the passivation layer comprises a silicon-based dielectric material (this limitation would read through [0021] item 240 is made of silicon).
Claim 15. Shi et al., disclose the apparatus of claim 11, wherein the one or more interconnects are configured to form an array of interconnects configured to be bonded via hybrid copper-to-copper bonding to another die or substrate (this limitation would read through the structure of figs 2a and 3i, wherein items 420, 390, 370 filled with copper and bonded together).
Claim 16. Shi et al., disclose the apparatus of claim 11, wherein the one or more interconnects comprises one or more of a conductive wire, trace, or pad (fig. 3I, item 380).
Claim 17. Shi et al., disclose the apparatus of claim 11, wherein the one or more trenches comprises a first set of trenches extending longitudinally in a first direction (this limitation would read through [0029] wherein Openings 310 may form a pattern that provides for a micro-channel that substantially extends or runs throughout substrate 300 or a portion of substrate 300).
Claim 18. Shi et al., disclose the apparatus of claim 17, wherein the one or more trenches comprises a second set of trenches extending longitudinally in a second direction different from the first direction, wherein the first set of trenches and second set of trenches together form a grid of trenches in the passivation layer (this limitation would read through [0029] wherein Openings 310 may form a pattern that provides for a micro-channel that substantially extends or runs throughout substrate 300 or a portion of substrate 300. For example, if substrate 300 is a chip or die, openings 310 may form a pattern that substantially extends throughout substrate 300. In another embodiment, if substrate 300 is a wafer, openings 310 may form patterns for several micro-channel layouts that each correspond to a die, such that the wafer may be aligned to a wafer (FIG. 3G) of integrated circuits to provide a micro-channel layout for each integrated circuit. In another embodiment, openings 310 may form a pattern that provides for multiple discrete micro-channels for a chip or die).
5. Claim(s) 13-14, is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi et al., US 2007/0085198 A1, in view FOUNTAIN, JR. et al., US 2020/0035641 A1.
Claims 13-14. Shi et al., disclose the apparatus of claim 11, above, but Shi appears to not specify wherein the one or more trenches is filled with a buffer material, wherein the buffer material is configured to be removed from the one or more trenches after the die has been bonded to another die or substrate.
[0063] of FOUNTAIN, JR. et al., disclose alternately, a light CMP with a slurry formulated for polishing a barrier layer (such as a barrier layer deposited into a cavity of an insulating layer 106 prior to copper deposition during a Damascene process, for example) can be used to selectively remove the oxidation 404.
It would have been within the skill of one of ordinary skill in the art before the effective filling date of the invention to form the one or more trenches filled with a buffer material, in order to manage interfaces between different material layers. The functions include improving interface quality, mitigating mechanical and thermal stresses, preventing contamination, and enabling better adhesion for fabrication processes.
Response to Arguments
Applicant's arguments filed 12/10/2025 have been fully considered but they are not persuasive.
Applicant presents claim 11, as amended, recites "the one or more trenches being positioned inside bonding interfaces to form one or more channels".
In response:
a) It is noted that fig. 3 of Shi’s reference clearly states in FIG. 3E, substrates 300 and 330 may be aligned and bonded. Substrates 300 and 330 may be aligned and bonded by any suitable techniques. Further, (items 320+340 correspond to the limitation of the one or more trenches being positioned inside bonding interfaces to form one or more channels). As noted, the structure of the device is substantially identical to that of the claimed structure which can function in the same manner, be labeled in the same manner, or be used in the same manner. MPEP 2112.01.
Thus, Examiner believe that the present claim language of the limitation claimed would not place the application in condition for allowance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899