DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/14/2022 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 14-16, and 20-21 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kinzer et al. (US Publication No. 2022/0102251).
Regarding claim 1, Kinzer discloses an apparatus comprising:
an insulating layer (320)
an electrically conductive layer (310) on the insulating layer (320), the conductive layer including a plurality of electrically isolated and conductive regions (Figure 3 and Figure 10A)
a first switch (1005) on a first of the conductive regions (1000), the first switch having a first terminal (1040) and a second terminal (1070) (Figure 10A)
a second switch (1015) on a second of the conductive regions (1035), the second switch having a third terminal (1055) and fourth terminal (1075) (Figure 10A)
a passive component (1020) having a fifth terminal and a sixth terminal (periphery terminals of 1020), wherein the first (1050) and third terminals (1055) are coupled to the first conductive region (1000), the fourth and sixth terminals are coupled to the second conductive region (1035), and the second and fifth terminals are coupled to a third of the conductive regions (Figure 10A)
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Regarding claim 14, Kinzer discloses a system comprising:
a substrate comprising: an insulating layer (320) having a planar surface; an electrically conductive layer (310) on the insulating layer (320), the conductive layer including a plurality of patterned conductive regions, which are electrically isolated from each other (Figure 3)
a power converter circuit comprising: a first switch (1005) disposed on a first of the conductive regions (1000), the first switch (1005) having first (1040) and second terminals (1070), a second switch (1015) disposed on a second of the conductive regions, the second switch having third (1055) and fourth terminals (1075), the second switch is coupled in series with the first switch between first and second voltage terminals
a passive component (1020) having fifth and sixth terminals (periphery terminals of 1020), the passive component is coupled in parallel with the first and second switches between the first and second voltage terminals, wherein: the first terminal (1050) and the third terminal (1055) are coupled to the first conductive region, the fourth terminal (1075), the sixth terminal and the second voltage are coupled to the second conductive region (1035), and the second terminal (1070), the fifth terminal and the first voltage terminal are coupled to a third of the conductive regions (Figure 10A)
Regarding claim 15, Kinzer discloses the power converter circuit has an output terminal coupled to the first conductive region (1000), the first switch (1005) has a first control terminal and the second switch (1015) has a second control terminal, the system further comprising: a power/control system having first and second control output terminals coupled to the first and second control terminals, respectively, the power/control system configured to control the first and second switches to provide a voltage at the output terminal of the power converter circuit (Figure 10B).
Regarding claim 16, Kinzer discloses the system is a system on chip (SOC) comprising the substrate, the power converter circuit and the power/control system (paragraph 102).
Regarding claim 20, Kinzer discloses a method comprising:
forming a first, second and third patterned conductive regions (1000/1005/1015) in a conductive layer (310) so the first conductive region surrounds the third conductive region and the conductive regions are electrically isolated from each other, the conductive layer being over an insulating substrate layer (320) (Figures 3 and 10A)
placing a first switch (1005) on the first conductive region, the first switch having first (1040) and second terminals (1020) and a first control terminal
placing a second switch (1015) on the second conductive region (1035), the second switch having third (1055) and fourth terminals (1075) and a second control terminal (1070)
placing a passive component (1020), having fifth and sixth terminals, on the conductive layer, the passive component having a body portion that extends as a jumper over a portion of a gap between the second and first conductive regions and over a portion of a gap between the first and third conductive regions, the fifth and sixth terminals being coupled to the second and third conductive regions, respectively (paragraph 87)
coupling the first terminal (1050) and the third terminal (1055) to the first conductive region (1000)
coupling the fourth terminal (1075) to the second conductive region (1070)
coupling the second terminal (1070) to the third conductive region (1055)
Regarding claim 21, Kinzer discloses the first switch, the second switch and the passive component are configured as a half-bridge (paragraph 86), the method further comprising packaging the device in a packaging material to provide an integrated system on chip (SOC) (paragraph 102).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-13 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al. (US Publication No. 2022/0102251) in view of Liu et al. (US Publication No. 2009/0174046).
Regarding claim 2, Kinzer discloses the limitations as discussed in the rejection of claim 1 above. Kinzer does not specifically disclose each of the conductive regions has a periphery, which is spaced from the periphery of at least one other of the conductive regions by a gap. However, Liu discloses conductive regions (256/240/356) separated from each other by a gap (encapsulation between 256, 240, and 356) (Figure 2). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the conductive regions of Kinzer to be separated by a gap, as taught by Liu, since they can provide isolated heat sinks for the groups of chips and mechanical support for the package (paragraph 45).
Regarding claim 3, Liu discloses the third conductive region (1025) is completely surrounded by the first conductive region (1000) and spaced apart therefrom by the respective gap between the first and third conductive regions.
Regarding claim 4, Kinzer discloses the passive component is a first passive component (1020), the apparatus comprising a second passive component (1030) coupled in parallel with the first passive component (1020) between the second (1035) and third conductive regions (1025).
Regarding claim 5, Kinzer discloses the first switch (1005) comprises a first field effect transistor (FET) implemented on a first die, which is mounted on the first conductive region, and the second switch (1015) comprises a second FET implemented on a second die, which is mounted on the second conductive region (paragraph 95), the first FET and the second FET configured as a half-bridge circuit (paragraph 86), in which the first FET is a high-side FET of the half-bridge circuit and the second FET is a low- side FET of the half-bridge circuit (Figure 10B), the first terminal is a drain of the high-side FET and the second terminal is a source of the high-side FET, whereby the third conductive region coupled to the high-side drain is surrounded by the first conductive region coupled to the high-side source (paragraphs 36-38; Figure 10A).
Regarding claim 6, Kinzer discloses the passive component is a decoupling capacitor having a body portion, which includes plates of the capacitor, in which the fifth and sixth terminals are coupled to the respective plates of the capacitor on opposing sides of the body portion, and the body portion extends as a jumper over a portion of the gap between the first and second conductive regions and over a portion of the gap between the first and third conductive regions (paragraph 87; Figure 10A).
Regarding claim 7, Kinzer discloses current flow between the first (1050) and third terminals (1055) travels along a path through the first conductive region (1035) having a direction transverse to a direction along which the body portion of the capacitor (1020/1030) extends (Figure 10A).
Regarding claim 8, Kinzer discloses a first wire coupled between the first terminal (1040) and the first conductive region (1045); a second wire coupled between the second terminal (1040) and the third conductive region (1035/1063); a third wire coupled between the third terminal (1055) and the first conductive region (1045); and a fourth wire coupled between the fourth terminal (1075) and the second conductive region (1035).
Regarding claim 9, Kinzer discloses the first and second wires bonds are parallel, and the third and fourth wires are parallel (Figure 10A).
Regarding claim 10, Kinzer discloses the first switch (1005) comprises a first transistor die, which is mounted on the first conductive region (1000), and second switch comprises a second transistor die mounted on the second conductive region (1035).
Regarding claim 11, Kinzer discloses the first transistor die comprises a first field effect transistor (FET) (1005), in which the first terminal is a drain (D) of the first FET (1005) and the second terminal (1050) is a source (S) of the first FET (1005), and the second transistor die comprises a second FET (1015), in which the third terminal (1055) is a drain (D) of the second FET (1015) and the fourth terminal (1075) is a source (S) of the second FET (1015).
Regarding claim 12, Kinzer discloses the first and second FETs are one of gallium nitride or silicon carbide FETs (paragraph 3).
Regarding claim 13, Kinzer discloses the conductive layer and the insulating layer form at least part of a direct bonded copper substrate, and the apparatus is a system on chip (SOC) (paragraph 102).
Regarding claim 17, Kinzer discloses the limitations as discussed in the rejection of claim 14 above. Kinzer does not specifically disclose each of the conductive regions has a periphery, which is spaced from the periphery of at least one other of the conductive regions by a gap. However, Liu discloses conductive regions (256/240/356) separated from each other by a gap (encapsulation between 256, 240, and 356) (Figure 2). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the conductive regions of Kinzer to be separated by a gap, as taught by Liu, since they can provide isolated heat sinks for the groups of chips and mechanical support for the package (paragraph 45).
Regarding claim 18, Kinzer discloses the first switch (1005) comprises a first field effect transistor (FET) implemented on a first die, which is mounted on the first conductive region, and the second switch (1015) comprises a second FET implemented on a second die, which is mounted on the second conductive region (paragraph 95), the first FET and the second FET configured as a half-bridge circuit (paragraph 86), in which the first FET is a high-side FET of the half-bridge circuit and the second FET is a low- side FET of the half-bridge circuit (Figure 10B), the first terminal is a drain of the high-side FET and the second terminal is a source of the high-side FET, whereby the third conductive region coupled to the high-side drain is surrounded by the first conductive region coupled to the high-side source (paragraphs 36-38; Figure 10A).
Regarding claim 19, Kinzer discloses the passive component is a first capacitor, the apparatus comprising a second capacitor coupled in parallel with the first capacitor between the second and third conductive regions, each of the first and second capacitors having a body portion that extends as a jumper over a portion of a gap between the second and first conductive regions and over a portion of the gap between the first and third conductive regions (paragraph 87; Figure 10A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Giandalia et al. (US Publication No. 2023/0006658) discloses chips on a conductive region separated by a gap from another conductive region (118).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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/N.R.P/ 1/20/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897