DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 12/09/2025 in response to the Office Action mailed on 09/18/2025 is
being acknowledged and entered into the record. The present Final rejection is made by taking into fully
consideration all the amendments.
Response to Arguments
Applicant’s arguments, see pages 7-8 of the remarks, filed on 12/09/2025, with respect to the rejections of Claims 1, 4-6 and 15-17 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejections of Claims 1, 4-6 and 15-17 have been withdrawn. However, upon further consideration, a new ground of 103 rejection is made in view of previously applied prior art reference of Yamashita and newly found prior art reference of Zhu. Zhu teaches the newly added limitations of Claim 1, as outlined in the rejection below.
On pages 9-12 of the remarks, filed on 12/09/2025, with respect to the 103 rejections of Claims 2, 3, 7-10, 12, 13,18 and 19, Applicant argues the prior art of record fails to teach or suggest "in a cross-section view, the first adhesive layer has a second sidewall and a part of the second sidewall connecting the semiconductor element is laterally inset relative to the first sidewall of the semiconductor element," as recited by amended claim 1. These arguments have been fully considered and are persuasive. Therefore, the rejections of Claims 2, 3, 7-10, 12, 13,18 and 19 have been withdrawn. However, upon further consideration, a new ground of 103 rejection is made in view of previously applied prior art references and newly found prior art reference of Zhu. Zhu teaches the newly added limitations of Claim 1, as outlined in the rejection below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21 recites the limitation “wherein the insulating layer comprises a part uncovered by the first adhesive layer”. However, neither the Figures nor the specification provides any support for this limitation. i.e., the insulating layer 106D is only shown in Fig. 3 and mentioned in paragraph 0231, but neither the specification nor the figures show the insulating layer 106D comprising a part uncovered by the first adhesive layer 102.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitations are limitations not explicitly disclosed in the primary
reference but disclosed in the secondary reference(s).
Claims 1, 4-6, 15-17 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (JP 2907195 B2), in view of Zhu (US 20180006083 A1).
Regarding Claim 1, Yamashita discloses a semiconductor element arrangement structure, comprising:
a carrier substrate 42 (see annotated Fig. 6g: 42, paragraph 0028 in English Translation of Yamashita);
a first adhesive layer 51_1 disposed on the carrier substrate 42 (see annotated Fig. 6g: 51, 51_1, 42, paragraph 0029 in English Translation of Yamashita);
and a semiconductor element 1_1 disposed on the first adhesive layer 51_1 (see annotated Fig. 6g: 1, 1_1, 51, 51_1, 42, paragraph 0019 in English Translation of Yamashita),
wherein, first semiconductor element 1_1 comprises a first electrode 2_1 at a side of the semiconductor element 1_1 and a first side wall (see annotated Fig. 6g: 2, 2_1, 1_1, paragraph 0007 in English Translation of Yamashita);
the first adhesive layer 51_1 is in direct contact with the first electrode 2_1 (see annotated Fig. 6g);
and in a cross-section view, the first adhesive laver has a second sidewall ( see annotated Fig. 6g) and a part of the second sidewall connecting the semiconductor element is laterally inset relative to the first sidewall of the semiconductor element.
Zhu et al. teaches a semiconductor element arrangement structure comprising the following limitation not disclosed in Yamashita:
in a cross-section view, a part of the second sidewall (of the first adhesive layer 212) connecting the semiconductor element 232A is laterally inset relative to the first sidewall of the semiconductor element 232A (Fig. 5: 232A, 212, paragraph 0069, 0070).
Therefore, it would have been obvious to a person of ordinary sill in the art before the effective
filing date of the claimed invention, to have combined the teachings of Yamashita and Zhu et al. in order to have a part of the second sidewall connecting the semiconductor element laterally inset relative to the first sidewall of the semiconductor element. Doing so would decrease the contact area of the adhesive layer with the substrate, thereby reducing the adhesive strength resulting in easy release of the semiconductor element when needed.
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[AltContent: textbox (Annotated Fig. 6g of Yamashita (JP 2907195 B2))]
Regarding Claim 4, Yamashita discloses the semiconductor element arrangement structure of claim 1, wherein the first adhesive layer 51_1 has a width gradually decreasing along a direction away from the carrier substrate 42 (see annotated Fig. 6g: 51_1, 42).
Regarding Claim 5, Yamashita discloses the semiconductor element arrangement structure of claim 1, wherein the first sidewall of the first adhesive layer 51_1 is curved in the cross-sectional view (see annotated Fig. 6g: 51_1).
Regarding Claim 6, Yamashita discloses the semiconductor element arrangement structure of claim 1, wherein the semiconductor element 1_1 comprises a first conductive bump 3_1 disposed on the first electrode 2_1, and the first conductive bump 3_1 has a curved profile (see annotated Fig. 6g: 3, 3_1, paragraph 0020).
Regarding Claim 15, Yamashita discloses the semiconductor element arrangement structure of claim 1, wherein, in the cross-sectional view, the first adhesive layer 51_1 comprises a third maximum width W3, and the semiconductor element 1_1 comprises a fourth maximum width W4, and the third maximum W3 width is different from the fourth maximum width W4 (see annotated Fig. 6g: W3, W4, 51_1, 1_1).
Regarding Claim 16, Yamashita discloses the semiconductor element arrangement structure of claim 15, wherein the third maximum W3 width is greater than the fourth maximum width W4 (see annotated Fig. 6g: W3, W4).
Regarding Claim 17, Yamashita discloses the semiconductor element arrangement structure of claim 15, wherein the third maximum width W3 is located at a bottommost surface of the first adhesive layer 51_1 (see annotated Fig. 6g: W3).
Regarding Claim 22, Yamashita discloses the semiconductor element arrangement structure of claim 6, wherein the curved profile of the first conductive bump 3_1 comprises a part which is closest to the carrier substrate 42, wherein the first adhesive layer 51_1 comprises a first portion between the first electrode 2_1 and the carrier substrate 42, and a second portion between the part and the carrier substrate 42, and wherein a thickness T1 of the first portion is greater than a thickness T2 of the second portion (see annotated Fig. 6g: T1, T2).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (JP 2907195 B2), in view of Zou (US 20190096859 A1), as applied to claim 1 above, further in view of Tsai et al. (US 20100203296 A1).
Regarding Claim 7, The combination of Yamashita and Zhu et al. fails to explicitly teach the semiconductor element arrangement structure of claim 1, further comprising a release layer disposed between the carrier substrate and the first adhesive layer.
However, Tsai et al. teaches a semiconductor element arrangement structure, comprising a release layer 202 disposed between the carrier substrate 200 and the first adhesive layer 206 (Fig. 2d: 202, 200, 206, paragraph 0020, 0021).
Therefore, a person of ordinary skill in the art would have combined the teachings of both Yamashita, Zhu et al. and Tsai et al. in order to have a release layer disposed between the carrier substrate and the first adhesive layer. By doing so, the release layer would allow the subsequently formed semiconductor elements to be easily separated from the carrier substrate, as recognized by Tsai et al. (paragraph 0020).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (JP 2907195 B2), in view of Zou (US 20190096859 A1), further in view of Tsai et al. (US 20100203296 A1), as applied to Claim 7 above, further in view of Liu et al. (US 20130071650 A1).
The combination of Yamashita, Zhu et al. and Tsai et al. fails to teach the semiconductor element arrangement structure of claim 7, wherein the release layer comprises an inorganic material.
However, Liu et al. teaches a semiconductor element arrangement structure comprising a release layer 102, wherein the release layer 102 comprises an inorganic material (Fig. 2D: 102, paragraph 0017).
Therefore, a person of ordinary skill in the art would have combined the teachings of Yamashita, Zhu et al., Tsai et al. and Liu et al. in order to have the release layer comprise an inorganic material. Doing so would enable the semiconductor element structure to withstand high-temperature processes such as annealing and laser lift-off, which is often challenging with organic release layers as they tend to decompose or outgas at relatively low temperatures.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (JP 2907195 B2), in view of Zou (US 20190096859 A1), as applied to claim 1 above, further in view of Fukui et al. (US 20200316908 A1) and Sakai et al. (US 20020048906 A1).
The combination of Yamashita and Zhu et al. fails to teach the semiconductor element arrangement structure of claim 1, further comprising an auxiliary adhesive layer located between the carrier substrate and the first adhesive layer and a base material layer located between the auxiliary adhesive layer and the first adhesive layer.
However, Fukui et al. teaches a semiconductor element arrangement structure comprising an auxiliary adhesive layer 4 located between the carrier substrate 1 and the first adhesive layer 2 Fig. 1: 1, 2, 3, paragraph 0019, 0020).
Note that the auxiliary adhesive layer 4 is made of a thermoplastic (see paragraph 0020), which is the same class of material disclosed by the Applicant for the auxiliary adhesive layer in the present disclosure (see paragraph 0018 of originally filed disclosure).
Therefore, a person of ordinary skill in the art would have combined the teachings of Yamashita, and Fukui et al. in order to have an auxiliary adhesive layer located between the carrier substrate and the first adhesive layer. Doing so would improve the physical strength of the semiconductor element structure and thereby improve the ease of handling with minimal damage, as recognized by Fukui et al. (paragraph 0015).
Furthermore, Sakai et al. teaches a semiconductor element arrangement structure comprising a base material layer 4 located between the carrier substrate 6 and the first adhesive layer 5 (Fig. 1D: 4, 5, 6, paragraph 0031, 0032).
Therefore, a person of ordinary skill in the art would have combined the teachings of Yamashita, and Sakai et al. in order to have a base material disposed in the semiconductor element structure of Yamashita. Doing so would enable the base material to serve as a reinforcing member that would protect the semiconductor elements from an external force and impact, as recognized by Sakai et al. (paragraph 0032).
Furthermore, a person of ordinary skill in the art would have recognized that the auxiliary adhesive layer of Fukui et al. and the base material layer of Sakai et al. can be disposed in the semiconductor element structure of Yamashita such that the base material layer of Sakai et al. is located between the auxiliary adhesive layer of Fukui et al. and the first adhesive layer of Yamashita.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (JP 2907195 B2), in view of Zou (US 20190096859 A1), further in view of Tsai et al. (US 20100203296 A1), as applied to Claim 9 above, further in view of Wakiyama et al. (US 20050189634 A1).
Regarding Claim 12, the combination of Yamashita, Zhu et al. and Tsai et al. teaches the semiconductor element arrangement structure of claim 9, further comprising a first included angle between a bottom and the second sidewall of the first adhesive layer 51_1 (as taught by Yamashita in annotated Fig. 6g: 51_1), and a second included angle between a bottom and a sidewall of the first release layer 202a (as taught by Tsai et al. in Fig. 2d: 202a).
But the combination fails to teach wherein the first included angle is different from the second included angle in the cross-sectional view.
However, Wakiyama et al. teaches a semiconductor element arrangement structure, comprising a first included angle between a bottom and a sidewall of the first adhesive layer 7 (Fig. 4: 7, paragraph 0044). Furthermore, the first included angle (which is less than 90 degrees according to Fig. 4 of Wakiyama et al.) is different from the second included angle (which is 90 degrees according Fig. 2d of Tsai et al.) in the cross-sectional view.
Therefore, a person of ordinary skill in the art would have combined the teachings of Yamashita, Tsai et al. and Wakiyama et al. in order to have a first included angle between a bottom and a sidewall of the first adhesive layer, and a second included angle between a bottom and a sidewall of the first release layer, wherein the first included angle is different from the second included angle in the cross-sectional view. Doing so would ensure the subsequently formed semiconductor elements are easily separated from the carrier substrate.
Regarding Claim 13, the combination of Tsai et al. and Wakiyama et al. teaches the semiconductor element arrangement structure of claim 12, wherein the second included angle (which is 90 degrees according Fig. 2d of Tsai et al.) is greater than the first included angle (which is less than 90 degrees according to Fig. 4 of Wakiyama et al.).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (JP 2907195 B2), in view of Zou (US 20190096859 A1), as applied to claim1 above, further in view of Wakiyama et al. (US 20050189634 A1).
Yamashita and Zhu et al. fail to teach the semiconductor element arrangement structure of claim 1, wherein the second sidewall of the first adhesive layer is tilted in the cross-sectional view.
However, Wakiyama et al. teaches a semiconductor element arrangement structure, wherein the second sidewall of first adhesive layer 7 is tilted in the cross-sectional view (Fig. 4: 7, paragraph 0044).
Therefore, a person of ordinary skill in the art would have combined the teachings of Yamashita and Wakiyama et al. in order to have the second sidewall of the first adhesive layer tilted in the cross-sectional view. Doing so would ensure ease of fabrication and process consistency as titled sidewalls require less complex patterning compared to curved sidewalls taught by Yamashita.
Claims 19 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (JP 2907195 B2), in view of Zou (US 20190096859 A1), as applied to Claim 1 above, further in view of second reference Liu et al. (US 20190131282 A1), herein referred to as Liu II.
Regarding Claim 19, Yamashita and Zhu et al. fail to teach the semiconductor element arrangement structure of claim 1, further comprising a void located between the semiconductor element and the first adhesive layer.
However, Liu II teaches a semiconductor element arrangement structure comprising a void located between the first semiconductor element 130b and the first adhesive layer 120 (see annotated Fig. 5: 130b, 120, 132a, 132b, paragraph 0040, 0051, 0061).
Therefore, a person of ordinary skill in the art would have combined the teachings of Yamashita and Liu II in order to have a void located between the first semiconductor element and the first adhesive layer. Doing so would electrically isolate the electrodes from each thereby preventing electrical shorting.
[AltContent: textbox (Annotated Fig. 5 of Liu II (US 20190131282 A1))]
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Regarding Claim 23, Yamashita teaches the semiconductor element arrangement structure of claim 1, wherein the semiconductor element 1_1 further comprises a second electrode 2_2 at the side of the semiconductor element 1_1, the first electrode 2_1 comprises a side surface facing the second electrode 2_2 (see annotated Fig. 6g: 2_1, 2_2, 1_1), but fails to explicitly teach the side surface of the first electrode 2_1 comprises a portion uncovered by the first adhesive layer 51_1.
However, Liu II teaches a semiconductor element arrangement structure, wherein the side surface of the first electrode 132a comprises a portion uncovered by the first adhesive layer 120 (see annotated Fig. 5: 130b, 120, 132a, 132b, paragraph 0040, 0051, 0061).
Therefore, a person of ordinary skill in the art would have combined the teachings of Yamashita and Liu II in order to have the side surface of the first electrode comprise a portion uncovered by the first adhesive layer. Doing so would ensure the exposed surfaces of the electrodes provide additional conductive area, thereby improving contact reliability.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (JP 2907195 B2), in view of Zou (US 20190096859 A1), as applied to Claim 1 above, further in view of Lin et al. (US 20210202794 A1).
Regarding Claim 21, the combination of Yamashita and Zhu et al. fails to teach the semiconductor element arrangement structure of claim 1, wherein the semiconductor element further comprises a semiconductor stack and an insulating layer formed between the semiconductor stack and the first electrode, and wherein the insulating layer comprises a part uncovered by the first adhesive layer.
However, Lin et al. teaches a semiconductor element arrangement structure, wherein the semiconductor element further comprises a semiconductor stack 12 and an insulating layer 50 formed between the semiconductor stack 12 and the first electrode 30, and wherein the insulating layer 50 comprises a part uncovered by the first adhesive layer 16 (Fig. 11: 12, 50, 30, 16, paragraph 0064).
Note that the side surface of the insulating layer 50 in Fig. 11 is uncovered by the adhesive layer 16.
Therefore, a person of ordinary skill in the art would have combined the teachings of Yamashita and Lin et al. in order have the semiconductor element further comprise a semiconductor stack and an insulating layer formed between the semiconductor stack and the first electrode, and wherein the insulating layer comprises a part uncovered by the first adhesive layer. Doing so would electrically isolate the semiconductor stack from the electrodes and the uncovered portion of the insulating layer would prevent the adhesive layer from climbing up the electrodes.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (JP 2907195 B2), in view of Zou (US 20190096859 A1), as applied to Claim 6 above, further in view of Ball (US 20020192936 A1).
Regarding Claim 24, the combination of Yamashita and Zhu et al. fails to teach the semiconductor element arrangement structure of claim 6, wherein the curved profile of the first conductive bump comprises a part which is closest to the carrier substrate, and the part directly contacts the first adhesive layer.
However, Ball teaches a semiconductor element arrangement structure, wherein the curved profile of the first conductive bump 16 comprises a part which is closest to the carrier substrate 71, and the part directly contacts the first adhesive layer 20 (Fig. 8C: 16, 71, 20, paragraph 0051).
Therefore, a person of ordinary skill in the art would have combined the teachings of Yamashita and Lin et al. in order to have the curved profile of the first conductive bump comprise a part which is closest to the carrier substrate, and the part directly contacting the first adhesive layer. Doing so would ensure the adhesive layer grips onto the anchoring area of the conductive bump rendered by its curved profile.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/
Examiner, Art Unit 2817
05/20/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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