Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner has considered the Applicant’s argument, but respectfully disagrees for the following reasons;
Applicant respectfully disagrees with the position and rationale set forth in the Office
Action.
Applicant argues that, The Examiner's Interpretation of “Cavity” Is Legally Improper Under the Broadest Reasonable interpretation Standard Under MPEP § 2111, the broadest reasonable interpretation (BRI) must be reasonable in light of the specification and the understanding of one of ordinary skill in the art, and cannot be the “broadest possible” interpretation. In re Suitco Surface, Inc., 603 F.3d 1255, 1260 (Fed. Cir. 2010); In re Smith Int’l, Inc., 871 F.3d 1375, 1382 (Fed. Cir. 2017). Applicant’s specification defines a cavity with clarity and consistency as a recess formed into a surface of a substrate that does not extend through the full thickness of the substrate, as depicted in Fig. 1B and accompanying text. This definition aligns with authoritative semiconductor packaging terminology: JEDEC JESD30E — “a recess or hollow in a package body or substrate,” IPC-7093 — “a recessed pocket within a substrate or interposer,” ASM Microelectronics Packaging Handbook — “recessed regions machined or etched into a substrate,” IEEE GlobalSpec — “a recess, pocket, or hollow area within a solid body.”
The Examiner has considered the Applicant’s argument, but respectfully disagrees for the following reasons;
The Examiner first would like state definition of a cavity; “a hole in a substrate can be considered a cavity, as a cavity is fundamentally defined as a hollow area or an unfilled space within a solid body”.
The Examiner takes the position that Bemanian consistently refers to specific areas of his claimed invention as cavities; paragraph 0118, fig. #16, item 1624, paragraph 0119, fig. #17, item 1724, paragraph 0120, fig. #18, item 1824. Furthermore, Bemanian shows in paragraph 0136, “ the mold(s) can contain cavity/cavities of any sizes/shapes”. Therefore, the Examiner takes the position that it is not the Examiner’s interpretation, but Bemanian’s definition and explicit examples that shows the unquestionable presents of cavities.
The Examiner takes the position that Bemanian consisting refers to various openings as cavities; figures, 16-19. It would appear that the Applicant is taking the position that Bemanian’s definition of a cavity is indeed incorrect. However, the Examiner takes the position that Bemanian is clear and correct with respect to the description of a cavity.
Applicant argues, II. Rebuttal to Examiner's Reliance on Bemanian paragraphs 90118-0120 and Figures 16-18 The Examiner relies on Bemanian’s Figures 16-18 (items 1624, 1724, and 1824) to assert that Bemanian discloses the claimed cavity. Applicant respectfully submits that this interpretation is incorrect for the reasons set forth below. A, Figure 16, item 1624 — Cavity in Substrate 1602, but Not the Claimed Cavity Applicant acknowledges that item 1624 is depicted as a cavity formed within substrate 1602 as described in Bemanian 0118. However, the cavity shown in Bemanian is structurally, geometrically, and functionally distinct from the recessed substrate cavity claimed by Applicant. Specifically: Item 1624 is configured for Bemanian’s substrate assembly and does not correspond to the structural arrangement required by Applicant’s claims. The Examiner fails to show that: “said first substrate including a first first-substrate cavity on the first surface of said first substrate, said second substrate includes a first second-substrate cavity on the first surface of said second substrate, said second surface of said first substrate and said second surface of said second substrate is located between said first surface of said first substrate and the first surface of said second substrate, and” B. Figure 17, item 1724 — Through-Hole, Not a Cavity Item 1724 is not a cavity under Applicant’s specification or under any JEDEC, IPC, ASM, or IEEE definition. Instead: Item 1724 extends fully through the structure in which it is formed, having no bottom surface. LJ It is not recessed into the substrate. LJ It is therefore a through-hole, not a cavity. Because a cavity must be a partial-depth recess, item 1724 cannot satisfy the claimed cavity limitation. C. Figure 18, tem 1824 — Also a Through-Hole, Not a Cavity The same analysis applies to item 1824 in Figure 18: LJ Item 1824 also passes completely through the structure. LJ It is not formed as a recess and does not retain substrate material beneath it. LJ It is likewise a through-hole, not a cavity. Accordingly, item 1824 fails to meet the definition of a cavity required by the claims. For at least these reasons, Applicant respectfully requests withdrawal of the rejection in view of the arguments presented herein.
The Examiner has considered the Applicant’s arguments, but respectfully disagrees for the following reasons;
The present claim description of the term ‘cavity’ within the present application fails to present any differences that would separate it from the definition of the cavity areas shown by Bemanian.
Furthermore, the Examiner takes the position that Bemanian shows different geometrically designed shapes as can be used with various examples for different implementations.
The also notes that the Applicant is arguing items that were not used in the Non-Final rejection and will not be used in the rejection that will be shown below; Figures, 17, 18.
For these reasons, the Examiner takes the position that the rejection issued on 11/18/2025 was proper and will be maintained in the rejection shown below in it’s entirety. Therefore the Examiner makes this rejection a Final Rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) #1, 2, 4-6, 29, 32, 34 is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by Bemanian et al., (U.S. Pub. No, 2012/0068229), hereinafter referred to as " Bemanian".
Bemanian shows, with respect to claim #1, an integrated circuit package comprising: one or more component(s) (fig. #19, item 1908, 1910) (paragraph 0121); and one or more substrate(s) (fig. #19, item 1942, 1902), wherein said one or more substrate(s) including a first substrate and a second substrate (fig. #19, item 1942, 1902), said first substrate including a first surface of said first substrate and a second surface of said first substrate (fig. #19, first substrate, item 1942, with first interior side surface/second surfaces) (paragraph 0121), said second substrate including a first surface of said second substrate and a second surface of said second substrate (fig. #19, second substrate with first interior side surface/second surface), said first substrate including a first first-substrate cavity on the first surface of said first substrate (fig. #19, first substrate, item 1942, with cavity on the first interior side surface of the first substrate of listed item), said second substrate includes a first second-substrate cavity on the first surface of said second substrate (fig. #19, second substrate, item 1902, with cavity on the first interior side surface of second substrate 1902), said second surface of said first substrate and said second surface of said second substrate is located between said first surface of said first substrate and the first surface of said second substrate (fig. #19, interior side surfaces from item 1902, 1942, present between top surface of 1942 and bottom surface of 1902) (paragraph 0121), and said one or more component(s) is/are disposed inside said first-substrate cavity of said first substrate and/or said first second-substrate cavity of said second substrate (fig. #19, item 1908, 1910, within cavity 1902) (paragraph 0121, 0204).
Bemanian shows, with respect to claim 2, an integrated circuit package wherein one of said one or more component(s) is electrically and/or optically coupled to said one or more substrate(s) using a flip chip or a wire bond method (Fig. #19, flip chip method utilized) (paragraph 0096-0098, 0154).
Bemanian shows, with respect to claim 4, an integrated circuit package wherein one of said one or more component(s) is a power management/regulator or power device or security sub-circuit or tamper detect circuit or router or switch or antenna or radar or phased array or modem or baseband or transceiver or mm-wave subsystem or silicon-on- insulator or amplifier or Field Programmable Gate Array (FPGA) or capacitor or resistor or inductor or processor or memory or sensor or analog- to-digital converter or digital-to-analog converter or electrical-optical converter or optical- electrical converter or Light Emitting Diode (LED) or micro LED or Application-Specific Integrated Circuit (ASIC) or Through- Silicon Via (TSV) or laser or analog circuit or digital circuit or Serializer/Deserializer (SerDes) or filter or Lens or Graphics Processing Unit (GPU) or magnet or waveguide or wire bond or epoxy mold compound (EMC) or under-fill material or heat-pipe or mirror or fan or bump or fiber or accelerator/co-processor or processor core or nanowire or Microelectromechanical Systems (MEMS) or membrane or heat spreader or energy source or sensing material or piezoelectric or light source or touch screen or display or Liquid Crystal Display (LCD) or organic light-emitting diode (OLED) or battery or Electromagnetic Shield (EMI) coating (fig. #14, paragraph 0008, 0119).
Bemanian shows, with respect to claim 5, an integrated circuit package wherein one of said one or more component(s) is/are stacked component(s) (Fig. 19, components including items 1938 and 1940 shows stacked configuration) (paragraph 0017, 0121).
Bemanian shows, with respect to claim 6, an integrated circuit package wherein one of said one or more substrate(s) is a semiconductor and/or glass (Fig. #19, paragraph 0145).
Bemanian shows, with respect to claim #29, an integrated circuit package wherein one of said substrate(s) comprise of a through hole (fig. #19, item 1936) (paragraph 0121).
Bemanian shows, with respect to claim 32, an integrated circuit package wherein said one or more component(s) is/are attached to both said first first-substrate cavity of said first substrate and said first second-substrate cavity of said second substrate (see Fig. 19, components 1908/1910 attached indirectly to cavities from substrates 1902/1942) (paragraph 0121).
Bemanian shows, with respect to claim 34, an integrated circuit package wherein said first first-substrate cavity of said first substrate and said first second-substrate cavity of said second substrate partially or fully overlap (Fig. 19, components including items 1938 and 1940 shows stacked configuration) (paragraph 0017, 0121).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) #3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bemanian et al., (U.S. Pub. No, 2012/0068229), hereinafter referred to as " Bemanian " as shown in the rejection of claim #1 above, and in view of Lipson et al., (U.S. Pub. No. 2014/0264400), hereinafter referred to as “Lipson”.
Bemanian substantially shows the claimed invention as shown in the rejection of claim #1 above.
Bemanian fails to show, with respect to claim #3, an integrated circuit package, wherein one of said one or more component(s) is electrically and/or optically coupled to said one or more substrate(s) using a flip chip or a wire bond method or a waveguide.
Lipson teaches, with respect to claim #3, an integrated circuit package, wherein one of said one or more component(s) (fig. #2c, item 210) (paragraph 0036) is electrically and/or optically coupled to said one or more substrate(s) using a flip chip or a wire bond method or a waveguide (paragraph 0038).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #3, to modified the invention of Bemanian as modified by the invention of Lipson, which teaches an integrated circuit package, wherein one of said one or more component(s) is electrically and/or optically coupled to said one or more substrate(s) using a flip chip or a wire bond method or a waveguide, to incorporate a structural condition that would increase the effective reception of pumped light and to produce one or more optical signals at optical wavelengths different from the pump light, as taught by Lipson.
//
Claim(s) #35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bemanian et al., (U.S. Pub. No, 2012/0068229), hereinafter referred to as " Bemanian " as shown in the rejection of claim #1 above, and in view of Shim et al., (U.S. Pat. No. 7,842,542), hereinafter referred to as “Shim”.
Bemanian substantially shows the claimed invention as shown in the rejection of claim #1 above.
Bemanian fails to show, with respect to claim #35, an integrated circuit package wherein any of said substrate(s) cavities are filled with light guiding materials.
Shim shows, with respect to claim 35, an integrated circuit package wherein any of said substrate(s) cavities are filled with light guiding materials (column #8, line 38-47).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #35, to modified the invention of Bemanian as modified by the invention of Shim, which teaches an integrated circuit package wherein any of said substrate(s) cavities are filled with light guiding materials, to incorporate a structural condition that would the increase the effective reception of pumped light and to produce one or more optical signals at optical wavelengths different from the pump light, as taught by Shim
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Allowable Subject Matter
Claims #21, 23-28, 30, 31, 33 and 36 are allowed.
The following is an examiner’s statement of reasons for allowance: While the prior art teaches am integrated circuit package comprising :one or more component(s); and one or more substrate(s), wherein said one or more substrate(s) including a first substrate, a second substrate, and a third substrate, said first substrate including a first surface of said first substrate and a second surface of said first substrate, said second substrate including a first surface of said second substrate and a second surface of said second substrate, said third substrate including a first surface of said third substrate and a second surface of said third substrate, said first substrate including a first first-substrate cavity on the first surface of said first substrate, said second substrate includes a first second-substrate cavity on the first surface of said second substrate, (Bemanian et al., 2012/0068229; Lipson et al., 2014/0264400l Kim et al., 2013/0075915; Senba et al., 6,188,127), it fails to teach either collectively or alone, with respect to claim #21, an integrated circuit package comprising third substrate includes a first third-substrate cavity on the first surface of said third substrate, said second surface of said first substrate and said second surface of said second substrate is located between said first surface of said first substrate and the first surface of said second substrate, said first surface of said second substrate and said first surface of said third substrate is located between said second surface of said second substrate and the said second surface of said third substrate, and said one or more component(s) is/are disposed inside said first-substrate cavity of said first substrate and/or said first second-substrate cavity of said second substrate and/or said first third-substrate cavity of said third substrate.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
01/12/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899