DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 06/11/2026 has been entered. Claims 1-14 and 31-36 are pending.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 06/11/2026, have been fully considered, regarding claims 1, 11 and 33, the amendment of “the first source layer lacks an intervening interface structure between the first part and the second part” are moot because do not apply to new ground of rejections with a reference of the record, US 20210043647 A1 to Kim, being used in the current rejection. Kim discloses a first source layer 200-SP1 lacks an intervening interface structure (there is not an interface structure between 200 and SP1, Fig. 3) between the first part 200 and the second part SP1, see detail below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-14 and 31-36 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim et al. (US 20210043647 A1, hereinafter Kim, of the record).
Re: Independent Claim 1, Kim teaches a semiconductor device (Fig. 3) comprising:
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Kim’s Figure 3-Annotated.
a first source layer (200-SP1 portion 200 and SP1 formed of a polycrystalline semiconductor material in [0032, 0033], Fig. 3) including a first part (200 in [0032], Fig. 3) having a first grain size (200 having a grain size GS2 in [0033]) and a second part (SP1 in [0033], Fig. 3) having a second grain size (SP1 having a grain size GS1 in [0033]) smaller (a grain size GS1 of the SP1 is smaller than a grain size of GS2 of 200 in [0033]) than the first grain size (200-GS2), wherein the first source layer (200-SP1) is a single layer (200-SP1 form a single layer because both are composed of polycrystalline semiconductor material in [0032, 0033]) and the first part (200) is in direct contact with the second part (SP1), and the first source layer (200-SP1) lacks an intervening interface structure (there is not an interface structure between 200 and SP1, Fig. 3) between the first part (200) and the second part (SP1);
a gate structure (210a, 210b, 210c, and 210d gate electrodes and the insulating patterns 220 in [0035], Fig. 3) on the first source layer (200-SP1); and
a channel structure (VC vertical channel portions VC, gap-fill layer 230, pad 240 and a charge storing structure CTS in [0040, 0041, 0051], Fig. 3) extending (Fig. 3) to the first part (200) of the first source layer (200-SP1) through the gate structure (210a, 210b, 210c, and 210d) and the second part (SP1) of the first source layer (200-SP1).
Regarding Claim 2, Kim discloses the semiconductor device of claim 1, further comprising: a second source layer (SP2-top a top portion of SP2 formed of a polycrystalline semiconductor material in [0034], Fig. 3-Annotated) located between (Fig. 3-Annotated) the first source layer (200-SP1) and the gate structure (210a, 210b, 210c, and 210d).
Regarding Claim 3, Kim discloses the semiconductor device of claim 2, wherein the second part (SP1) is located between (Fig. 3-Annotated) the first part (200) and the second source layer (SP2-top).
Regarding Claim 4, Kim discloses the semiconductor device of claim 2, wherein the second part (SP1) has a smaller grain size (a grain size of crystal grains GS3 of the SP2 is larger than the grain size of the crystal grains GS1 of the SP1 in [0034]) than the second source layer (SP2-top).
Regarding Claim 5, Kim discloses the semiconductor device of claim 2, further comprising: a third source layer (SP2-bottom a bottom portion of SP2 formed of a polycrystalline semiconductor material in [0034], Fig. 3-Annotated) located between (Fig. 3-Annotated) the first source layer (200-SP1) and the second source layer (SP2-top).
Regarding Claim 6, Kim discloses the semiconductor device of claim 5, wherein the second part (SP1) has a smaller grain size (a grain size of crystal grains GS3 of the SP2 is larger than the grain size of the crystal grains GS1 of the SP1 in [0034]) than the third source layer (SP2-bottom).
Regarding Claim 7, Kim discloses the semiconductor device of claim 5, wherein the second part (SP1) extends along an interface between (Fig. 3-Annotated) the first source layer (200-SP1) and the third source layer (SP2-bottom).
Regarding Claim 8, Kim discloses the semiconductor device of claim 1, further comprising: a source contact structure (CSP a common source pattern in [0044], Fig. 3) passing through (Fig. 3) the gate structure (210a, 210b, 210c, and 210d) and electrically connected to the first source layer (200-SP1).
Regarding Claim 9, Kim discloses the semiconductor device of claim 8, wherein the source contact structure (CSP) comprises: a contact plug (CSP-lower a lower portion of CSP connected to 200-SP1, Fig.3-Annotated) electrically connected to the first source layer (200-SP1); and an insulating spacer (SL a spacer having an insulating material between a common source pattern CSP and the stacks ST in [0044], Fig. 3) surrounding a sidewall (Fig. 3) of the contact plug (CSP-lower a lower portion of a common source pattern in [0044], Fig. 3-Annotated).
Regarding Claim 10, Kim discloses the semiconductor device of claim 9, wherein the contact plug (CSP-lower) and the second part (SP1) are separated by the insulating spacer (SL).
Regarding Independent Claim 11, Kim teaches a semiconductor device comprising:
a first source layer (200-SP1 portion 200 and SP1 formed of a polycrystalline semiconductor material in [0032, 0033], Fig. 3) including a first part (200 in [0032], Fig. 3) and a second part (SP1 in [0033], Fig. 3), wherein the second part (SP1) has a denser grain structure (a grain size GS1 of the SP1 is smaller than a grain size of GS2 of 200 in [0033], then, the part SP1 have a denser grain structure than 200) than the first part (200), the first source layer (200-SP1) is a single layer (200-SP1 form a single layer because both are composed of polycrystalline semiconductor material in [0032, 0033]) and the first part (200) is in direct contact with the second part (SP1), and the first source layer (200-SP1) lacks an intervening interface structure (there is not an interface structure between 200 and SP1, Fig. 3) between the first part (200) and the second part (SP1);
a gate structure (210a, 210b, 210c, and 210d gate electrodes and the insulating patterns 220 in [0035], Fig. 3) on the first source layer (200-SP1);
a second source layer (SP2-top a top portion of SP2 formed of a polycrystalline semiconductor material in [0034], Fig. 3-Annotated) located between (Fig. 3-Annotated) the first source layer (200-SP1) and the gate structure (210a, 210b, 210c, and 210d); and
a source contact structure (CSP a common source pattern in [0044], Fig. 3) extending (Fig. 3) to the first source layer (200-SP1) through the gate structure (210a, 210b, 210c, and 210d) and the second source layer (SP2-top),
wherein the second part (SP1) extends along an interface between (Fig. 3) the first source layer (200-SP1) and the second source layer (SP2-top).
Regarding Claim 12, Kim discloses the semiconductor device of claim 11, further comprising: a channel structure (vertical channel portions VC, gap-fill layer 230, pad 240 and a charge storing structure CTS in [0040, 0041, 0051], Fig. 3) passing through (Fig. 3) the gate structure (210a, 210b, 210c, and 210d), the second source layer (SP2-top), and the second part (SP1).
Regarding Claim 13, Kim discloses the semiconductor device of claim 11, wherein the second part (SP1) has a grain size smaller (a grain size GS1 of the SP1 is smaller than a grain size of GS2 of 200 in [0033]) than the first part (200).
Regarding Claim 14, Kim discloses the semiconductor device of claim 11, wherein the second part (SP1) has a grain boundary density larger (a grain size GS1 of the SP1 is smaller than a grain size of GS2 of 200 in [0033], then, the part SP1 have a denser grain structure than 200) than the first part (200).
Regarding Claim 31, Kim discloses the semiconductor device of claim 11, wherein the source contact structure (CSP) comprises: a contact plug (CSP-lower a lower portion of CSP connected to 200-SP1, Fig.3-Annotated) electrically connected to the first source layer (200-SP1); and an insulating spacer (SL a spacer having an insulating material between a common source pattern CSP and the stacks ST in [0044], Fig. 3) surrounding a sidewall (Fig. 3) of the contact plug (CSP-lower a lower portion of a common source pattern in [0044], Fig. 3-Annotated).
Regarding Claim 32, Kim discloses the semiconductor device of claim 31, wherein the contact plug (CSP-lower) and the second part (SP1) are separated by the insulating spacer (SL).
Regarding Independent Claim 33, Kim teaches a semiconductor device comprising:
a first source layer (200-SP1 portion 200 and SP1 formed of a polycrystalline semiconductor material in [0032, 0033], Fig. 3) including a first part (200 in [0032], Fig. 3) having a first grain size (200 having a grain size GS2 in [0033]) and a second part (SP1 in [0033], Fig. 3) having a second grain size (SP1 having a grain size GS1 in [0033]) smaller than the first grain size (200-GS2), wherein the first source layer (200-SP1) is a single layer (200-SP1 form a single layer because both are composed of polycrystalline semiconductor material in [0032, 0033]) and the first part (200) is in direct contact with the second part (SP1), and the first source layer (200-SP1) lacks an intervening interface structure (there is not an interface structure between 200 and SP1, Fig. 3) between the first part (200) and the second part (SP1);
a gate structure (210a, 210b, 210c, and 210d gate electrodes and the insulating patterns 220 in [0035], Fig. 3) on the first source layer (200-SP1);
a channel structure (VC vertical channel portions VC, gap-fill layer 230, pad 240 and a charge storing structure CTS in [0040, 0041, 0051], Fig. 3) extending (Fig. 3) to the first source layer (200-SP1) through the gate structure (210a, 210b, 210c, and 210d); and
a source contact structure (CSP a common source pattern in [0044], Fig. 3) extending (Fig. 3) to the first source layer (200-SP1) through the gate structure (210a, 210b, 210c, and 210d).
Regarding Claim 34, Kim discloses the discloses the semiconductor device of claim 33, further comprising: a second source layer (SP2-top a top portion of SP2 formed of a polycrystalline semiconductor material in [0034], Fig. 3-Annotated) located between (Fig. 3-Annotated) the first source layer (200-SP1) and the gate structure (210a, 210b, 210c, and 210d).
Regarding Claim 35, Kim discloses the discloses the semiconductor device of claim 34, wherein the second part (SP1) has a smaller grain size (a grain size of crystal grains GS3 of the SP2 is larger than the grain size of the crystal grains GS1 of the SP1 in [0034]) than the second source layer (SP2-top).
Regarding Claim 36, Kim discloses the discloses the semiconductor device of claim 34, wherein the second part (SP1) extends between (Fig. 3-Annotated) the first source layer (200-SP1) and the second source layer (SP2-top).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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