DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR
1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/12/2026 has been entered.
Response to Amendment
The Amendment filed on 01/13/2026 has been entered.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Final Reject" filed on 01/13/2026, have been fully considered, regarding claims 1, 11 and 33, the amendment of “the first source layer is a single layer” are moot because do not apply to new ground of rejections with new reference, US 20170103913 A1 to Dutartre, being used in the current rejection. Dutartre discloses a single layer including two parts (4-12 and 14) with different grain size, in direct contact ([0045], Fig. 4), see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-8, 11-14 and 33-36 are rejected under 35 U.S.C. 103 as being unpatentable over Kashima (US 20220285371 A1, hereinafter Kashima, of the record), in view of Dutartre et al. (US 20170103913 A1, hereinafter Dutartre).
PNG
media_image1.png
494
396
media_image1.png
Greyscale
Regarding Independent Claim 1, Kashima teaches a semiconductor device comprising:
Kashima’s Figure 4-Annotated.
a first source layer (211-212 portion 211 and 212 made of a semiconductor material in [0055], Fig. 4) including a first part (211 in [0055], Fig. 4) having a first grain size (211 having a first average crystal grain size of 300 nm in [0057]) and a second part (212 in [0055], Fig. 4) having a second grain size (212 having a second average crystal grain size of 100 nm in [0058]) smaller than the first grain size;
a gate structure (222-221 a gate structure formed by the pluralities of conductive layers 221 and insulation layers 220 in [0051], Fig. 4) on the first source layer (211-212); and
a channel structure (231-232-233-234-235 a block insulation films 231, a charge storage films 232, a tunnel insulation films 233, a semiconductor layers 234 and a core insulation layer 235 in [0051], Fig. 4) extending (Fig. 4) to the first part (211) of the first source layer (211-212) through the gate structure (222-221) and the second part (212) of the first source layer (211-212).
Kashima does not expressly disclose wherein the first source layer is a single layer and the first part is in direct contact with the second part.
PNG
media_image2.png
394
472
media_image2.png
Greyscale
Dutartre’s Figure 4-Annotated.
However, in the same semiconductor device field of endeavor, Dutartre discloses a single layer (4-12, 14 a polysilicon layer comprising a first portion 4 including a top region 12 exposed to oxygen and a second portion 14 in [0045], Fig. 4) and the first part (4-12 in [0045], Fig. 4) is in direct contact with the second part (14 in [0045], Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the Kashima’s first source layer as a single layer and the first part in direct contact with the second part by Dutartre’s device to improve the electrical parameters of the device ([0012], Dutartre).
Regarding Claim 2, Kashima modified by Dutartre discloses the semiconductor device of claim 1, further comprising: a second source layer (215 a semiconductor layer in [0062], Fig. 4, Kashima) located between (Fig. 4, Kashima) the first source layer (211-212, Kashima) and the gate structure (221, Kashima).
Regarding Claim 3, Kashima modified by Dutartre discloses the semiconductor device of claim 2, wherein the second part (212 Kashima) is located between (Fig. 4 Kashima) the first part (211 Kashima) and the second source layer (215 Kashima).
Regarding Claim 4, Kashima modified by Dutartre discloses the semiconductor device of claim 2, wherein the second part (212 Kashima) has a smaller grain size (212 having a grain size of 100 nm in [0058] and 215 having a fourth average crystal grain size of 300 nm in [0062], Fig. 4 Kashima) than the second source layer (215 Kashima).
Regarding Claim 5, Kashima modified by Dutartre discloses the semiconductor device of claim 2, further comprising: a third source layer (214 a semiconductor layer in [0060], Fig. 4 Kashima) located between (Fig. 4 Kashima) the first source layer (211-212 Kashima) and the second source layer (215 Kashima).
Regarding Claim 6, Kashima modified by Dutartre discloses the semiconductor device of claim 5, wherein the second part (212 Kashima) has a smaller grain size (212 having a grain size of 100 nm in [0058] and 214 having a grain size of 150 nm in [0060], Fig. 4 Kashima) than the third source layer (214 Kashima).
Regarding Claim 7, Kashima modified by Dutartre discloses the semiconductor device of claim 5, wherein the second part (212 Kashima) extends along an interface between (Fig. 4 Kashima) the first source layer (211-212 Kashima) and the third source layer (214 Kashima).
Regarding Claim 8, Kashima modified by Dutartre discloses the semiconductor device of claim 1, further comprising: a source contact structure (241 a conductive layer as a contact layer in [0077], Fig. 4 Kashima) passing through (Fig. 4 Kashima) the gate structure (221 Kashima) and electrically connected to the first source layer (211-212 Kashima).
Regarding Independent Claim 11, Kashima teaches a semiconductor device comprising:
a first source layer (211-212 a semiconductor layer 211 and a semiconductor layer 212 in [0055], Fig. 4) including a first part (211 in [0055], Fig. 4) and a second part (212 in [0055], Fig. 4), wherein the second part (212) has a denser grain structure (212 having a second average crystal grain size of 100 nm in [0058] in comparation with 211 having a first average crystal grain size of 300 nm in [0057], then, the part 212 have a denser grain structure than 211) than the first part (211);
a gate structure (222-221 a gate structure formed by the pluralities of conductive layers 221 and insulation layers 220 in [0051], Fig. 4) on the first source layer (211-212);
a second source layer (215 a semiconductor layer in [0062], Fig. 4) located between (Fig. 4) the first source layer (211-212) and the gate structure (222-221); and
a source contact structure (241 a conductive layer as a contact layer in [0077], Fig. 4) extending (Fig. 4) to the first source layer (211-212) through the gate structure (222-221) and the second source layer (215),
wherein the second part (212) extends along an interface between (Fig. 4) the first source layer (211-212) and the second source layer (215).
Kashima does not expressly disclose the first source layer is a single layer, wherein the first part is in direct contact with the second part.
However, in the same semiconductor device field of endeavor, Dutartre discloses a single layer (4-12, 14 a polysilicon layer comprising a first portion 4 including a top region 12 exposed to oxygen and a second portion 14 in [0045], Fig. 4) wherein the first part (4-12 in [0045], Fig. 4) is in direct contact with the second part (14 in [0045], Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the Kashima’s first source layer as a single layer wherein the first part in direct contact with the second part by Dutartre’s device to improve the electrical parameters of the device ([0012], Dutartre).
Regarding Claim 12, Kashima modified by Dutartre discloses the semiconductor device of claim 11, further comprising: a channel structure (231-232-233-234-235 a block insulation films 231, a charge storage films 232, a tunnel insulation films 233, a semiconductor layers 234 and a core insulation layer 235 in [0051], Fig. 4 Kashima) passing through (Fig. 4 Kashima) the gate structure (221 Kashima), the second source layer (215 Kashima), and the second part (212 Kashima).
Regarding Claim 13, Kashima modified by Dutartre discloses the semiconductor device of claim 11, wherein the second part (212 Kashima) has a grain size smaller (212 having a grain size of 100 nm in [0058] in comparation with 211 having a grain size of 300 nm in [0057] Kashima) than the first part (211 Kashima).
Regarding Claim 14, Kashima modified by Dutartre discloses the semiconductor device of claim 11, wherein the second part (212 Kashima) has a grain boundary density larger (212 having a grain size of 100 nm in [0058] in comparation with 211 having a grain size of 300 nm in [0057], then, the part 212 have a denser grain structure than 211 Kashima) than the first part (211 Kashima).
Regarding Independent Claim 33, Kashima teaches a semiconductor device comprising:
a first source layer (211-212 a semiconductor layer 211 and a semiconductor layer 212 in [0055], Fig. 4) including a first part (211 in [0055], Fig. 4) having a first grain size (211 having a first average crystal grain size of 300 nm in [0057]) and a second part (212 in [0055], Fig. 4) having a second grain size (212 having a second average crystal grain size of 100 nm in [0058]) smaller than the first grain size;
a gate structure (221 a gate structure formed by the pluralities of conductive layers 221 and insulation layers 222 in [0051], Fig. 4) on the first source layer (211-212); and
a channel structure (231-232-233-234-235 a block insulation films 231, a charge storage films 232, a tunnel insulation films 233, a semiconductor layers 234 and a core insulation layer 235 in [0051], Fig. 4) extending (Fig. 4) to the first part (211) of the first source layer (211-212) through the gate structure (221) and the second part (212) of the first source layer (211-212); and
a source contact structure (241 a conductive layer as a contact layer in [0077], Fig. 4) extending (Fig. 4) to the first source layer (211-212) through the gate structure (222-221).
Kashima does not expressly disclose wherein the first source layer is a single layer and the first part is in direct contact with the second part.
However, in the same semiconductor device field of endeavor, Dutartre discloses a single layer (4-12, 14 a polysilicon layer comprising a first portion 4 including a top region 12 exposed to oxygen and a second portion 14 in [0045], Fig. 4) and the first part (4-12 in [0045], Fig. 4) is in direct contact with the second part (14 in [0045], Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the Kashima’s first source layer as a single layer and the first part in direct contact with the second part by Dutartre’s device to improve the electrical parameters of the device ([0012], Dutartre).
Regarding Claim 34, Kashima modified by Dutartre discloses the semiconductor device of claim 33, further comprising: a second source layer (215 a semiconductor layer in [0062], Fig. 4, Kashima) located between (Fig. 4, Kashima) the first source layer (211-212, Kashima) and the gate structure (221, Kashima).
Regarding Claim 35, Kashima modified by Dutartre discloses the semiconductor device of claim 34, wherein the second part (212 Kashima) has a smaller grain size (212 having a grain size of 100 nm in [0058] and 215 having a fourth average crystal grain size of 300 nm in [0062], Fig. 4 Kashima) than the second source layer (215 Kashima).
Regarding Claim 36, Kashima modified by Dutartre discloses the semiconductor device of claim 33, wherein the second part (212 Kashima) extends between (Fig. 4 Kashima) the first source layer (211-212, Kashima) and the second source layer (215 Kashima).
Claims 9-10 and 31-32 are rejected under 35 U.S.C. 103 as being unpatentable over Kashima, in view of Dutartre and further in view of Kim et al. (US 20210043647 A1, hereinafter Kim, of the record).
Regarding Claim 9, Kashima modified by Dutartre discloses the semiconductor device of claim 8, wherein the source contact structure (241 Kashima) comprises: a contact plug (241-lower a lower portion of 241 connected to 211-212, Fig.4-Annotated Kashima) electrically connected to the first source layer (211-212 Kashima);
Kashima modified by Dutartre does not expressly disclose an insulating spacer surrounding a sidewall of the contact plug.
However, in the same semiconductor device field of endeavor, Kim discloses an insulating spacer (SL a spacer having an insulating material between a common source pattern CSP and the stacks ST in [0044], Fig. 3) surrounding a sidewall (Fig. 3) of the contact plug (CSP-lower a lower portion of a common source pattern in [0044], Fig. 3-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kim’s feature of an insulating spacer surrounding a sidewall of the contact plug to the combination of Kashima and Dutartre to isolate the common source pattern from the gate stack ([0044], Kim).
Regarding Claim 10, Kashima modified by Dutartre and Kim discloses the semiconductor device of claim 9, wherein the contact plug (241-lower, Kashima) and the second part (212, Kashima) are separated by the insulating spacer (SL, Kim).
Regarding Claim 31, Kashima modified by Dutartre discloses the semiconductor device of claim 11, wherein the source contact structure (241 Kashima) comprises: a contact plug (241-lower a lower portion of 241 connected to 211-212, Fig.4-Annotated Kashima) electrically connected to the first source layer (211-212 Kashima);
Kashima modified by Dutartre does not expressly disclose an insulating spacer surrounding a sidewall of the contact plug.
However, in the same semiconductor device field of endeavor, Kim discloses an insulating spacer (SL a spacer having an insulating material between a common source pattern CSP and the stacks ST in [0044], Fig. 3) surrounding a sidewall (Fig. 3) of the contact plug (CSP-lower a lower portion of a common source pattern in [0044], Fig. 3-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kim’s feature of an insulating spacer surrounding a sidewall of the contact plug to the combination of Kashima and Dutartre to isolate the common source pattern from the gate stack ([0044], Kim).
Regarding Claim 32, Kashima modified by Dutartre and Kim discloses the semiconductor device of claim 31, wherein the contact plug (241-lower, Kashima) and the second part (212, Kashima) are separated by the insulating spacer (SL, Kim).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Choi (US 20190355734 A1) teaches “SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME”. This document is related to a 3D memory device including a source region with three source layers and a source contact line extending through a gate structure.
Lee et al. (US 20160343450 A1) teaches “3-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF”. This document is related to a 3D memory device including a substrate with three well structures and a common source plug extending through a gate structure.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898